专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07326610B2 Process options of forming silicided metal gates for advanced CMOS devices 有权
标题翻译：为先进的CMOS器件形成硅化金属栅的工艺选择
公开(公告)号：US07326610B2
公开(公告)日：2008-02-05
申请号：US11271032
申请日：2005-11-10
申请人： Ricky S. Amos , Douglas A. Buchanan , Cyril Cabral, Jr. , Evgeni P. Gousev , Victor Ku , An Steegen
发明人： Ricky S. Amos , Douglas A. Buchanan , Cyril Cabral, Jr. , Evgeni P. Gousev , Victor Ku , An Steegen
IPC分类号： H01L21/31
CPC分类号： H01L21/823842 , H01L21/76895 , H01L21/823835
摘要： Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds. A second silicide may be employed within the gate. A replacement gate is made from two different metals (dual metal gate replacement) prior to capping with a silicide.
摘要翻译：硅化物通过不同的工艺选择被引入到CMOS器件的栅极区域，用于常规和替代栅极类型工艺。将硅化物放置在栅极本身中，引入硅化物直接与栅极电介质接触，将硅化物作为填充物引入金属栅极顶部，并准备就绪，并将硅化物作为覆盖层引入到多晶硅上或现有的金属门。硅化物用作连接CMOS结构的PFET和NFET器件的选项。该过程保护金属栅极，同时允许源极和漏极硅化物与栅极硅化物不同的硅化物。提供了具有栅极和源极和漏极区域的半导体衬底。栅极电介质层与金属栅极层一起沉积在衬底上。然后用形成在栅极顶部上的硅化物对金属栅极层进行封装，然后继续进行常规的器件形成。可以在栅极内使用第二硅化物。在使用硅化物封盖之前，更换栅极由两种不同的金属（双金属栅极替代）制成。

2. 发明授权

US07029966B2 Process options of forming silicided metal gates for advanced CMOS devices 失效
标题翻译：为先进的CMOS器件形成硅化金属栅的工艺选择
公开(公告)号：US07029966B2
公开(公告)日：2006-04-18
申请号：US10605261
申请日：2003-09-18
申请人： Ricky S. Amos , Douglas A. Buchanan , Cyril Cabral, Jr. , Evgeni P. Gousev , Victor Ku , An Steegen
发明人： Ricky S. Amos , Douglas A. Buchanan , Cyril Cabral, Jr. , Evgeni P. Gousev , Victor Ku , An Steegen
IPC分类号： H01L21/8238 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823842 , H01L21/76895 , H01L21/823835
摘要： Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds. A second silicide may be employed within the gate. A replacement gate is made from two different metals (dual metal gate replacement) prior to capping with a silicide.
摘要翻译：硅化物通过不同的工艺选择被引入到CMOS器件的栅极区域，用于常规和替代栅极类型工艺。将硅化物放置在栅极本身中，引入硅化物直接与栅极电介质接触，将硅化物作为填充物引入金属栅极顶部，并准备就绪，并将硅化物作为覆盖层引入到多晶硅上或现有的金属门。硅化物用作连接CMOS结构的PFET和NFET器件的选项。该过程保护金属栅极，同时允许源极和漏极硅化物与栅极硅化物不同的硅化物。提供了具有栅极和源极和漏极区域的半导体衬底。栅极电介质层与金属栅极层一起沉积在衬底上。然后用形成在栅极顶部上的硅化物对金属栅极层进行封装，然后继续进行常规的器件形成。可以在栅极内使用第二硅化物。在使用硅化物封盖之前，更换栅极由两种不同的金属（双金属栅极替代）制成。

3. 发明授权

US07655557B2 CMOS silicide metal gate integration 失效
标题翻译： CMOS硅化物金属栅极集成
公开(公告)号：US07655557B2
公开(公告)日：2010-02-02
申请号：US12145113
申请日：2008-06-24
申请人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral, Jr. , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
发明人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral, Jr. , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L29/66545 , H01L29/6656
摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
摘要翻译：本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

4. 发明授权

US07411227B2 CMOS silicide metal gate integration 有权
标题翻译： CMOS硅化物金属栅极集成
公开(公告)号：US07411227B2
公开(公告)日：2008-08-12
申请号：US11407313
申请日：2006-04-19
申请人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral, Jr. , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
发明人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral, Jr. , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
IPC分类号： H01L27/10 , H01L29/73
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L29/66545 , H01L29/6656
摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
摘要翻译：本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

5. 发明授权

US07056782B2 CMOS silicide metal gate integration 失效
公开(公告)号：US07056782B2
公开(公告)日：2006-06-06
申请号：US10786901
申请日：2004-02-25
申请人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral, Jr. , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaran Surendra
发明人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral, Jr. , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaran Surendra
IPC分类号： H01L21/8238
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L29/66545 , H01L29/6656
摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

6. 发明申请

US20080254622A1 CMOS SILICIDE METAL GATE INTEGRATION 失效
标题翻译： CMOS硅胶金属门整合
公开(公告)号：US20080254622A1
公开(公告)日：2008-10-16
申请号：US12145113
申请日：2008-06-24
申请人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
发明人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
IPC分类号： H01L21/44
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L29/66545 , H01L29/6656
摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
摘要翻译：本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

7. 发明授权

US08492803B2 Field effect device with reduced thickness gate 有权
标题翻译：具有减小厚度门的场效应装置
公开(公告)号：US08492803B2
公开(公告)日：2013-07-23
申请号：US12274758
申请日：2008-11-20
申请人： Ricky S. Amos , Wesley C. Natzle , Siddhartha Panda , Brian L. Tessier
发明人： Ricky S. Amos , Wesley C. Natzle , Siddhartha Panda , Brian L. Tessier
IPC分类号： H01L29/80 , H01L21/335
CPC分类号： H01L21/28097 , H01L29/66507 , H01L29/6653 , H01L29/66545 , H01L29/66628
摘要： A semiconductor structure is fabricated with reduced gate capacitance by thinning of a gate electrode to provide a reduced thickness gate electrode. The gate electrode is thinned after forming a spacer layer adjoining the gate electrode. In addition, the height of the spacer layer may also be reduced. The spacer layer thus has an enhanced horizontal width desired for locating an intrinsic source/drain with respect to an extension region and in particular, an enhanced horizontal width relative to the spacer height. The reduced thickness gate electrode may be fully silicided to provide decreased gate resistance. A raised source/drain layer may be located upon the intrinsic source/drain region. The raised source/drain layer may have a top surface higher than the reduced thickness gate electrode. In addition, the raised source/drain layer may have a top surface higher than the reduced height spacer layer.
摘要翻译：通过减薄栅电极来制造具有减小的栅极电容的半导体结构，以提供减小厚度的栅电极。在形成与栅电极相邻的间隔层之后，栅电极变薄。此外，间隔层的高度也可以减小。间隔层因此具有相对于延伸区域定位本征源极/漏极所需的增强的水平宽度，特别是相对于间隔物高度的增强的水平宽度。减薄厚度的栅电极可以被完全硅化以提供降低的栅极电阻。升高的源极/漏极层可以位于本征源极/漏极区域上。凸起的源极/漏极层可以具有比缩小的厚度栅电极高的顶表面。此外，隆起的源极/漏极层可以具有高于缩小的高度间隔层的顶表面。

8. 发明授权

US07960798B2 Structure and method to form multilayer embedded stressors 有权
标题翻译：多层嵌入式应激物的结构和方法
公开(公告)号：US07960798B2
公开(公告)日：2011-06-14
申请号：US12618152
申请日：2009-11-13
申请人： Zhijiong Luo , Ricky S. Amos , Nivo Rovedo , Henry K. Utomo
发明人： Zhijiong Luo , Ricky S. Amos , Nivo Rovedo , Henry K. Utomo
IPC分类号： H01L27/088
CPC分类号： H01L29/7848 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L29/1083 , H01L29/165 , H01L29/6656 , H01L29/66636
摘要： A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain regions are typically located. The inventive multilayer stressor includes a first conformal epi semiconductor layer that is undoped or lightly doped and a second epi semiconductor layer that is highly dopant relative to the first epi semiconductor layer. The first and second epi semiconductor layers each have the same lattice constant, which is different from that of the substrate they are embedded in. The structure including the inventive multilayer embedded stressor achieves a good balance between stress proximity and short channel effects, and even eliminates or substantially reduces any possible defects that are typically generated during formation of the deep source/drain regions.
摘要翻译：提供了具有用于在器件沟道区域上诱发应变的半导体结构中的渐变掺杂物分布的多层嵌入式应力器。本发明的多层应力器形成在源极/漏极区域通常位于其中的半导体结构的区域内。本发明的多层应力器包括未掺杂或轻掺杂的第一共形外延半导体层和相对于第一外延半导体层高度掺杂的第二外延半导体层。第一和第二外延半导体层各自具有相同的晶格常数，其不同于嵌入其中的衬底。包括本发明的多层嵌入式应力器的结构在应力接近和短沟道效应之间实现良好的平衡，甚至消除或基本上减少在深源/漏区形成期间通常产生的任何可能的缺陷。

9. 发明申请

US20080006818A1 STRUCTURE AND METHOD TO FORM MULTILAYER EMBEDDED STRESSORS 有权
标题翻译：形成多层嵌入式应力的结构和方法
公开(公告)号：US20080006818A1
公开(公告)日：2008-01-10
申请号：US11423227
申请日：2006-06-09
申请人： Zhijiong Luo , Ricky S. Amos , Nivo Rovedo , Henry K. Utomo
发明人： Zhijiong Luo , Ricky S. Amos , Nivo Rovedo , Henry K. Utomo
IPC分类号： H01L31/00 , H01L29/06
CPC分类号： H01L29/7848 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L29/1083 , H01L29/165 , H01L29/6656 , H01L29/66636
摘要： A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain regions are typically located. The inventive multilayer stressor includes a first conformal epi semiconductor layer that is undoped or lightly doped and a second epi semiconductor layer that is highly dopant relative to the first epi semiconductor layer. The first and second epi semiconductor layers each have the same lattice constant, which is different from that of the substrate they are embedded in. The structure including the inventive multilayer embedded stressor achieves a good balance between stress proximity and short channel effects, and even eliminates or substantially reduces any possible defects that are typically generated during formation of the deep source/drain regions.
摘要翻译：提供了具有用于在器件沟道区域上诱发应变的半导体结构中的渐变掺杂物分布的多层嵌入式应力器。本发明的多层应力器形成在源极/漏极区域通常位于其中的半导体结构的区域内。本发明的多层应力器包括未掺杂或轻掺杂的第一共形外延半导体层和相对于第一外延半导体层高度掺杂的第二外延半导体层。第一和第二外延半导体层各自具有相同的晶格常数，其不同于嵌入其中的衬底。包括本发明的多层嵌入式应力器的结构在应力接近和短沟道效应之间实现良好的平衡，甚至消除或基本上减少在深源/漏区形成期间通常产生的任何可能的缺陷。

10. 发明授权

US06916698B2 High performance CMOS device structure with mid-gap metal gate 失效
标题翻译：高性能CMOS器件结构，具有中间间隙金属栅极
公开(公告)号：US06916698B2
公开(公告)日：2005-07-12
申请号：US10795672
申请日：2004-03-08
申请人： Anda C. Mocuta , Meikei Ieong , Ricky S. Amos , Diane C. Boyd , Dan M. Mocuta , Huajie Chen
发明人： Anda C. Mocuta , Meikei Ieong , Ricky S. Amos , Diane C. Boyd , Dan M. Mocuta , Huajie Chen
IPC分类号： H01L29/423 , H01L21/8238 , H01L27/092 , H01L29/49
CPC分类号： H01L21/823807 , H01L21/823828
摘要： High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.
摘要翻译：公开了具有中间间隙功函数金属栅极的高性能（表面沟道）CMOS器件，其中外延层用于PFET区域的阈值电压Vt调整/减小，用于大的Vt降低（〜500mV），如需要具有中间间隙金属栅极的CMOS器件。本发明提供了使用原位B掺杂外延层或B和C共掺杂外延层的反掺杂，其中C共掺杂提供了额外的自由度以减少B的扩散（也在随后的激活热循环期间））以保持浅的B剖面，这对于提供具有中间间隙金属栅极的表面沟道CMOS器件而言是至关重要的，同时保持良好的短沟道效应。对于具有中间间隙金属栅极的器件，B扩散曲线令人满意地浅，尖锐且具有高B浓度，以在栅极氧化物下提供并保持薄的高掺杂B层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式