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1. 发明授权

US07887711B2 Method for etching chemically inert metal oxides 有权
标题翻译：蚀刻化学惰性金属氧化物的方法
公开(公告)号：US07887711B2
公开(公告)日：2011-02-15
申请号：US10170914
申请日：2002-06-13
申请人： Douglas A. Buchanan , Eduard A. Cartier , Evgeni Gousev , Harald Okorn-Schmidt , Katherine L. Saenger
发明人： Douglas A. Buchanan , Eduard A. Cartier , Evgeni Gousev , Harald Okorn-Schmidt , Katherine L. Saenger
IPC分类号： B44C1/22 , H01L21/00
CPC分类号： H01L21/31122 , Y10S438/924
摘要： A system and method for patterning metal oxide materials in a semiconductor structure. The method comprises a first step of depositing a layer of metal oxide material over a substrate. Then, a patterned mask layer is formed over the metal oxide layer leaving one or more first regions of the metal oxide layer exposed. The exposed first regions of the metal oxide layer are then subjected to an energetic particle bombardment process to thereby damage the first regions of the metal oxide layer. The exposed and damaged first regions of the metal oxide layer are then removed by a chemical etch. Advantageously, the system and method is implemented to provide high-k dielectric materials in small-scale semiconductor devices. Besides using the ion implantation damage (I/I damage) plus wet etch technique to metal oxides (including metal oxides not previously etchable by wet methods), other damage methods including lower energy, plasma-based ion bombardment, may be implemented. Plasma-based ion bombardment typically uses simpler and cheaper tooling, and results in less collateral damage to underlying structures as the damage profile can be more easily localized to the depth of the thin metal oxide film.
摘要翻译：一种在半导体结构中图案化金属氧化物材料的系统和方法。该方法包括在衬底上沉积金属氧化物材料层的第一步骤。然后，在金属氧化物层之上形成图案化掩模层，留下暴露金属氧化物层的一个或多个第一区域。接着对金属氧化物层的暴露的第一区域进行高能粒子轰击处理，从而破坏金属氧化物层的第一区域。然后通过化学蚀刻去除金属氧化物层的暴露和损坏的第一区域。有利地，该系统和方法被实现以在小规模半导体器件中提供高k电介质材料。除了使用离子注入损伤（I / I损伤）以及湿法蚀刻技术对金属氧化物（包括以前不能用湿法蚀刻的金属氧化物）外，还可以实施包括较低能量，基于等离子体的离子轰击等其他损伤方法。基于等离子体的离子轰击通常使用更简单和更便宜的工具，并且导致对下面的结构的较少的附带损伤，因为损伤分布可以更容易地定位于薄金属氧化物膜的深度。

2. 发明授权

US08153514B2 Method of forming metal/high-κ gate stacks with high mobility 有权
标题翻译：金属/高分子金属成型方法移动性高的门栈
公开(公告)号：US08153514B2
公开(公告)日：2012-04-10
申请号：US12187767
申请日：2008-08-07
申请人： Wanda Andreoni , Alessandro C. Callegari , Eduard A. Cartier , Alessandro Curioni , Christopher P. D'Emic , Evgeni Gousev , Michael A. Gribelyuk , Paul C. Jamison , Rajarao Jammy , Dianne L. Lacey , Fenton R. McFeely , Vijay Narayanan , Carlo A. Pignedoli , Joseph F. Shepard, Jr. , Sufi Zafar
发明人： Wanda Andreoni , Alessandro C. Callegari , Eduard A. Cartier , Alessandro Curioni , Christopher P. D'Emic , Evgeni Gousev , Michael A. Gribelyuk , Paul C. Jamison , Rajarao Jammy , Dianne L. Lacey , Fenton R. McFeely , Vijay Narayanan , Carlo A. Pignedoli , Joseph F. Shepard, Jr. , Sufi Zafar
IPC分类号： H01L21/3205
CPC分类号： H01L21/28176 , H01L29/4908 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6656 , H01L29/66575 , H01L29/66772 , H01L29/7833 , H01L29/78684
摘要： The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.
摘要翻译：本发明提供具有高迁移率和低界面电荷的栅叠层结构，以及包括其的半导体器件即金属氧化物半导体场效应晶体管（MOSFET）。在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间。本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（大约800℃）。本发明中使用的高温退火提供了一种栅极叠层结构，其具有约8×10 10电荷/ cm 2或更小的峰值迁移率，约250cm 2 / s或更大的峰迁移率的通过电荷泵浦测量的界面状态密度，以及在大约6.0×10 12反转电荷/ cm 2或更大时基本上没有迁移率降解。

3. 发明申请

US20080293259A1 METHOD OF FORMING METAL/HIGH-k GATE STACKS WITH HIGH MOBILITY 有权
标题翻译：形成具有高移动性的金属/高k栅极堆叠的方法
公开(公告)号：US20080293259A1
公开(公告)日：2008-11-27
申请号：US12187767
申请日：2008-08-07
申请人： Wanda Andreoni , Alessandro C. Callegari , Eduard A. Cartier , Alessandro Curioni , Christopher P. D'Emic , Evgeni Gousev , Michael A. Gribelyuk , Paul C. Jamison , Rajarao Jammy , Dianne L. Lacey , Fenton R. McFeely , Vijay Narayanan , Carlo A. Pignedoli , Joseph F. Shepard, JR. , Sufi Zafar
发明人： Wanda Andreoni , Alessandro C. Callegari , Eduard A. Cartier , Alessandro Curioni , Christopher P. D'Emic , Evgeni Gousev , Michael A. Gribelyuk , Paul C. Jamison , Rajarao Jammy , Dianne L. Lacey , Fenton R. McFeely , Vijay Narayanan , Carlo A. Pignedoli , Joseph F. Shepard, JR. , Sufi Zafar
IPC分类号： H01L21/263
CPC分类号： H01L21/28176 , H01L29/4908 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6656 , H01L29/66575 , H01L29/66772 , H01L29/7833 , H01L29/78684
摘要： The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.
摘要翻译：本发明提供具有高移动性和低界面电荷的栅叠层结构，以及包括其的半导体器件，即金属氧化物半导体场效应晶体管（MOSFET）。在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间。本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（大约800℃）。本发明中使用的高温退火提供了具有大约8×10 10电荷/ cm 2或更小的电荷泵浦的界面状态密度，约250cm 2 / s以上的峰值迁移率和基本上没有约6.0×10 12反相电荷/ cm 2以上的迁移率降解。

4. 发明授权

US06603181B2 MOS device having a passivated semiconductor-dielectric interface 失效
标题翻译： MOS器件具有钝化的半导体 - 电介质界面
公开(公告)号：US06603181B2
公开(公告)日：2003-08-05
申请号：US09760621
申请日：2001-01-16
申请人： Paul M. Solomon , Douglas A. Buchanan , Eduard A. Cartier , Kathryn W. Guarini , Fenton R. McFeely , Huiling Shang , John J. Yourkas
发明人： Paul M. Solomon , Douglas A. Buchanan , Eduard A. Cartier , Kathryn W. Guarini , Fenton R. McFeely , Huiling Shang , John J. Yourkas
IPC分类号： H01L2976
CPC分类号： H01L29/517 , H01L21/263 , H01L21/28079 , H01L29/495 , Y10S438/91
摘要： A MOS structure processed to have a semiconductor-dielectric interface that is passivated to reduce the interface state density. An example is a MOSFET having a gate dielectric on which an electrode is present that is substantially impervious to molecular hydrogen, but sufficiently thin to be pervious to atomic hydrogen, enabling atomic hydrogen to be diffused therethrough into an underlying semiconductor-dielectric interface. Atomic hydrogen diffusion can be achieved by subjecting such an electrode to hydrogen plasma, forming the electrode of an aluminum-tungsten alloy in the presence of hydrogen, and implanting atomic hydrogen into the electrode. The latter two techniques are each followed by an anneal to cause the atomic hydrogen to diffuse through the electrode and into the semiconductor-dielectric interface.
摘要翻译：被处理成具有钝化的半导体 - 电介质界面以降低界面态密度的MOS结构。一个例子是具有栅电介质的MOSFET，其上存在基本上不透分子氢的电极，但是足够薄以能够透过原子氢，使原子氢能够通过其扩散到下面的半导体介电界面中。原子氢扩散可以通过使这样的电极经受氢等离子体，在氢的存在下形成铝 - 钨合金的电极，并将原子氢注入到电极中来实现。后两种技术之后各自进行退火以使原子氢扩散通过电极并进入半导体 - 电介质界面。

5. 发明授权

US06803266B2 Process for passivating the semiconductor-dielectric interface of a MOS device and MOS device formed thereby 失效
标题翻译：钝化MOS器件的半导体介质接口和由此形成的MOS器件的工艺
公开(公告)号：US06803266B2
公开(公告)日：2004-10-12
申请号：US10249184
申请日：2003-03-20
申请人： Paul M. Solomon , Douglas A. Buchanan , Eduard A. Cartier , Kathryn W. Guarini , Fenton R. McFeely , Huiling Shang , John J. Yourkas
发明人： Paul M. Solomon , Douglas A. Buchanan , Eduard A. Cartier , Kathryn W. Guarini , Fenton R. McFeely , Huiling Shang , John J. Yourkas
IPC分类号： H01L21336
CPC分类号： H01L29/517 , H01L21/263 , H01L21/28079 , H01L29/495 , Y10S438/91
摘要： A process for passivating the semiconductor-dielectric interface of a MOS structure to reduce the interface state density to a very low level. A particular example is a MOSFET having a tungsten electrode that in the past has prevented passivation of the underlying semiconductor-dielectric interface to an extent sufficient to reduce the interface state density to less than 5×1010/cm2−eV. Though substantially impervious to molecular hydrogen, thin tungsten layers are shown to be pervious to atomic hydrogen, enabling atomic hydrogen to be diffused through a tungsten electrode into an underlying semiconductor-dielectric interface. Three general approaches are encompassed: forming an aluminum-tungsten electrode stack in the presence of hydrogen so as to store atomic hydrogen between the tungsten and aluminum layers, followed by an anneal to cause the atomic hydrogen to diffuse through the tungsten layer and into the interface; subjecting a tungsten electrode to hydrogen plasma, during which atomic hydrogen diffuses through the electrode and into the semiconductor-dielectric interface; and implanting atomic hydrogen into tungsten electrode, followed by an anneal to cause the atomic hydrogen to diffuse through the electrode and into the semiconductor-dielectric interface.
摘要翻译：一种用于钝化MOS结构的半导体 - 电介质界面以将界面态密度降低到非常低的水平的方法。具体的示例是具有钨电极的MOSFET，其过去已经阻止下面的半导体 - 电介质界面的钝化达到足以将界面态密度降低到小于5×10 10 / cm 2 -eV的程度。虽然基本上不透分子氢，但是显示出薄钨层可以透过原子氢，使原子氢能够通过钨电极扩散到下面的半导体 - 电介质界面。包括三种一般方法：在氢的存在下形成铝 - 钨电极堆叠，以便在钨和铝层之间存储原子氢，随后进行退火，使原子氢扩散通过钨层并进入界面 ; 使钨电极经受氢等离子体，其中原子氢通过电极扩散并进入半导体 - 电介质界面; 并将原子氢注入钨电极中，随后进行退火，使原子氢扩散通过电极并进入半导体 - 电介质界面。

6. 发明授权

US06511873B2 High-dielectric constant insulators for FEOL capacitors 有权
公开(公告)号：US06511873B2
公开(公告)日：2003-01-28
申请号：US09882749
申请日：2001-06-15
申请人： Arne W. Ballantine , Douglas A. Buchanan , Eduard A. Cartier , Douglas D. Coolbaugh , Evgeni P. Gousev , Harald F. Okorn-Schmidt
发明人： Arne W. Ballantine , Douglas A. Buchanan , Eduard A. Cartier , Douglas D. Coolbaugh , Evgeni P. Gousev , Harald F. Okorn-Schmidt
IPC分类号： H01L2100
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L27/0629 , H01L27/0635 , H01L27/0805 , H01L28/55 , H01L28/60 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/94
摘要： Methods of forming front-end-of the line (FEOL) capacitors such as polysilicon-polysilicon capacitors and metal-insulator-silicon capacitors are provided that are capable of incorporating a high-dielectric constant (k of greater than about 8) into the capacitor structure. The inventive methods provide high capacitance/area devices with low series resistance of the top and bottom electrodes for high frequency responses. The inventive methods provide a significant reduction in chip size, especially in analog and mixed-signal applications where large areas of capacitance are used.

7. 发明授权

US06444592B1 Interfacial oxidation process for high-k gate dielectric process integration 有权
标题翻译：用于高k栅介质工艺集成的界面氧化工艺
公开(公告)号：US06444592B1
公开(公告)日：2002-09-03
申请号：US09597765
申请日：2000-06-20
申请人： Arne W. Ballantine , Douglas A. Buchanan , Eduard A. Cartier , Kevin K. Chan , Matthew W. Copel , Christopher P. D'Emic , Evgeni P. Gousev , Fenton Read McFeely , Joseph S. Newbury , Harald F. Okorn-Schmidt , Patrick R. Varekamp , Theodore H. Zabel
发明人： Arne W. Ballantine , Douglas A. Buchanan , Eduard A. Cartier , Kevin K. Chan , Matthew W. Copel , Christopher P. D'Emic , Evgeni P. Gousev , Fenton Read McFeely , Joseph S. Newbury , Harald F. Okorn-Schmidt , Patrick R. Varekamp , Theodore H. Zabel
IPC分类号： H01L21469
CPC分类号： H01L21/31691 , H01L28/56
摘要： A method for integrating a high-k material into CMOS processing schemes is provided. The method includes forming an interfacial oxide, oxynitride and/or nitride layer on a device region of a semiconductor substrate, said interfacial layer having a thickness of less than 10 Å; and (b) forming a high-k dielectric material on said interfacial oxide, oxynitride and/or, nitride layer, said high-k dielectric having a dielectric constant, k, of greater than 8.
摘要翻译：提供了一种将高k材料集成到CMOS处理方案中的方法。该方法包括在半导体衬底的器件区域上形成界面氧化物，氧氮化物和/或氮化物层，所述界面层的厚度小于10埃; 和（b）在所述界面氧化物，氧氮化物和/或氮化物层上形成高k电介质材料，所述高k电介质的介电常数k大于8。

8. 发明申请

US20080017936A1 Semiconductor device structures (gate stacks) with charge compositions 审中-公开
标题翻译：具有电荷组成的半导体器件结构（栅极堆叠）
公开(公告)号：US20080017936A1
公开(公告)日：2008-01-24
申请号：US11477707
申请日：2006-06-29
申请人： Douglas A. Buchanan , Eduard A. Cartier , Kevin K. Chan , Leland Chang , Christopher P. D'Emic , Martin M. Frank , Evgeni Gusev , Jin-Ping Han , Rajarao Jammy , Vamsi K. Paruchuri , Sufi Zafar
发明人： Douglas A. Buchanan , Eduard A. Cartier , Kevin K. Chan , Leland Chang , Christopher P. D'Emic , Martin M. Frank , Evgeni Gusev , Jin-Ping Han , Rajarao Jammy , Vamsi K. Paruchuri , Sufi Zafar
IPC分类号： H01L29/94 , H01L29/76 , H01L31/00
CPC分类号： H01L21/823857 , H01L21/28167 , H01L21/28194 , H01L29/51 , H01L29/513 , H01L29/78
摘要： A semiconductor structure, particularly a gate stack, useful in field effect transistors (FETs) in which the threshold voltage thereof is controlled by introducing a fixed spatial distribution of electric charge density to the gate dielectric material and a method of forming the same are provided. nFETs and/or pFETs structures are disclosed. In accordance with the present invention, the fixed spatial distribution of electric charge density of the gate stack or FET denotes an electrical charge density that occupies space which remains substantially constant as a function of time under device operation conditions and is non-zero at least at one location within the dielectric material or at its interface with the channel, gate electrode, spacer, or any other structural elements of the device.
摘要翻译：提供了一种半导体结构，特别是栅极堆叠，其中通过向栅极电介质材料引入电荷密度的固定空间分布来控制其阈值电压的场效应晶体管（FET）及其形成方法。公开了nFET和/或pFET结构。根据本发明，栅极堆叠或FET的电荷密度的固定空间分布表示占空间的电荷密度，其在器件操作条件下作为时间的函数保持基本上恒定，并且至少在电介质材料内的一个位置，或其与沟道，栅电极，间隔物或器件的任何其它结构元件的界面。

9. 发明授权

US06958506B2 High-dielectric constant insulators for feol capacitors 有权
标题翻译：高介电常数绝缘子
公开(公告)号：US06958506B2
公开(公告)日：2005-10-25
申请号：US10688508
申请日：2003-10-17
申请人： Evgeni P. Gousev , Harald F. Okorn-Schmidt , Arne W. Ballantine , Douglas A. Buchanan , Eduard A. Cartier , Douglas D. Coolbaugh
发明人： Evgeni P. Gousev , Harald F. Okorn-Schmidt , Arne W. Ballantine , Douglas A. Buchanan , Eduard A. Cartier , Douglas D. Coolbaugh
IPC分类号： H01L29/73 , H01L21/02 , H01L21/28 , H01L21/331 , H01L21/822 , H01L21/8222 , H01L21/8234 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/08 , H01L29/51 , H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L27/0629 , H01L27/0635 , H01L27/0805 , H01L28/55 , H01L28/60 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/94
摘要： Methods of forming front-end-of the line (FEOL) capacitors such as polysilicon-polysilicon capacitors and metal-insulator-silicon capacitors are provided that are capable of incorporating a high-dielectric constant (k of greater than about 8) into the capacitor structure. The inventive methods provide high capacitance/area devices with low series resistance of the top and bottom electrodes for high frequency responses. The inventive methods provide a significant reduction in chip size, especially in analog and mixed-signal applications where large areas of capacitance are used.
摘要翻译：提供了形成前端的方法（FEOL）电容器，例如多晶硅 - 多晶硅电容器和金属 - 绝缘体 - 硅电容器，其能够将高介电常数（k大于约8）并入电容器结构体。本发明的方法提供了用于高频响应的顶部和底部电极具有低串联电阻的高电容/面积器件。本发明的方法提供了芯片尺寸的显着降低，特别是在使用大面积电容的模拟和混合信号应用中。

10. 发明授权

US06667207B2 High-dielectric constant insulators for FEOL capacitors 失效
标题翻译：用于FEOL电容器的高介电常数绝缘子
公开(公告)号：US06667207B2
公开(公告)日：2003-12-23
申请号：US10246110
申请日：2002-09-18
申请人： Arne W. Ballantine , Douglas A. Buchanan , Eduard A. Cartier , Douglas D. Coolbaugh , Evgeni P. Gousev , Harald F. Okorn-Schmidt
发明人： Arne W. Ballantine , Douglas A. Buchanan , Eduard A. Cartier , Douglas D. Coolbaugh , Evgeni P. Gousev , Harald F. Okorn-Schmidt
IPC分类号： H01L218249
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L27/0629 , H01L27/0635 , H01L27/0805 , H01L28/55 , H01L28/60 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/94
摘要： Methods of forming front-end-of the line (FEOL) capacitors such as polysilicon-polysilicon capacitors and metal-insulator-silicon capacitors are provided that are capable of incorporating a high-dielectric constant (k of greater than about 8) into the capacitor structure. The inventive methods provide high capacitance/area devices with low series resistance of the top and bottom electrodes for high frequency responses. The inventive methods provide a significant reduction in chip size, especially in analog and mixed-signal applications where large areas of capacitance are used.
摘要翻译：提供了形成前端的方法（FEOL）电容器，例如多晶硅 - 多晶硅电容器和金属 - 绝缘体 - 硅电容器，其能够将高介电常数（k大于约8）并入电容器结构体。本发明的方法提供了用于高频响应的顶部和底部电极具有低串联电阻的高电容/面积器件。本发明的方法提供了芯片尺寸的显着降低，特别是在使用大面积电容的模拟和混合信号应用中。

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