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    • 4. 发明授权
    • Heterojunction FET with doubly-doped channel
    • 具有双掺杂沟道的异质结FET
    • US4673959A
    • 1987-06-16
    • US686661
    • 1984-12-27
    • Yasuhiro ShirakiYoshifumi KatayamaYoshimasa MurayamaMakoto MoriokaYasushi SawadaTomoyoshi MishimaTakao KurodaEiichi Maruyama
    • Yasuhiro ShirakiYoshifumi KatayamaYoshimasa MurayamaMakoto MoriokaYasushi SawadaTomoyoshi MishimaTakao KurodaEiichi Maruyama
    • H01L29/812H01L21/338H01L29/205H01L29/423H01L29/778H01L29/80
    • H01L29/42316H01L29/7781H01L29/7786
    • There is disclosed a semiconductor device comprising at least first and second semiconductor layers positioned to form a hetero-junction therebetween, such a hetero-junction being adapted to form a channel, means for controlling carriers, and source and drain areas on opposite edges of the channel, wherein the first and second semiconductor layers formed between the source and drain regions have an area containing only 10.sup.16 cm.sup.-3 or less of an impurity; the first semiconductor layer has a wider forbidden band than that of the second semiconductor layer; and further including at least one semiconductor layer having a higher activation efficiency of impurities than that of the first semiconductor layer, with such at least one semiconductor layer being located on the side of the first semiconductor layer not in contact with the second semiconductor layer. A multi-quantum well structure may be used as the higher impurity activation efficiency semiconductor layer. The electrical resistance in the semiconductor area constituting the source and drain regions can be lowered by utilizing such a higher impurity activation efficiency semiconductor layer.
    • 公开了一种半导体器件,其至少包括第一和第二半导体层,该第一和第二半导体层被定位以在它们之间形成异质结,这样的异质结适于形成沟道,用于控制载流子的装置,以及在其的相对边缘上的源极和漏极区域 沟道,其中形成在源区和漏区之间的第一和第二半导体层具有仅含有1016cm-3或更小的杂质的面积; 第一半导体层具有比第二半导体层更宽的禁带; 并且还包括至少一个具有比第一半导体层高的杂质活化效率的半导体层,这样的至少一个半导体层位于不与第二半导体层接触的第一半导体层的一侧。 可以使用多量子阱结构作为较高的杂质活化效率半导体层。 通过利用这种较高的杂质活化效率的半导体层,可以降低构成源区和漏区的半导体区的电阻。