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1. 发明申请

US20060065926A1 Insulated gate semiconductor device and manufacturing method of the same 有权
标题翻译：绝缘栅半导体器件及其制造方法相同
公开(公告)号：US20060065926A1
公开(公告)日：2006-03-30
申请号：US11230538
申请日：2005-09-21
申请人： Hirotoshi Kubo , Junichiro Tojo , Hiroaki Saito , Masahito Onda , Satoshi Iwata , Masamichi Yanagida
发明人： Hirotoshi Kubo , Junichiro Tojo , Hiroaki Saito , Masahito Onda , Satoshi Iwata , Masamichi Yanagida
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/66734
摘要： A capacity layer is formed of non-doped polysilicon. Unlike capacity layers formed of an oxide film, generation of seams and the like can be suppressed and thereby a stable capacity layer can be formed. Moreover, polysilicon used as a capacity layer may be doped polysilicon, and an oxide film formed on the surface of the polysilicon also serves as a capacity film. Thus, provision of an insulated gate device featuring low capacity is made possible.
摘要翻译：电容层由非掺杂多晶硅形成。与由氧化膜形成的容量层不同，可以抑制接缝等的产生，从而可以形成稳定的电容层。此外，用作电容层的多晶硅可以是掺杂多晶硅，并且形成在多晶硅表面上的氧化膜也用作容量膜。因此，提供具有低容量的绝缘栅极器件成为可能。

2. 发明申请

US20060054970A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060054970A1
公开(公告)日：2006-03-16
申请号：US11220406
申请日：2005-09-07
申请人： Masamichi Yanagida , Hirotoshi Kubo , Junichiro Tojo , Hiraoki Saito , Masahito Onda
发明人： Masamichi Yanagida , Hirotoshi Kubo , Junichiro Tojo , Hiraoki Saito , Masahito Onda
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/66734
摘要： In an embodiment of the present invention, after trenches, a gate oxide film and gate electrodes are formed, a channel layer is formed by plural high-acceleration ion implantations where acceleration voltages are different with one another. The channel layer is an impurity implanted layer on which diffusion by a heat treatment is not performed. The channel layer is allowed to have its impurity concentration substantially uniform in a depth-wise direction of the trenches, by implanting ions of the impurity at plural different times by use of a high-acceleration ion implantation system. Since a second region having almost no influence on a characteristic of the channel layer can be reduced, the channel layer having a minimum necessary depth can be obtained. The trenches are thus made shallow, and accordingly a capacitance can be reduced. Furthermore, an on resistance can be made lower by making an epitaxial layer thinner.
摘要翻译：在本发明的实施例中，在沟槽之后，形成栅氧化膜和栅电极，通过加速电压彼此不同的多个高加速度离子注入形成沟道层。沟道层是不进行通过热处理的扩散的杂质注入层。通过使用高加速度离子注入系统，在多个不同时间通过注入杂质的离子，允许沟道层在沟槽的深度方向上具有基本均匀的杂质浓度。由于可以减少对沟道层的特性几乎没有影响的第二区域，所以可以获得具有最小所需深度的沟道层。因此，沟槽变浅，因此可以减小电容。此外，通过使外延层更薄，可以使导通电阻更低。

3. 发明授权

US06967139B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06967139B2
公开(公告)日：2005-11-22
申请号：US10893223
申请日：2004-07-19
申请人： Makoto Oikawa , Hiroki Etou , Hirotoshi Kubo , Shouji Miyahara
发明人： Makoto Oikawa , Hiroki Etou , Hirotoshi Kubo , Shouji Miyahara
IPC分类号： H01L29/06 , H01L21/336 , H01L29/10 , H01L29/423 , H01L29/78 , H01L21/8234
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/1095 , H01L29/4236 , H01L29/66348 , H01L29/66734 , H01L29/7397 , H01L29/7813
摘要： In a conventional power MOSFET, an electric field concentration occurs at a gate electrode bottom portion on the outermost periphery of an operating area, thereby causing a deterioration in high voltage strength between the drain and the source, or between the collector and emitter. In this invention, a trench at the outermost periphery of an operating area is shallower than trenches of the operating area. Thereby, the electric field concentration at the gate electrode bottom portion on the outermost periphery of the operating area is relieved, and a deterioration in high voltage strength between the drain and source is suppressed. Furthermore, by narrowing the outermost peripheral trench aperture portion, trenches different in depth can be formed by an identical step.
摘要翻译：在常规功率MOSFET中，在操作区域的最外周的栅电极底部产生电场浓度，从而导致漏极与源极之间或集电极与发射极之间的高电压强度的劣化。在本发明中，操作区域的最外周的沟槽比操作区域的沟槽浅。由此，减轻了操作区域的最外周的栅电极底部的电场浓度，并且抑制了漏极与源极之间的高电压强度的劣化。此外，通过使最外周沟槽开口部分变窄，可以通过相同的步骤形成深度不同的沟槽。

4. 发明申请

US20050255706A1 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20050255706A1
公开(公告)日：2005-11-17
申请号：US11123248
申请日：2005-05-06
申请人： Hiroyasu Ishida , Hirotoshi Kubo , Shouji Miyahara , Masato Onda
发明人： Hiroyasu Ishida , Hirotoshi Kubo , Shouji Miyahara , Masato Onda
IPC分类号： H01L21/28 , H01L21/30 , H01L21/31 , H01L21/322 , H01L21/336 , H01L21/469 , H01L21/768 , H01L21/8234 , H01L27/10 , H01L29/417 , H01L29/45 , H01L29/74 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/3003 , H01L21/76886 , H01L21/823487 , H01L29/456
摘要： In a MOSFET, after an element region is formed, a wiring layer is formed subsequently to a barrier metal layer, and hydrogen annealing is performed. However, in the case of an n-channel MOSFET, a threshold voltage is lowered due to an occlusion characteristic of the barrier metal layer. Thus, an increased impurity concentration in a channel layer causes a problem that reduction in an on-resistance is inhibited. According to the present invention, after a barrier metal layer is formed, an opening is provided in the barrier metal layer on an interlayer insulating film, and hydrogen annealing treatment is performed after a wiring layer is formed. Thus, an amount of hydrogen which reaches a substrate is further increased, and lowering of a threshold voltage is suppressed. Moreover, since an impurity concentration in a channel layer can be lowered, an on-resistance is reduced.
摘要翻译：在MOSFET中，在形成元件区之后，在阻挡金属层的后面形成布线层，进行氢退火。然而，在n沟道MOSFET的情况下，由于阻挡金属层的遮挡特性，阈值电压降低。因此，通道层中杂质浓度的增加引起导通电阻的降低被抑制的问题。根据本发明，在形成阻挡金属层之后，在层间绝缘膜上的阻挡金属层中设置开口，在形成布线层之后进行氢退火处理。因此，到达基板的氢的量进一步增加，并且抑制了阈值电压的降低。此外，由于可以降低沟道层中的杂质浓度，所以导通电阻降低。

5. 发明申请

US20080237808A1 Semiconductor Device and Method of Manufacturing the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080237808A1
公开(公告)日：2008-10-02
申请号：US12134861
申请日：2008-06-06
申请人： Hirotoshi Kubo , Yukari Shirahata , Shigehito Matsumoto , Masamichi Yamamuro , Koujiro Kameyama , Mitsuo Umemoto
发明人： Hirotoshi Kubo , Yukari Shirahata , Shigehito Matsumoto , Masamichi Yamamuro , Koujiro Kameyama , Mitsuo Umemoto
IPC分类号： H01L23/538 , H05K1/18
CPC分类号： H01L29/7322 , H01L23/3128 , H01L23/481 , H01L23/4824 , H01L23/4951 , H01L23/49562 , H01L24/05 , H01L24/06 , H01L24/17 , H01L24/29 , H01L24/48 , H01L24/73 , H01L24/91 , H01L29/1004 , H01L29/41708 , H01L29/66272 , H01L2224/0401 , H01L2224/04042 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/13099 , H01L2224/32225 , H01L2224/32245 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/73265 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/0781 , H01L2924/12033 , H01L2924/12036 , H01L2924/12041 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/351 , H01L2924/00012 , H01L2924/00 , H01L2224/45099
摘要： Disclosed is a semiconductor device in which emitter pad electrodes connected to an active region, collector and base pad electrodes are formed on a surface of a semiconductor substrate. Furthermore, on a back surface of the semiconductor substrate, a backside electrode is formed. Moreover, the emitter pad electrodes connected to a grounding potential are connected to the backside electrode through feedthrough electrodes penetrating the semiconductor substrate in a thickness direction.
摘要翻译：公开了一种半导体器件，其中连接到有源区，集电极和基极焊盘电极的发射极焊盘电极形成在半导体衬底的表面上。此外，在半导体衬底的背面形成有背面电极。此外，连接到接地电位的发射极焊盘电极通过穿过半导体衬底的厚度方向的穿通电极而连接到背面电极。

6. 发明授权

US07413954B2 Insulated gate semiconductor device and manufacturing method of the same 有权
标题翻译：绝缘栅半导体器件及其制造方法相同
公开(公告)号：US07413954B2
公开(公告)日：2008-08-19
申请号：US11230538
申请日：2005-09-21
申请人： Hirotoshi Kubo , Junichiro Tojo , Hiroaki Saito , Masahito Onda , Satoshi Iwata , Masamichi Yanagida
发明人： Hirotoshi Kubo , Junichiro Tojo , Hiroaki Saito , Masahito Onda , Satoshi Iwata , Masamichi Yanagida
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/66734
摘要： A capacity layer is formed of non-doped polysilicon. Unlike capacity layers formed of an oxide film, generation of seams and the like can be suppressed and thereby a stable capacity layer can be formed. Moreover, polysilicon used as a capacity layer may be doped polysilicon, and an oxide film formed on the surface of the polysilicon also serves as a capacity film. Thus, provision of an insulated gate device featuring low capacity is made possible.
摘要翻译：电容层由非掺杂多晶硅形成。与由氧化膜形成的容量层不同，可以抑制接缝等的产生，从而可以形成稳定的电容层。此外，用作电容层的多晶硅可以是掺杂多晶硅，并且形成在多晶硅表面上的氧化膜也用作容量膜。因此，提供具有低容量的绝缘栅极器件成为可能。

7. 发明授权

US07320916B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07320916B2
公开(公告)日：2008-01-22
申请号：US10952381
申请日：2004-09-29
申请人： Hirotoshi Kubo , Yasuhiro Igarashi , Masahiro Shibuya
发明人： Hirotoshi Kubo , Yasuhiro Igarashi , Masahiro Shibuya
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/456
摘要： When Ti as a barrier metal layer is brought into contact with a diffusion region of boron provided on a surface of a silicon substrate, there is a problem that boron is absorbed by titanium silicide, and contact resistance is increased. Although there is a method of additionally implanting boron whose amount is equal to the amount of boron absorbed by titanium silicide, there has been a problem that when boron is additionally implanted into, for example, a source region in a p-channel type, the additionally added boron is diffused deeply at the diffusion step, and characteristics are deteriorated. According to the invention, after formation of an element region, boron is additionally implanted into the whole surface at a dosage of about 10% of an element region, and is activated in the vicinity of a surface of a silicon substrate by an alloying process of a barrier metal layer. By this, a specified concentration profile of the element region is kept, and the impurity concentration only in the vicinity of the surface can be raised. Accordingly, even if boron is absorbed by titanium silicide, a specified boron concentration can be kept in the element region, and the increase of contact resistance can be suppressed.
摘要翻译：当作为阻挡金属层的Ti与设置在硅衬底的表面上的硼的扩散区域接触时，存在硼被硅化钛吸收的问题，并且接触电阻增加。虽然存在另外注入硼量的方法，其量等于由硅化钛吸收的硼的量，但是存在如下问题：当将硼另外注入例如p沟道型的源极区时，在扩散步骤中另外添加硼深度扩散，特性劣化。根据本发明，在形成元件区域之后，以元素区域的约10％的剂量将硼额外地注入整个表面，并且通过合金化工艺在硅衬底的表面附近活化阻挡金属层。由此，保持元件区域的规定的浓度分布，仅能够提高表面附近的杂质浓度。因此，即使硼被硅化钛吸收，也可以在元件区域中保持规定的硼浓度，能够抑制接触电阻的增加。

8. 发明授权

US07230300B2 Semiconductor device with peripheral trench 有权
标题翻译：具有外围沟槽的半导体器件
公开(公告)号：US07230300B2
公开(公告)日：2007-06-12
申请号：US10929727
申请日：2004-08-31
申请人： Masahito Onda , Hirotoshi Kubo , Shouji Miyahara , Hiroyasu Ishida
发明人： Masahito Onda , Hirotoshi Kubo , Shouji Miyahara , Hiroyasu Ishida
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7811 , H01L29/407 , H01L29/7813 , Y10S257/908
摘要： Conventional power MOSFETs enables prevention of an inversion in a surrounding region surrounding the outer periphery of an element region by a wide annular layer and a wide sealed metal. Since, resultantly, the area of the surrounding region is large, increase in the element region has been restrained. A semiconductor device is hereby provided which has an inversion prevention region containing an MIS (MOS) structure. The width of polysilicon for the inversion prevention region is large enough to prevent an inversion since the area of an oxide film can be increased by the depth of the trench. By this, leakage current can be reduced even though the area of the region surrounding the outer periphery of the element region is not enlarged. In addition, since the element region is enlarged, on-state resistance of the MOSFET can be reduced.
摘要翻译：常规的功率MOSFET能够防止围绕元件区域的外围的周围区域由宽的环形层和宽的密封金属引起的反转。因此，由于周边地区的面积大，元素区域的增加受到限制。因此提供了具有包含MIS（MOS）结构的反转防止区域的半导体器件。用于防反转区域的多晶硅的宽度足够大以防止由于沟槽的深度增加氧化膜的面积而导致的反转。由此，即使围绕元件区域的外周的区域的面积没有扩大，也可以减小泄漏电流。此外，由于元件区域被扩大，MOSFET的导通电阻可以降低。

9. 发明申请

US20060220178A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060220178A1
公开(公告)日：2006-10-05
申请号：US11392802
申请日：2006-03-28
申请人： Hirotoshi Kubo , Yukari Shirahata , Shigehito Matsumoto , Masamichi Yamamuro , Koujiro Kameyama , Mitsuo Umemoto
发明人： Hirotoshi Kubo , Yukari Shirahata , Shigehito Matsumoto , Masamichi Yamamuro , Koujiro Kameyama , Mitsuo Umemoto
IPC分类号： H01L29/00
CPC分类号： H01L29/7322 , H01L23/3128 , H01L23/481 , H01L23/4824 , H01L23/4951 , H01L23/49562 , H01L24/05 , H01L24/06 , H01L24/17 , H01L24/29 , H01L24/48 , H01L24/73 , H01L24/91 , H01L29/1004 , H01L29/41708 , H01L29/66272 , H01L2224/0401 , H01L2224/04042 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/13099 , H01L2224/32225 , H01L2224/32245 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/73265 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/0781 , H01L2924/12033 , H01L2924/12036 , H01L2924/12041 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/351 , H01L2924/00012 , H01L2924/00 , H01L2224/45099
摘要： Disclosed is a semiconductor device in which emitter pad electrodes connected to an active region, collector and base pad electrodes are formed on a surface of a semiconductor substrate. Furthermore, on a back surface of the semiconductor substrate, a backside electrode is formed. Moreover, the emitter pad electrodes connected to a grounding potential are connected to the backside electrode through feedthrough electrodes penetrating the semiconductor substrate in a thickness direction.
摘要翻译：公开了一种半导体器件，其中连接到有源区，集电极和基极焊盘电极的发射极焊盘电极形成在半导体衬底的表面上。此外，在半导体衬底的背面形成有背面电极。此外，连接到接地电位的发射极焊盘电极通过穿过半导体衬底的厚度方向的穿通电极而连接到背面电极。

10. 发明授权

US06939776B2 Semiconductor device and a method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06939776B2
公开(公告)日：2005-09-06
申请号：US09988272
申请日：2001-11-19
申请人： Hirotoshi Kubo , Masanao Kitagawa , Masahito Onda , Hiroaki Saito , Eiichiroh Kuwako
发明人： Hirotoshi Kubo , Masanao Kitagawa , Masahito Onda , Hiroaki Saito , Eiichiroh Kuwako
IPC分类号： H01L21/336 , H01L29/10 , H01L29/423 , H01L29/78 , H01L21/76
CPC分类号： H01L29/7802 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A power MOSFET comprises: a semiconductor substrate 21 of a first conduction type; a drain layer 22 of the first conduction type and formed on a surface layer of the substrate; a gate insulating film 25 formed in a partial region on the drain layer 22; a gate electrode 26 formed on the gate insulating film 25; an insulating film 27 formed on the gate electrode; a side wall insulator 28 formed on side walls of the gate insulating film 25, the gate electrode 26, and the insulating film 27; a recess formed on the drain layer 22 and in a region other than a region where the gate electrode 25 and the side wall insulator 28 are formed; a channel layer 23 of a second conduction type opposite to the first conduction type and formed in a range from the region where the recess is formed to a vicinity of the region where the gate electrode 26 is formed; a source region layer 24 of the one conduction type and formed on the channel layer 23 outside the recess; and a wiring layer 29 formed to cover the channel layer 23 which is exposed through the recess, the side wall insulator 28, and the insulating film.
摘要翻译：功率MOSFET包括：第一导电类型的半导体衬底21; 第一导电类型的漏极层22，并形成在衬底的表面层上; 形成在漏极层22的局部区域中的栅极绝缘膜25; 形成在栅极绝缘膜25上的栅电极26; 形成在栅电极上的绝缘膜27; 形成在栅极绝缘膜25，栅电极26和绝缘膜27的侧壁上的侧壁绝缘体28; 在漏极层22上形成的凹部和形成有栅电极25和侧壁绝缘体28的区域以外的区域; 与第一导电型相反的第二导电类型的沟道层23形成在从形成凹部的区域到形成栅电极26的区域附近的范围内; 一个导电类型的源极区24，并形成在凹槽外部的沟道层23上; 以及形成为覆盖通过凹部暴露的沟道层23，侧壁绝缘体28和绝缘膜的布线层29。

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