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1. 发明授权

US07413954B2 Insulated gate semiconductor device and manufacturing method of the same 有权
标题翻译：绝缘栅半导体器件及其制造方法相同
公开(公告)号：US07413954B2
公开(公告)日：2008-08-19
申请号：US11230538
申请日：2005-09-21
申请人： Hirotoshi Kubo , Junichiro Tojo , Hiroaki Saito , Masahito Onda , Satoshi Iwata , Masamichi Yanagida
发明人： Hirotoshi Kubo , Junichiro Tojo , Hiroaki Saito , Masahito Onda , Satoshi Iwata , Masamichi Yanagida
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/66734
摘要： A capacity layer is formed of non-doped polysilicon. Unlike capacity layers formed of an oxide film, generation of seams and the like can be suppressed and thereby a stable capacity layer can be formed. Moreover, polysilicon used as a capacity layer may be doped polysilicon, and an oxide film formed on the surface of the polysilicon also serves as a capacity film. Thus, provision of an insulated gate device featuring low capacity is made possible.
摘要翻译：电容层由非掺杂多晶硅形成。与由氧化膜形成的容量层不同，可以抑制接缝等的产生，从而可以形成稳定的电容层。此外，用作电容层的多晶硅可以是掺杂多晶硅，并且形成在多晶硅表面上的氧化膜也用作容量膜。因此，提供具有低容量的绝缘栅极器件成为可能。

2. 发明申请

US20060065926A1 Insulated gate semiconductor device and manufacturing method of the same 有权
标题翻译：绝缘栅半导体器件及其制造方法相同
公开(公告)号：US20060065926A1
公开(公告)日：2006-03-30
申请号：US11230538
申请日：2005-09-21
申请人： Hirotoshi Kubo , Junichiro Tojo , Hiroaki Saito , Masahito Onda , Satoshi Iwata , Masamichi Yanagida
发明人： Hirotoshi Kubo , Junichiro Tojo , Hiroaki Saito , Masahito Onda , Satoshi Iwata , Masamichi Yanagida
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/66734
摘要： A capacity layer is formed of non-doped polysilicon. Unlike capacity layers formed of an oxide film, generation of seams and the like can be suppressed and thereby a stable capacity layer can be formed. Moreover, polysilicon used as a capacity layer may be doped polysilicon, and an oxide film formed on the surface of the polysilicon also serves as a capacity film. Thus, provision of an insulated gate device featuring low capacity is made possible.
摘要翻译：电容层由非掺杂多晶硅形成。与由氧化膜形成的容量层不同，可以抑制接缝等的产生，从而可以形成稳定的电容层。此外，用作电容层的多晶硅可以是掺杂多晶硅，并且形成在多晶硅表面上的氧化膜也用作容量膜。因此，提供具有低容量的绝缘栅极器件成为可能。

3. 发明申请

US20070166905A1 Method of manufacturing semiconductor device with trench 审中-公开
标题翻译：制造具有沟槽的半导体器件的方法
公开(公告)号：US20070166905A1
公开(公告)日：2007-07-19
申请号：US11709147
申请日：2007-02-22
申请人： Masamichi Yanagida , Hirotoshi Kubo , Junichiro Tojo , Hiroaki Saito , Masahito Onda
发明人： Masamichi Yanagida , Hirotoshi Kubo , Junichiro Tojo , Hiroaki Saito , Masahito Onda
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/66734
摘要： In an embodiment of the present invention, after trenches, a gate oxide film and gate electrodes are formed, a channel layer is formed by plural high-acceleration ion implantations where acceleration voltages are different with one another. The channel layer is an impurity implanted layer on which diffusion by a heat treatment is not performed. The channel layer is allowed to have its impurity concentration substantially uniform in a depth-wise direction of the trenches, by implanting ions of the impurity at plural different times by use of a high-acceleration ion implantation system. Since a second region having almost no influence on a characteristic of the channel layer can be reduced, the channel layer having a minimum necessary depth can be obtained. The trenches are thus made shallow, and accordingly a capacitance can be reduced. Furthermore, an on resistance can be made lower by making an epitaxial layer thinner.
摘要翻译：在本发明的实施例中，在沟槽之后，形成栅氧化膜和栅电极，通过加速电压彼此不同的多个高加速度离子注入形成沟道层。沟道层是不进行通过热处理的扩散的杂质注入层。通过使用高加速度离子注入系统，在多个不同时间通过注入杂质的离子，允许沟道层在沟槽的深度方向上具有基本均匀的杂质浓度。由于可以减少对沟道层的特性几乎没有影响的第二区域，所以可以获得具有最小所需深度的沟道层。因此，沟槽变浅，因此可以减小电容。此外，通过使外延层更薄，可以使导通电阻更低。

4. 发明申请

US20060054970A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060054970A1
公开(公告)日：2006-03-16
申请号：US11220406
申请日：2005-09-07
申请人： Masamichi Yanagida , Hirotoshi Kubo , Junichiro Tojo , Hiraoki Saito , Masahito Onda
发明人： Masamichi Yanagida , Hirotoshi Kubo , Junichiro Tojo , Hiraoki Saito , Masahito Onda
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/66734
摘要： In an embodiment of the present invention, after trenches, a gate oxide film and gate electrodes are formed, a channel layer is formed by plural high-acceleration ion implantations where acceleration voltages are different with one another. The channel layer is an impurity implanted layer on which diffusion by a heat treatment is not performed. The channel layer is allowed to have its impurity concentration substantially uniform in a depth-wise direction of the trenches, by implanting ions of the impurity at plural different times by use of a high-acceleration ion implantation system. Since a second region having almost no influence on a characteristic of the channel layer can be reduced, the channel layer having a minimum necessary depth can be obtained. The trenches are thus made shallow, and accordingly a capacitance can be reduced. Furthermore, an on resistance can be made lower by making an epitaxial layer thinner.
摘要翻译：在本发明的实施例中，在沟槽之后，形成栅氧化膜和栅电极，通过加速电压彼此不同的多个高加速度离子注入形成沟道层。沟道层是不进行通过热处理的扩散的杂质注入层。通过使用高加速度离子注入系统，在多个不同时间通过注入杂质的离子，允许沟道层在沟槽的深度方向上具有基本均匀的杂质浓度。由于可以减少对沟道层的特性几乎没有影响的第二区域，所以可以获得具有最小所需深度的沟道层。因此，沟槽变浅，因此可以减小电容。此外，通过使外延层更薄，可以使导通电阻更低。

5. 发明授权

US08018031B2 MOS transistors formed on the front and back surface of a semiconductor substrate 有权
标题翻译：形成在半导体衬底的前表面和后表面上的MOS晶体管
公开(公告)号：US08018031B2
公开(公告)日：2011-09-13
申请号：US12128230
申请日：2008-05-28
申请人： Masamichi Yanagida
发明人： Masamichi Yanagida
IPC分类号： H01L27/07
CPC分类号： H01L27/0694
摘要： The invention realizes low on-resistance and high current flow in a semiconductor device in which a current flows in a thickness direction of a semiconductor substrate. A first MOS transistor having first gate electrodes and first source layers is formed on a front surface of a semiconductor substrate, and a second MOS transistor having second gate electrodes and second source layers is formed on a back surface thereof. A drain electrode connected to the semiconductor substrate, a first source electrode connected to the first source layers, a second source electrode connected to the second source layers, and a first penetration hole penetrating the semiconductor substrate are further formed. A first wiring connecting the first source electrode and the second source electrode is formed in the first penetration hole. The semiconductor substrate serves as a common drain region of the first and second MOS transistors.
摘要翻译：本发明实现了电流在半导体衬底的厚度方向上流动的半导体器件中的低导通电阻和高电流。具有第一栅电极和第一源极层的第一MOS晶体管形成在半导体衬底的前表面上，并且在其后表面上形成具有第二栅电极和第二源极层的第二MOS晶体管。连接到半导体衬底的漏电极，连接到第一源极的第一源电极，连接到第二源极的第二源极和穿透半导体衬底的第一穿透孔进一步形成。连接第一源极和第二源电极的第一布线形成在第一贯通孔中。半导体衬底用作第一和第二MOS晶体管的公共漏极区域。

6. 发明申请

US20060118866A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20060118866A1
公开(公告)日：2006-06-08
申请号：US11274481
申请日：2005-11-16
申请人： Masamichi Yanagida , Tadao Mandai
发明人： Masamichi Yanagida , Tadao Mandai
IPC分类号： H01L29/76
CPC分类号： H01L29/7825 , H01L27/0266 , H01L29/0696 , H01L29/41758 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16245 , H01L2924/00014 , H01L2924/13091 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： In a preferred embodiment of the present invention, first MOS transistors connected to first source electrodes and second MOS transistors connected to second source electrodes are arranged alternately next to each other on one chip. Different potentials are applied respectively to the first source electrodes and to the second source electrodes, and both of the MOS transistors are controlled with respect to an ON or OFF state by one gate terminal. Currents flow along surroundings of trenches, whereby on-resistance is reduced.
摘要翻译：在本发明的优选实施例中，连接到第一源电极的第一MOS晶体管和连接到第二源极的第二MOS晶体管在一个芯片上彼此交替布置。分别对第一源极和第二源电极施加不同的电位，并且通过一个栅极端子相对于导通或截止状态来控制两个MOS晶体管。电流沿着沟槽周围流动，从而降低了导通电阻。

7. 发明申请

US20070215938A1 Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20070215938A1
公开(公告)日：2007-09-20
申请号：US11724330
申请日：2007-03-15
申请人： Masamichi Yanagida , Koujiro Kameyama , Kikuo Okada
发明人： Masamichi Yanagida , Koujiro Kameyama , Kikuo Okada
IPC分类号： H01L29/94
CPC分类号： H01L29/7802 , H01L29/0653 , H01L29/0657 , H01L29/0696 , H01L29/0834 , H01L29/0886 , H01L29/41716 , H01L29/41741 , H01L29/41766 , H01L29/66734 , H01L29/7395 , H01L29/7397 , H01L29/7398 , H01L29/7809 , H01L29/7813 , H01L2924/10158
摘要： Thinning a semiconductor substrate has been needed for reducing on-resistance in a semiconductor device such as a vertical MOS transistor, IGBT, or the like where a high current flows in the semiconductor substrate in a vertical direction. In this case, the thinning is performed to the extent that the semiconductor substrate does not warp with a heat treatment, so that there is a limitation in reduction of on-resistance. In the invention, openings such as trench holes are formed on a back surface side of a semiconductor substrate. Then, a drain electrode is formed being electrically connected with bottoms of these openings. In this case, a current path is formed short corresponding to the depths of the openings, thereby easily achieving low on-resistance.
摘要翻译：在半导体衬底中沿垂直方向流过高电流的半导体器件，例如垂直MOS晶体管，IGBT等半导体器件中，需要对半导体衬底进行稀化。在这种情况下，通过热处理使半导体基板不翘曲的程度进行变薄，因此导通电阻的降低存在限制。在本发明中，在半导体基板的背面侧形成有诸如沟槽的开口。然后，形成与这些开口的底部电连接的漏电极。在这种情况下，电流路径形成为与开口的深度相对应，从而容易实现低导通电阻。

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