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1. 发明申请

US20060054970A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060054970A1
公开(公告)日：2006-03-16
申请号：US11220406
申请日：2005-09-07
申请人： Masamichi Yanagida , Hirotoshi Kubo , Junichiro Tojo , Hiraoki Saito , Masahito Onda
发明人： Masamichi Yanagida , Hirotoshi Kubo , Junichiro Tojo , Hiraoki Saito , Masahito Onda
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/66734
摘要： In an embodiment of the present invention, after trenches, a gate oxide film and gate electrodes are formed, a channel layer is formed by plural high-acceleration ion implantations where acceleration voltages are different with one another. The channel layer is an impurity implanted layer on which diffusion by a heat treatment is not performed. The channel layer is allowed to have its impurity concentration substantially uniform in a depth-wise direction of the trenches, by implanting ions of the impurity at plural different times by use of a high-acceleration ion implantation system. Since a second region having almost no influence on a characteristic of the channel layer can be reduced, the channel layer having a minimum necessary depth can be obtained. The trenches are thus made shallow, and accordingly a capacitance can be reduced. Furthermore, an on resistance can be made lower by making an epitaxial layer thinner.
摘要翻译：在本发明的实施例中，在沟槽之后，形成栅氧化膜和栅电极，通过加速电压彼此不同的多个高加速度离子注入形成沟道层。沟道层是不进行通过热处理的扩散的杂质注入层。通过使用高加速度离子注入系统，在多个不同时间通过注入杂质的离子，允许沟道层在沟槽的深度方向上具有基本均匀的杂质浓度。由于可以减少对沟道层的特性几乎没有影响的第二区域，所以可以获得具有最小所需深度的沟道层。因此，沟槽变浅，因此可以减小电容。此外，通过使外延层更薄，可以使导通电阻更低。

2. 发明申请

US20060065926A1 Insulated gate semiconductor device and manufacturing method of the same 有权
标题翻译：绝缘栅半导体器件及其制造方法相同
公开(公告)号：US20060065926A1
公开(公告)日：2006-03-30
申请号：US11230538
申请日：2005-09-21
申请人： Hirotoshi Kubo , Junichiro Tojo , Hiroaki Saito , Masahito Onda , Satoshi Iwata , Masamichi Yanagida
发明人： Hirotoshi Kubo , Junichiro Tojo , Hiroaki Saito , Masahito Onda , Satoshi Iwata , Masamichi Yanagida
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/66734
摘要： A capacity layer is formed of non-doped polysilicon. Unlike capacity layers formed of an oxide film, generation of seams and the like can be suppressed and thereby a stable capacity layer can be formed. Moreover, polysilicon used as a capacity layer may be doped polysilicon, and an oxide film formed on the surface of the polysilicon also serves as a capacity film. Thus, provision of an insulated gate device featuring low capacity is made possible.
摘要翻译：电容层由非掺杂多晶硅形成。与由氧化膜形成的容量层不同，可以抑制接缝等的产生，从而可以形成稳定的电容层。此外，用作电容层的多晶硅可以是掺杂多晶硅，并且形成在多晶硅表面上的氧化膜也用作容量膜。因此，提供具有低容量的绝缘栅极器件成为可能。

3. 发明授权

US07413954B2 Insulated gate semiconductor device and manufacturing method of the same 有权
标题翻译：绝缘栅半导体器件及其制造方法相同
公开(公告)号：US07413954B2
公开(公告)日：2008-08-19
申请号：US11230538
申请日：2005-09-21
申请人： Hirotoshi Kubo , Junichiro Tojo , Hiroaki Saito , Masahito Onda , Satoshi Iwata , Masamichi Yanagida
发明人： Hirotoshi Kubo , Junichiro Tojo , Hiroaki Saito , Masahito Onda , Satoshi Iwata , Masamichi Yanagida
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/66734
摘要： A capacity layer is formed of non-doped polysilicon. Unlike capacity layers formed of an oxide film, generation of seams and the like can be suppressed and thereby a stable capacity layer can be formed. Moreover, polysilicon used as a capacity layer may be doped polysilicon, and an oxide film formed on the surface of the polysilicon also serves as a capacity film. Thus, provision of an insulated gate device featuring low capacity is made possible.
摘要翻译：电容层由非掺杂多晶硅形成。与由氧化膜形成的容量层不同，可以抑制接缝等的产生，从而可以形成稳定的电容层。此外，用作电容层的多晶硅可以是掺杂多晶硅，并且形成在多晶硅表面上的氧化膜也用作容量膜。因此，提供具有低容量的绝缘栅极器件成为可能。

4. 发明申请

US20070166905A1 Method of manufacturing semiconductor device with trench 审中-公开
标题翻译：制造具有沟槽的半导体器件的方法
公开(公告)号：US20070166905A1
公开(公告)日：2007-07-19
申请号：US11709147
申请日：2007-02-22
申请人： Masamichi Yanagida , Hirotoshi Kubo , Junichiro Tojo , Hiroaki Saito , Masahito Onda
发明人： Masamichi Yanagida , Hirotoshi Kubo , Junichiro Tojo , Hiroaki Saito , Masahito Onda
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/66734
摘要： In an embodiment of the present invention, after trenches, a gate oxide film and gate electrodes are formed, a channel layer is formed by plural high-acceleration ion implantations where acceleration voltages are different with one another. The channel layer is an impurity implanted layer on which diffusion by a heat treatment is not performed. The channel layer is allowed to have its impurity concentration substantially uniform in a depth-wise direction of the trenches, by implanting ions of the impurity at plural different times by use of a high-acceleration ion implantation system. Since a second region having almost no influence on a characteristic of the channel layer can be reduced, the channel layer having a minimum necessary depth can be obtained. The trenches are thus made shallow, and accordingly a capacitance can be reduced. Furthermore, an on resistance can be made lower by making an epitaxial layer thinner.
摘要翻译：在本发明的实施例中，在沟槽之后，形成栅氧化膜和栅电极，通过加速电压彼此不同的多个高加速度离子注入形成沟道层。沟道层是不进行通过热处理的扩散的杂质注入层。通过使用高加速度离子注入系统，在多个不同时间通过注入杂质的离子，允许沟道层在沟槽的深度方向上具有基本均匀的杂质浓度。由于可以减少对沟道层的特性几乎没有影响的第二区域，所以可以获得具有最小所需深度的沟道层。因此，沟槽变浅，因此可以减小电容。此外，通过使外延层更薄，可以使导通电阻更低。

5. 发明申请

US20050266642A1 Semiconductor device and a method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050266642A1
公开(公告)日：2005-12-01
申请号：US11194446
申请日：2005-08-02
申请人： Hirotoshi Kubo , Masanao Kitagawa , Masahito Onda , Hiroaki Saito , Eiichiroh Kuwako
发明人： Hirotoshi Kubo , Masanao Kitagawa , Masahito Onda , Hiroaki Saito , Eiichiroh Kuwako
IPC分类号： H01L21/336 , H01L29/10 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7802 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A power MOSFET comprises: a semiconductor substrate 21 of a first conduction type; a drain layer 22 of the first conduction type and formed on a surface layer of the substrate; a gate insulating film 25 formed in a partial region on the drain layer 22; a gate electrode 26 formed on the gate insulating film 25; an insulating film 27 formed on the gate electrode; a side wall insulator 28 formed on side walls of the gate insulating film 25, the gate electrode 26, and the insulating film 27; a recess formed on the drain layer 22 and in a region other than a region where the gate electrode 25 and the side wall insulator 28 are formed; a channel layer 23 of a second conduction type opposite to the first conduction type and formed in a range from the region where the recess is formed to a vicinity of the region where the gate electrode 26 is formed; a source region layer 24 of the one conduction type and formed on the channel layer 23 outside the recess; and a wiring layer 29 formed to cover the channel layer 23 which is exposed through the recess, the side wall insulator 28, and the insulating film.
摘要翻译：功率MOSFET包括：第一导电类型的半导体衬底21; 第一导电类型的漏极层22，并形成在衬底的表面层上; 形成在漏极层22上的部分区域中的栅极绝缘膜25; 形成在栅极绝缘膜25上的栅电极26; 形成在栅电极上的绝缘膜27; 形成在栅极绝缘膜25，栅电极26和绝缘膜27的侧壁上的侧壁绝缘体28; 在漏极层22上形成的凹部和形成有栅电极25和侧壁绝缘体28的区域以外的区域; 与第一导电型相反的第二导电类型的沟道层23形成在从形成凹部的区域到形成栅电极26的区域附近的范围内; 一个导电类型的源极区24，并形成在凹槽外部的沟道层23上; 以及形成为覆盖通过凹部暴露的沟道层23，侧壁绝缘体28和绝缘膜的布线层29。

6. 发明申请

US20050167748A1 Insulated gate-type semiconductor device and manufacturing method of the same 有权
标题翻译：绝缘栅型半导体器件及其制造方法
公开(公告)号：US20050167748A1
公开(公告)日：2005-08-04
申请号：US11023961
申请日：2004-12-29
申请人： Masahito Onda , Hirotoshi Kubo , Shouji Miyahara , Hiroyasu Ishida , Hiroaki Saito
发明人： Masahito Onda , Hirotoshi Kubo , Shouji Miyahara , Hiroyasu Ishida , Hiroaki Saito
IPC分类号： H01L29/417 , H01L21/265 , H01L21/336 , H01L29/08 , H01L29/41 , H01L29/423 , H01L29/49 , H01L29/72 , H01L29/739 , H01L29/76 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0869 , H01L29/4236 , H01L29/66727 , H01L29/66734
摘要： An interlayer dielectric film is completely buried in a trench, and failures caused by step coverage is prevented because a source electrode can be formed substantially uniformly on an upper portion of a gate electrode. Also, in the processes of forming a source region, a body region and an interlayer dielectric film, only one mask is necessary so that the device size is reduced to account for placement error of only one mask alignment.
摘要翻译：层间电介质膜被完全埋入沟槽中，由于可以在栅电极的上部基本上均匀地形成源电极，所以防止由台阶覆盖引起的故障。此外，在形成源极区域，体区域和层间电介质膜的过程中，仅需要一个掩模，使得器件尺寸减小以仅考虑一个掩模对准的放置误差。

7. 发明授权

US07230300B2 Semiconductor device with peripheral trench 有权
标题翻译：具有外围沟槽的半导体器件
公开(公告)号：US07230300B2
公开(公告)日：2007-06-12
申请号：US10929727
申请日：2004-08-31
申请人： Masahito Onda , Hirotoshi Kubo , Shouji Miyahara , Hiroyasu Ishida
发明人： Masahito Onda , Hirotoshi Kubo , Shouji Miyahara , Hiroyasu Ishida
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7811 , H01L29/407 , H01L29/7813 , Y10S257/908
摘要： Conventional power MOSFETs enables prevention of an inversion in a surrounding region surrounding the outer periphery of an element region by a wide annular layer and a wide sealed metal. Since, resultantly, the area of the surrounding region is large, increase in the element region has been restrained. A semiconductor device is hereby provided which has an inversion prevention region containing an MIS (MOS) structure. The width of polysilicon for the inversion prevention region is large enough to prevent an inversion since the area of an oxide film can be increased by the depth of the trench. By this, leakage current can be reduced even though the area of the region surrounding the outer periphery of the element region is not enlarged. In addition, since the element region is enlarged, on-state resistance of the MOSFET can be reduced.
摘要翻译：常规的功率MOSFET能够防止围绕元件区域的外围的周围区域由宽的环形层和宽的密封金属引起的反转。因此，由于周边地区的面积大，元素区域的增加受到限制。因此提供了具有包含MIS（MOS）结构的反转防止区域的半导体器件。用于防反转区域的多晶硅的宽度足够大以防止由于沟槽的深度增加氧化膜的面积而导致的反转。由此，即使围绕元件区域的外周的区域的面积没有扩大，也可以减小泄漏电流。此外，由于元件区域被扩大，MOSFET的导通电阻可以降低。

8. 发明授权

US06939776B2 Semiconductor device and a method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06939776B2
公开(公告)日：2005-09-06
申请号：US09988272
申请日：2001-11-19
申请人： Hirotoshi Kubo , Masanao Kitagawa , Masahito Onda , Hiroaki Saito , Eiichiroh Kuwako
发明人： Hirotoshi Kubo , Masanao Kitagawa , Masahito Onda , Hiroaki Saito , Eiichiroh Kuwako
IPC分类号： H01L21/336 , H01L29/10 , H01L29/423 , H01L29/78 , H01L21/76
CPC分类号： H01L29/7802 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A power MOSFET comprises: a semiconductor substrate 21 of a first conduction type; a drain layer 22 of the first conduction type and formed on a surface layer of the substrate; a gate insulating film 25 formed in a partial region on the drain layer 22; a gate electrode 26 formed on the gate insulating film 25; an insulating film 27 formed on the gate electrode; a side wall insulator 28 formed on side walls of the gate insulating film 25, the gate electrode 26, and the insulating film 27; a recess formed on the drain layer 22 and in a region other than a region where the gate electrode 25 and the side wall insulator 28 are formed; a channel layer 23 of a second conduction type opposite to the first conduction type and formed in a range from the region where the recess is formed to a vicinity of the region where the gate electrode 26 is formed; a source region layer 24 of the one conduction type and formed on the channel layer 23 outside the recess; and a wiring layer 29 formed to cover the channel layer 23 which is exposed through the recess, the side wall insulator 28, and the insulating film.
摘要翻译：功率MOSFET包括：第一导电类型的半导体衬底21; 第一导电类型的漏极层22，并形成在衬底的表面层上; 形成在漏极层22的局部区域中的栅极绝缘膜25; 形成在栅极绝缘膜25上的栅电极26; 形成在栅电极上的绝缘膜27; 形成在栅极绝缘膜25，栅电极26和绝缘膜27的侧壁上的侧壁绝缘体28; 在漏极层22上形成的凹部和形成有栅电极25和侧壁绝缘体28的区域以外的区域; 与第一导电型相反的第二导电类型的沟道层23形成在从形成凹部的区域到形成栅电极26的区域附近的范围内; 一个导电类型的源极区24，并形成在凹槽外部的沟道层23上; 以及形成为覆盖通过凹部暴露的沟道层23，侧壁绝缘体28和绝缘膜的布线层29。

9. 发明授权

US5972741A Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5972741A
公开(公告)日：1999-10-26
申请号：US958992
申请日：1997-10-28
申请人： Hirotoshi Kubo , Eiichiroh Kuwako , Masanao Kitagawa , Masahito Onda , Hiroaki Saitou , Keita Odajima
发明人： Hirotoshi Kubo , Eiichiroh Kuwako , Masanao Kitagawa , Masahito Onda , Hiroaki Saitou , Keita Odajima
IPC分类号： H01L21/336 , H01L29/78 , H01L21/352
CPC分类号： H01L29/7813
摘要： A first conductivity layer and a first insulating film are successively formed on a channel layer, and a photoresist film is formed on the first insulating film. The photoresist film is selectively exposed to light using a photomask and patterned. Using the patterned photoresist film as a mask, the first insulating film and the first conductivity layer are etched to form source electrodes from the first conductivity layer. Using the first insulating film and the source electrodes as a mask, an impurity of one conductivity type is diffused into exposed portions of the channel layer to form source regions. A second insulating film is formed in covering relation to side walls and upper surfaces of the source electrodes. Using the second insulating film as a mask, the channel layer and the common drain layer are etched to form trenches in the source regions, the channel layer, and the common drain layer. A third insulating film is formed on surfaces of the trenches, and a second conductive layer is formed as a gate electrode on the entire surface so as to fill up the trenches and cover the second insulating film.
摘要翻译：在沟道层上依次形成第一导电层和第一绝缘膜，在第一绝缘膜上形成光致抗蚀剂膜。使用光掩模将光致抗蚀剂膜选择性地暴露于光并图案化。使用图案化的光致抗蚀剂膜作为掩模，第一绝缘膜和第一导电层被蚀刻以从第一导电层形成源电极。使用第一绝缘膜和源电极作为掩模，一种导电类型的杂质扩散到沟道层的暴露部分中以形成源极区。形成与源极电极的侧壁和上表面相关的第二绝缘膜。使用第二绝缘膜作为掩模，蚀刻沟道层和公共漏极层，以在源极区，沟道层和公共漏极层中形成沟槽。第三绝缘膜形成在沟槽的表面上，并且在整个表面上形成第二导电层作为栅电极，以填充沟槽并覆盖第二绝缘膜。

10. 发明授权

US07629644B2 Insulated gate-type semiconductor device and manufacturing method of the same 有权
标题翻译：绝缘栅型半导体器件及其制造方法
公开(公告)号：US07629644B2
公开(公告)日：2009-12-08
申请号：US11023961
申请日：2004-12-29
申请人： Masahito Onda , Hirotoshi Kubo , Shouji Miyahara , Hiroyasu Ishida , Hiroaki Saito
发明人： Masahito Onda , Hirotoshi Kubo , Shouji Miyahara , Hiroyasu Ishida , Hiroaki Saito
IPC分类号： H01L29/76
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0869 , H01L29/4236 , H01L29/66727 , H01L29/66734
摘要： An interlayer dielectric film is completely buried in a trench, and failures caused by step coverage is prevented because a source electrode can be formed substantially uniformly on an upper portion of a gate electrode. Also, in the processes of forming a source region, a body region and an interlayer dielectric film, only one mask is necessary so that the device size is reduced to account for placement error of only one mask alignment.
摘要翻译：层间电介质膜被完全埋入沟槽中，由于可以在栅电极的上部基本上均匀地形成源电极，所以防止由台阶覆盖引起的故障。此外，在形成源极区域，体区域和层间电介质膜的过程中，仅需要一个掩模，使得器件尺寸减小以仅考虑一个掩模对准的放置误差。

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