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1. 发明授权

US07413954B2 Insulated gate semiconductor device and manufacturing method of the same 有权
标题翻译：绝缘栅半导体器件及其制造方法相同
公开(公告)号：US07413954B2
公开(公告)日：2008-08-19
申请号：US11230538
申请日：2005-09-21
申请人： Hirotoshi Kubo , Junichiro Tojo , Hiroaki Saito , Masahito Onda , Satoshi Iwata , Masamichi Yanagida
发明人： Hirotoshi Kubo , Junichiro Tojo , Hiroaki Saito , Masahito Onda , Satoshi Iwata , Masamichi Yanagida
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/66734
摘要： A capacity layer is formed of non-doped polysilicon. Unlike capacity layers formed of an oxide film, generation of seams and the like can be suppressed and thereby a stable capacity layer can be formed. Moreover, polysilicon used as a capacity layer may be doped polysilicon, and an oxide film formed on the surface of the polysilicon also serves as a capacity film. Thus, provision of an insulated gate device featuring low capacity is made possible.
摘要翻译：电容层由非掺杂多晶硅形成。与由氧化膜形成的容量层不同，可以抑制接缝等的产生，从而可以形成稳定的电容层。此外，用作电容层的多晶硅可以是掺杂多晶硅，并且形成在多晶硅表面上的氧化膜也用作容量膜。因此，提供具有低容量的绝缘栅极器件成为可能。

2. 发明申请

US20060065926A1 Insulated gate semiconductor device and manufacturing method of the same 有权
标题翻译：绝缘栅半导体器件及其制造方法相同
公开(公告)号：US20060065926A1
公开(公告)日：2006-03-30
申请号：US11230538
申请日：2005-09-21
申请人： Hirotoshi Kubo , Junichiro Tojo , Hiroaki Saito , Masahito Onda , Satoshi Iwata , Masamichi Yanagida
发明人： Hirotoshi Kubo , Junichiro Tojo , Hiroaki Saito , Masahito Onda , Satoshi Iwata , Masamichi Yanagida
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/66734
摘要： A capacity layer is formed of non-doped polysilicon. Unlike capacity layers formed of an oxide film, generation of seams and the like can be suppressed and thereby a stable capacity layer can be formed. Moreover, polysilicon used as a capacity layer may be doped polysilicon, and an oxide film formed on the surface of the polysilicon also serves as a capacity film. Thus, provision of an insulated gate device featuring low capacity is made possible.
摘要翻译：电容层由非掺杂多晶硅形成。与由氧化膜形成的容量层不同，可以抑制接缝等的产生，从而可以形成稳定的电容层。此外，用作电容层的多晶硅可以是掺杂多晶硅，并且形成在多晶硅表面上的氧化膜也用作容量膜。因此，提供具有低容量的绝缘栅极器件成为可能。

3. 发明申请

US20070166905A1 Method of manufacturing semiconductor device with trench 审中-公开
标题翻译：制造具有沟槽的半导体器件的方法
公开(公告)号：US20070166905A1
公开(公告)日：2007-07-19
申请号：US11709147
申请日：2007-02-22
申请人： Masamichi Yanagida , Hirotoshi Kubo , Junichiro Tojo , Hiroaki Saito , Masahito Onda
发明人： Masamichi Yanagida , Hirotoshi Kubo , Junichiro Tojo , Hiroaki Saito , Masahito Onda
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/66734
摘要： In an embodiment of the present invention, after trenches, a gate oxide film and gate electrodes are formed, a channel layer is formed by plural high-acceleration ion implantations where acceleration voltages are different with one another. The channel layer is an impurity implanted layer on which diffusion by a heat treatment is not performed. The channel layer is allowed to have its impurity concentration substantially uniform in a depth-wise direction of the trenches, by implanting ions of the impurity at plural different times by use of a high-acceleration ion implantation system. Since a second region having almost no influence on a characteristic of the channel layer can be reduced, the channel layer having a minimum necessary depth can be obtained. The trenches are thus made shallow, and accordingly a capacitance can be reduced. Furthermore, an on resistance can be made lower by making an epitaxial layer thinner.
摘要翻译：在本发明的实施例中，在沟槽之后，形成栅氧化膜和栅电极，通过加速电压彼此不同的多个高加速度离子注入形成沟道层。沟道层是不进行通过热处理的扩散的杂质注入层。通过使用高加速度离子注入系统，在多个不同时间通过注入杂质的离子，允许沟道层在沟槽的深度方向上具有基本均匀的杂质浓度。由于可以减少对沟道层的特性几乎没有影响的第二区域，所以可以获得具有最小所需深度的沟道层。因此，沟槽变浅，因此可以减小电容。此外，通过使外延层更薄，可以使导通电阻更低。

4. 发明申请

US20060054970A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060054970A1
公开(公告)日：2006-03-16
申请号：US11220406
申请日：2005-09-07
申请人： Masamichi Yanagida , Hirotoshi Kubo , Junichiro Tojo , Hiraoki Saito , Masahito Onda
发明人： Masamichi Yanagida , Hirotoshi Kubo , Junichiro Tojo , Hiraoki Saito , Masahito Onda
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/66734
摘要： In an embodiment of the present invention, after trenches, a gate oxide film and gate electrodes are formed, a channel layer is formed by plural high-acceleration ion implantations where acceleration voltages are different with one another. The channel layer is an impurity implanted layer on which diffusion by a heat treatment is not performed. The channel layer is allowed to have its impurity concentration substantially uniform in a depth-wise direction of the trenches, by implanting ions of the impurity at plural different times by use of a high-acceleration ion implantation system. Since a second region having almost no influence on a characteristic of the channel layer can be reduced, the channel layer having a minimum necessary depth can be obtained. The trenches are thus made shallow, and accordingly a capacitance can be reduced. Furthermore, an on resistance can be made lower by making an epitaxial layer thinner.
摘要翻译：在本发明的实施例中，在沟槽之后，形成栅氧化膜和栅电极，通过加速电压彼此不同的多个高加速度离子注入形成沟道层。沟道层是不进行通过热处理的扩散的杂质注入层。通过使用高加速度离子注入系统，在多个不同时间通过注入杂质的离子，允许沟道层在沟槽的深度方向上具有基本均匀的杂质浓度。由于可以减少对沟道层的特性几乎没有影响的第二区域，所以可以获得具有最小所需深度的沟道层。因此，沟槽变浅，因此可以减小电容。此外，通过使外延层更薄，可以使导通电阻更低。

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