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1. 发明申请

US20120098073A1 Semiconductor Device 有权
标题翻译：半导体器件
公开(公告)号：US20120098073A1
公开(公告)日：2012-04-26
申请号：US12909002
申请日：2010-10-21
申请人： Dong-Hee Yu , Bong-Seok Suh , Yoon-Hae Kim , O Sung Kwon , Oh-Jung Kwon
发明人： Dong-Hee Yu , Bong-Seok Suh , Yoon-Hae Kim , O Sung Kwon , Oh-Jung Kwon
IPC分类号： H01L29/78
CPC分类号： H01L23/535 , H01L21/76802 , H01L21/76813 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided. The semiconductor device includes: a substrate; device isolation regions formed in the substrate; an impurity region formed in a region of the substrate between every two adjacent ones of the device isolation regions; a gate electrode formed on the substrate; first and second interlayer insulating films sequentially formed on the substrate; a metal interlayer insulating film formed on the second interlayer insulating film and comprising metal wiring layers; a first contact plug electrically connecting each of the metal wiring layers and the impurity region; and a second contact plug electrically connecting each of the metal wiring layers and the gate electrode, wherein the first contact plug is formed in the first and second interlayer insulating films, and the second contact plug is formed in the second interlayer insulating film.
摘要翻译：提供半导体器件。半导体器件包括：衬底; 在衬底中形成的器件隔离区; 在每隔两个相邻的器件隔离区域之间形成在衬底的区域中的杂质区; 形成在所述基板上的栅电极; 顺序形成在基板上的第一和第二层间绝缘膜; 形成在所述第二层间绝缘膜上并且包括金属布线层的金属层间绝缘膜; 电连接每个金属布线层和杂质区的第一接触插塞; 以及第二接触插塞，其电连接每个所述金属布线层和所述栅电极，其中所述第一接触插塞形成在所述第一和第二层间绝缘膜中，并且所述第二接触插塞形成在所述第二层间绝缘膜中。

2. 发明授权

US08633520B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08633520B2
公开(公告)日：2014-01-21
申请号：US12909002
申请日：2010-10-21
申请人： Dong-Hee Yu , Bong-Seok Suh , Yoon-Hae Kim , O Sung Kwon , Oh-Jung Kwon
发明人： Dong-Hee Yu , Bong-Seok Suh , Yoon-Hae Kim , O Sung Kwon , Oh-Jung Kwon
IPC分类号： H01L23/52
CPC分类号： H01L23/535 , H01L21/76802 , H01L21/76813 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided. The semiconductor device includes: a substrate; device isolation regions formed in the substrate; an impurity region formed in a region of the substrate between every two adjacent ones of the device isolation regions; a gate electrode formed on the substrate; first and second interlayer insulating films sequentially formed on the substrate; a metal interlayer insulating film formed on the second interlayer insulating film and comprising metal wiring layers; a first contact plug electrically connecting each of the metal wiring layers and the impurity region; and a second contact plug electrically connecting each of the metal wiring layers and the gate electrode, wherein the first contact plug is formed in the first and second interlayer insulating films, and the second contact plug is formed in the second interlayer insulating film.
摘要翻译：提供半导体器件。半导体器件包括：衬底; 在衬底中形成的器件隔离区; 在每隔两个相邻的器件隔离区域之间形成在衬底的区域中的杂质区; 形成在所述基板上的栅电极; 顺序形成在基板上的第一和第二层间绝缘膜; 形成在所述第二层间绝缘膜上并且包括金属布线层的金属层间绝缘膜; 电连接每个金属布线层和杂质区的第一接触插塞; 以及第二接触插塞，其电连接每个所述金属布线层和所述栅电极，其中所述第一接触插塞形成在所述第一和第二层间绝缘膜中，并且所述第二接触插塞形成在所述第二层间绝缘膜中。

3. 发明申请

US20090239344A1 Methods of Forming Field Effect Transistors Having Silicided Source/Drain Contacts with Low Contact Resistance 有权
标题翻译：形成具有低接触电阻的硅化源/漏极触点的场效应晶体管的方法
公开(公告)号：US20090239344A1
公开(公告)日：2009-09-24
申请号：US12402816
申请日：2009-03-12
申请人： Yong Kuk Jeong , Bong-Seok Suh , Dong-Hee Yu , Oh-Jung Kwon , Seong-Dong Kim , O Sung Kwon
发明人： Yong Kuk Jeong , Bong-Seok Suh , Dong-Hee Yu , Oh-Jung Kwon , Seong-Dong Kim , O Sung Kwon
IPC分类号： H01L21/335 , H01L21/28
CPC分类号： H01L29/7843 , H01L21/268 , H01L21/3105 , H01L29/6659 , H01L29/7833
摘要： Methods of forming integrated circuit devices according to embodiments of the present invention include forming a PMOS transistor having P-type source and drain regions, in a semiconductor substrate, and then forming a diffusion barrier layer on the source and drain regions. A silicon nitride layer is deposited on at least portions of the diffusion barrier layer that extend opposite the source and drain regions. Hydrogen is removed from the deposited silicon nitride layer by exposing the silicon nitride layer to ultraviolet (UV) radiation. This removal of hydrogen may operate to increase a tensile stress in a channel region of the field effect transistor. This UV radiation step may be followed by patterning the first and second silicon nitride layers to expose the source and drain regions and then forming silicide contact layers directly on the exposed source and drain regions.
摘要翻译：根据本发明的实施例的形成集成电路器件的方法包括在半导体衬底中形成具有P型源极和漏极区域的PMOS晶体管，然后在源极和漏极区域上形成扩散阻挡层。在扩散阻挡层的与源区和漏区相对延伸的至少一部分上沉积氮化硅层。通过将氮化硅层暴露于紫外线（UV）辐射，从沉积的氮化硅层去除氢。这种氢的去除可以用于增加场效应晶体管的沟道区域中的拉伸应力。该UV辐射步骤之后可以对第一和第二氮化硅层进行构图以暴露出源区和漏区，然后直接在暴露的源极和漏极区上形成硅化物接触层。

4. 发明授权

US07863201B2 Methods of forming field effect transistors having silicided source/drain contacts with low contact resistance 有权
标题翻译：形成具有低接触电阻的硅化源极/漏极触点的场效应晶体管的方法
公开(公告)号：US07863201B2
公开(公告)日：2011-01-04
申请号：US12402816
申请日：2009-03-12
申请人： Yong-Kuk Jeong , Bong-Seok Suh , Dong-Hee Yu , Oh-Jung Kwon , Seong-Dong Kim , O Sung Kwon
发明人： Yong-Kuk Jeong , Bong-Seok Suh , Dong-Hee Yu , Oh-Jung Kwon , Seong-Dong Kim , O Sung Kwon
IPC分类号： H01L21/31 , H01L21/469 , H01L21/00
CPC分类号： H01L29/7843 , H01L21/268 , H01L21/3105 , H01L29/6659 , H01L29/7833
摘要： Methods of forming integrated circuit devices according to embodiments of the present invention include forming a PMOS transistor having P-type source and drain regions, in a semiconductor substrate, and then forming a diffusion barrier layer on the source and drain regions. A silicon nitride layer is deposited on at least portions of the diffusion barrier layer that extend opposite the source and drain regions. Hydrogen is removed from the deposited silicon nitride layer by exposing the silicon nitride layer to ultraviolet (UV) radiation. This removal of hydrogen may operate to increase a tensile stress in a channel region of the field effect transistor. This UV radiation step may be followed by patterning the first and second silicon nitride layers to expose the source and drain regions and then forming silicide contact layers directly on the exposed source and drain regions.
摘要翻译：根据本发明的实施例的形成集成电路器件的方法包括在半导体衬底中形成具有P型源极和漏极区域的PMOS晶体管，然后在源极和漏极区域上形成扩散阻挡层。在扩散阻挡层的与源区和漏区相对延伸的至少一部分上沉积氮化硅层。通过将氮化硅层暴露于紫外线（UV）辐射，从沉积的氮化硅层去除氢。这种氢的去除可以用于增加场效应晶体管的沟道区域中的拉伸应力。该UV辐射步骤之后可以对第一和第二氮化硅层进行构图以暴露出源区和漏区，然后直接在暴露的源极和漏极区上形成硅化物接触层。

5. 发明申请

US20090057755A1 SPACER UNDERCUT FILLER, METHOD OF MANUFACTURE THEREOF AND ARTICLES COMPRISING THE SAME 审中-公开
标题翻译：间隔底部填充器，其制造方法和包含其的制品
公开(公告)号：US20090057755A1
公开(公告)日：2009-03-05
申请号：US11845448
申请日：2007-08-27
申请人： Thomas W. Dyer , Oh-Jung Kwon , Nivo Rovedo , O Sung Kwon , Bong-Seok Suh
发明人： Thomas W. Dyer , Oh-Jung Kwon , Nivo Rovedo , O Sung Kwon , Bong-Seok Suh
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L29/66545 , H01L21/28052 , H01L29/4933 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： Disclosed herein is a semiconducting device comprising a gate stack formed on a surface of a semiconductor substrate; a vertical nitride spacer element formed on each vertical sidewall of the gate stack; a portion of the vertical nitride spacer overlying the semiconductor substrate; a silicide contact formed on the semiconductor substrate adjacent the gate stack, the silicide contact being in operative communication with drain and source regions formed in the semiconductor substrate; and an oxide spacer disposed between the vertical nitride spacer element and the silicide contact; the oxide spacer operating to minimize an undercut adjacent the vertical nitride spacer during an etching process.
摘要翻译：本文公开了一种半导体器件，其包括形成在半导体衬底的表面上的栅极叠层; 形成在栅堆叠的每个垂直侧壁上的垂直氮化物隔离元件; 垂直氮化物间隔物的覆盖半导体衬底的部分; 形成在所述半导体衬底上的与所述栅叠层相邻的硅化物接触，所述硅化物接触与形成在所述半导体衬底中的漏极和源极区域可操作地连通; 以及设置在所述垂直氮化物间隔元件和所述硅化物接触之间的氧化物间隔物; 该氧化物间隔件用于在蚀刻过程期间最小化邻近垂直氮化物间隔物的底切。

6. 发明申请

US20110171794A1 TRANSISTOR FORMATION USING CAPPING LAYER 有权
标题翻译：使用覆盖层的晶体管形成
公开(公告)号：US20110171794A1
公开(公告)日：2011-07-14
申请号：US12685933
申请日：2010-01-12
申请人： Bong-Seok Seo , Jong-Ho Yang , Dong Hee Yu , O Sung Kwon , Oh-Jung Kwon
发明人： Bong-Seok Seo , Jong-Ho Yang , Dong Hee Yu , O Sung Kwon , Oh-Jung Kwon
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L21/823864
摘要： A method of transistor formation using a capping layer in complimentary metal-oxide semiconductor (CMOS) structures is provided, the method including: depositing a conductive layer over an n-type field effect transistor (nFET) and over a p-type field effect transistor (pFET); depositing a capping layer directly over the conductive layer; etching the capping and conductive layers to form a capped gate conductor to gates of the nFET and pFET, respectively; ion-implanting the nFET transistor with a first dopant; and ion-implanting the pFET transistor with a second dopant, wherein ion-implanting a transistor substantially dopes its source and drain regions, but not its gate region.
摘要翻译：提供了一种使用互补金属氧化物半导体（CMOS）结构中的覆盖层的晶体管形成方法，该方法包括：在n型场效应晶体管（nFET）上沉积导电层，并在p型场效应晶体管（pFET）; 在导电层上直接沉积覆盖层; 蚀刻封装和导电层以分别形成到nFET和pFET的栅极的封盖栅极导体; 用第一掺杂剂离子注入nFET晶体管; 并且用第二掺杂剂离子注入pFET晶体管，其中离子注入晶体管基本上掺杂其源极和漏极区域，而不是其栅极区域。

7. 发明授权

US08030196B2 Transistor formation using capping layer 有权
标题翻译：使用封盖层的晶体管形成
公开(公告)号：US08030196B2
公开(公告)日：2011-10-04
申请号：US12685933
申请日：2010-01-12
申请人： Bong-Seok Seo , Jong-Ho Yang , Dong Hee Yu , O Sung Kwon , Oh-Jung Kwon
发明人： Bong-Seok Seo , Jong-Ho Yang , Dong Hee Yu , O Sung Kwon , Oh-Jung Kwon
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L21/823864
摘要： A method of transistor formation using a capping layer in complimentary metal-oxide semiconductor (CMOS) structures is provided, the method including: depositing a conductive layer over an n-type field effect transistor (nFET) and over a p-type field effect transistor (pFET); depositing a capping layer directly over the conductive layer; etching the capping and conductive layers to form a capped gate conductor to gates of the nFET and pFET, respectively; ion-implanting the nFET transistor with a first dopant; and ion-implanting the pFET transistor with a second dopant, wherein ion-implanting a transistor substantially dopes its source and drain regions, but not its gate region.
摘要翻译：提供了一种使用互补金属氧化物半导体（CMOS）结构中的覆盖层的晶体管形成方法，该方法包括：在n型场效应晶体管（nFET）上沉积导电层，并在p型场效应晶体管（pFET）; 在导电层上直接沉积覆盖层; 蚀刻封盖和导电层，以分别形成到nFET和pFET的栅极的封盖栅极导体; 用第一掺杂剂离子注入nFET晶体管; 并且用第二掺杂剂离子注入pFET晶体管，其中离子注入晶体管基本上掺杂其源极和漏极区域，而不是其栅极区域。

8. 发明申请

US20080070360A1 METHOD AND STRUCTURE FOR FORMING SILICIDE CONTACTS ON EMBEDDED SILICON GERMANIUM REGIONS OF CMOS DEVICES 审中-公开
标题翻译： CMOS器件嵌入式硅锗区域形成硅化物接触的方法与结构
公开(公告)号：US20080070360A1
公开(公告)日：2008-03-20
申请号：US11533018
申请日：2006-09-19
申请人： Oh-Jung Kwon , O Sung Kwon
发明人： Oh-Jung Kwon , O Sung Kwon
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/66636 , H01L29/7848
摘要： A method of forming silicide contacts for a complementary metal oxide semiconductor (CMOS) device includes selectively forming a protective layer over faceted surfaces of an embedded SiGe (eSiGe) region of a substrate, the eSiGe region comprising a compressive stress inducing layer in a PFET portion of the CMOS device, wherein the faceted surfaces are disposed adjacent shallow trench isolation (STI) regions used to separate NFET regions from PFET regions of the CMOS device; depositing a metal layer for silicide formation over the CMOS device; and annealing the CMOS device to form silicide, wherein the protective layer formed over the faceted surfaces prevents the formation of silicide thereon.
摘要翻译：形成用于互补金属氧化物半导体（CMOS）器件的硅化物触点的方法包括在衬底的嵌入式SiGe（eSiGe）区域的刻面上选择性地形成保护层，eSiGe区域包括PFET部分中的压应力诱导层其中所述刻面被设置在用于将NFET区与CMOS器件的PFET区分离的浅沟槽隔离（STI）区域附近; 在CMOS器件上沉积用于硅化物形成的金属层; 并且对CMOS器件进行退火以形成硅化物，其中形成在刻面上的保护层防止其上形成硅化物。

9. 发明申请

US20110070732A1 METHOD OF SILICIDE FORMATION BY ADDING GRADED AMOUNT OF IMPURITY DURING METAL DEPOSITION 失效
标题翻译：通过在金属沉积期间增加放射量的量来制备硅化物的方法
公开(公告)号：US20110070732A1
公开(公告)日：2011-03-24
申请号：US12563459
申请日：2009-09-21
申请人： Oh-Jung Kwon , Anthony G. Domenicucci , O Sung Kwon , Jin-Woo Choi
发明人： Oh-Jung Kwon , Anthony G. Domenicucci , O Sung Kwon , Jin-Woo Choi
IPC分类号： H01L21/3205
CPC分类号： H01L21/28518 , C23C14/18 , C23C14/5806 , H01L21/2855
摘要： A method is provided for forming a metal semiconductor alloy that includes providing a deposition apparatus that includes a platinum source and a nickel source, wherein the platinum source is separate from the nickel source; positioning a substrate having a semiconductor surface in the deposition apparatus; forming a metal alloy on the semiconductor surface, wherein forming the metal alloy comprises a deposition stage in which the platinum source deposits platinum to the semiconductor surface at an initial rate at an initial period that is greater than a final rate at a final period of the deposition stage, and the nickel source deposits nickel to the semiconductor surface; and annealing the metal alloy to react the nickel and platinum with the semiconductor substrate to provide a nickel platinum semiconductor alloy.
摘要翻译：提供一种用于形成金属半导体合金的方法，其包括提供包括铂源和镍源的沉积设备，其中所述铂源与所述镍源分离; 将具有半导体表面的基板定位在沉积设备中; 在半导体表面上形成金属合金，其中形成金属合金包括沉积阶段，其中铂源以最初的速率以最初的速率将铂沉积到半导体表面上，该初始时间段大于最终时间段的最终时间沉积阶段，镍源将镍沉积到半导体表面; 并退火金属合金以使镍和铂与半导体衬底反应以提供镍铂半导体合金。

10. 发明申请

US20080119025A1 Method of making a strained semiconductor device 审中-公开
标题翻译：制造应变半导体器件的方法
公开(公告)号：US20080119025A1
公开(公告)日：2008-05-22
申请号：US11603276
申请日：2006-11-21
申请人： O Sung Kwon , Oh Jung Kwon , Jin-Ping Han , Henry Utomo
发明人： O Sung Kwon , Oh Jung Kwon , Jin-Ping Han , Henry Utomo
IPC分类号： H01L21/336 , H01L21/20
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66545 , H01L29/66636 , H01L29/7834 , H01L29/7843 , H01L29/7848
摘要： In a method of making a semiconductor device, a recess is formed in an upper surface of the semiconductor body of a first material. An embedded semiconductor region is formed in the recess. The embedded semiconductor region is formed from a second semiconductor material that is different than the first semiconductor material. An upper surface of the embedded semiconductor region is amorphized to create an amorphous region. A silicide is then formed over the amorphous region.
摘要翻译：在制造半导体器件的方法中，在第一材料的半导体本体的上表面中形成凹部。嵌入式半导体区域形成在凹部中。嵌入式半导体区域由与第一半导体材料不同的第二半导体材料形成。嵌入式半导体区域的上表面非晶化以产生非晶区域。然后在无定形区域上形成硅化物。

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