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1. 发明授权

US08384131B2 Semiconductor device and methods of forming the same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US08384131B2
公开(公告)日：2013-02-26
申请号：US12187271
申请日：2008-08-06
申请人： Kyoung-Woo Lee , Andrew Tae Kim , Hong-Jae Shin
发明人： Kyoung-Woo Lee , Andrew Tae Kim , Hong-Jae Shin
IPC分类号： H01L27/10
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device includes a fuse structure disposed on a substrate. An interlayer dielectric disposed on the fuse structure. A first contact plug, a second contact plug, and a third contact plug penetrate the interlayer dielectric and wherein each of the first contact plug, the second contact plug and the third contact plug are connected to the fuse structure. A first conductive pattern and a second conductive pattern are disposed on the interlayer dielectric. The first conductive pattern and the second conductive pattern are electrically connected to the first contact plug and second contact plug, respectively.
摘要翻译：半导体器件包括设置在衬底上的熔丝结构。设置在熔丝结构上的层间电介质。第一接触插塞，第二接触插塞和第三接触插塞穿透层间电介质，并且其中第一接触插塞，第二接触插塞和第三接触插塞中的每一个连接到熔丝结构。第一导电图案和第二导电图案设置在层间绝缘体上。第一导电图案和第二导电图案分别电连接到第一接触插塞和第二接触插塞。

2. 发明授权

US08237202B2 Semiconductor devices including dehydrogenated interlayer dielectric layers 有权
标题翻译：包括脱氢层间电介质层的半导体器件
公开(公告)号：US08237202B2
公开(公告)日：2012-08-07
申请号：US12987415
申请日：2011-01-10
申请人： Yong-kuk Jeong , Andrew-tae Kim , Dong-suk Shin
发明人： Yong-kuk Jeong , Andrew-tae Kim , Dong-suk Shin
IPC分类号： H01L27/118
CPC分类号： H01L21/823807 , H01L21/76801 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/823864 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： Methods of manufacturing a semiconductor device include forming an NMOS transistor on a semiconductor substrate, forming a first interlayer dielectric layer on the NMOS transistor, and dehydrogenating the first interlayer dielectric layer. Dehydrogenating the first interlayer dielectric layer may change a stress of the first interlayer dielectric layer. In particular, the first interlayer dielectric layer may have a tensile stress of 200 MPa or more after dehydrogenization. Semiconductor devices including dehydrogenated interlayer dielectric layers are also provided.
摘要翻译：制造半导体器件的方法包括在半导体衬底上形成NMOS晶体管，在NMOS晶体管上形成第一层间电介质层，并使第一层间电介质层脱氢。使第一层间电介质层脱氢可以改变第一层间电介质层的应力。特别地，第一层间电介质层可以在脱氢后具有200MPa以上的拉伸应力。还提供了包括脱氢层间电介质层的半导体器件。

3. 发明授权

US08198702B2 Electrical fuse device 失效
标题翻译：电熔丝装置
公开(公告)号：US08198702B2
公开(公告)日：2012-06-12
申请号：US13193637
申请日：2011-07-29
申请人： Dong-suk Shin , Andrew-Tae Kim , Hong-jae Shin
发明人： Dong-suk Shin , Andrew-Tae Kim , Hong-jae Shin
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L23/5258 , H01L27/112 , H01L2924/0002 , H01L2924/00
摘要： The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current densities in a fuse link. In one respect, there is provided an electrical fuse device that includes: an anode; a fuse link coupled to the anode on a first side of the fuse link; a cathode coupled to the fuse link on a second side of the fuse link; a first cathode contact coupled to the cathode; and a first anode contact coupled to the anode, at least one of the first cathode contact and the first anode contact being disposed across a virtual extending surface of the fuse link.
摘要翻译：本发明一般涉及半导体器件的熔丝器件，更具体地，涉及一种半导体器件的电熔丝器件。本发明的实施例提供一种能够减少由熔丝链中的不均匀电流密度引起的编程误差的熔丝装置。在一方面，提供一种电熔丝装置，其包括：阳极; 熔丝链路，其在所述熔丝连接件的第一侧上耦合到所述阳极; 连接到所述熔丝链的第二侧上的所述熔断体的阴极; 耦合到阴极的第一阴极接触; 以及耦合到所述阳极的第一阳极触点，所述第一阴极触点和所述第一阳极触点中的至少一个跨越所述熔断体的虚拟延伸表面设置。

4. 发明申请

US20110163386A1 Semiconductor Devices Including Dehydrogenated Interlayer Dielectric Layers 有权
标题翻译：包括脱氢层间电介质层的半导体器件
公开(公告)号：US20110163386A1
公开(公告)日：2011-07-07
申请号：US12987415
申请日：2011-01-10
申请人： Yong-kuk Jeong , Andrew-tae Kim , Dong-suk Shin
发明人： Yong-kuk Jeong , Andrew-tae Kim , Dong-suk Shin
IPC分类号： H01L27/092 , H01L29/51
CPC分类号： H01L21/823807 , H01L21/76801 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/823864 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： Methods of manufacturing a semiconductor device include forming an NMOS transistor on a semiconductor substrate, forming a first interlayer dielectric layer on the NMOS transistor, and dehydrogenating the first interlayer dielectric layer. Dehydrogenating the first interlayer dielectric layer may change a stress of the first interlayer dielectric layer. In particular, the first interlayer dielectric layer may have a tensile stress of 200 MPa or more after dehydrogenization. Semiconductor devices including dehydrogenated interlayer dielectric layers are also provided.
摘要翻译：制造半导体器件的方法包括在半导体衬底上形成NMOS晶体管，在NMOS晶体管上形成第一层间电介质层，并使第一层间电介质层脱氢。使第一层间电介质层脱氢可以改变第一层间电介质层的应力。特别地，第一层间电介质层可以在脱氢后具有200MPa以上的拉伸应力。还提供了包括脱氢层间电介质层的半导体器件。

5. 发明授权

US07888749B2 Semiconductor devices having selectively tensile stressed gate electrodes and methods of fabricating the same 有权
标题翻译：具有选择性拉伸应力栅电极的半导体器件及其制造方法
公开(公告)号：US07888749B2
公开(公告)日：2011-02-15
申请号：US11752370
申请日：2007-05-23
申请人： Dong-suk Shin , Andrew Tae Kim , Yong-kuk Jeong
发明人： Dong-suk Shin , Andrew Tae Kim , Yong-kuk Jeong
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L21/823828 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L29/6656 , H01L29/66636 , H01L29/7843 , H01L29/7846
摘要： A semiconductor device includes an active region. A gate electrode is disposed on the active region. An isolation region adjoins the active region, and is recessed with respect to a top surface of the active region underlying the gate electrode. The isolation region may be recessed a depth substantially equal to a height of the gate electrode. In some embodiments, the gate electrode is configured to support current flow through the active region along a first direction, and a tensile stress layer covers the gate electrode and is configured to apply a tensile stress to the gate electrode along a second direction perpendicular to the first direction. The tensile stress layer may cover the recessed isolation region and portions of the active region between the isolation region and the gate electrode. In further embodiments, an interlayer insulating film is disposed on the tensile stress layer and is configured to apply a tensile stress to the gate electrode along the second direction.
摘要翻译：半导体器件包括有源区。栅电极设置在有源区上。隔离区域邻接有源区，并且相对于栅电极下方的有源区的顶表面凹陷。隔离区域可以凹入基本上等于栅电极的高度的深度。在一些实施例中，栅电极被配置为支持沿着第一方向流过有源区的电流，并且拉伸应力层覆盖栅电极，并且构造成沿垂直于第二方向的第二方向向栅电极施加拉伸应力第一个方向拉伸应力层可以覆盖凹陷的隔离区域和隔离区域和栅电极之间的有源区域的部分。在另外的实施例中，层间绝缘膜设置在拉伸应力层上，并被构造成沿着第二方向向栅电极施加拉伸应力。

6. 发明申请

US20090039480A1 SEMICONDUCTOR DEVICE AND METHODS OF FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20090039480A1
公开(公告)日：2009-02-12
申请号：US12187271
申请日：2008-08-06
申请人： KYOUNG-WOO LEE , Andrew Tae Kim , Hong-Jae Shin
发明人： KYOUNG-WOO LEE , Andrew Tae Kim , Hong-Jae Shin
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device includes a fuse structure disposed on a substrate. An interlayer dielectric disposed on the fuse structure. A first contact plug, a second contact plug, and a third contact plug penetrate the interlayer dielectric and wherein each of the first contact plug, the second contact plug and the third contact plug are connected to the fuse structure. A first conductive pattern and a second conductive pattern are disposed on the interlayer dielectric. The first conductive pattern and the second conductive pattern are electrically connected to the first contact plug and second contact plug, respectively.
摘要翻译：半导体器件包括设置在衬底上的熔丝结构。设置在熔丝结构上的层间电介质。第一接触插塞，第二接触插塞和第三接触插塞穿透层间电介质，并且其中第一接触插塞，第二接触插塞和第三接触插塞中的每一个连接到熔丝结构。第一导电图案和第二导电图案设置在层间电介质上。第一导电图案和第二导电图案分别电连接到第一接触插塞和第二接触插塞。

7. 发明申请

US20080023769A1 Semiconductor Devices Having Selectively Tensile Stressed Gate Electrodes and Methods of Fabricating the Same 有权
标题翻译：具有选择性拉伸的栅极电极的半导体器件及其制造方法
公开(公告)号：US20080023769A1
公开(公告)日：2008-01-31
申请号：US11752370
申请日：2007-05-23
申请人： Dong-suk Shin , Andrew Tae Kim , Yong-kuk Jeong
发明人： Dong-suk Shin , Andrew Tae Kim , Yong-kuk Jeong
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L21/823828 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L29/6656 , H01L29/66636 , H01L29/7843 , H01L29/7846
摘要： A semiconductor device includes an active region. A gate electrode is disposed on the active region. An isolation region adjoins the active region, and is recessed with respect to a top surface of the active region underlying the gate electrode. The isolation region may be recessed a depth substantially equal to a height of the gate electrode. In some embodiments, the gate electrode is configured to support current flow through the active region along a first direction, and a tensile stress layer covers the gate electrode and is configured to apply a tensile stress to the gate electrode along a second direction perpendicular to the first direction. The tensile stress layer may cover the recessed isolation region and portions of the active region between the isolation region and the gate electrode. In further embodiments, an interlayer insulating film is disposed on the tensile stress layer and is configured to apply a tensile stress to the gate electrode along the second direction.
摘要翻译：半导体器件包括有源区。栅电极设置在有源区上。隔离区域邻接有源区，并且相对于栅电极下方的有源区的顶表面凹陷。隔离区域可以凹入基本上等于栅电极的高度的深度。在一些实施例中，栅电极被配置为支持沿着第一方向流过有源区的电流，并且拉伸应力层覆盖栅电极，并且构造成沿垂直于第二方向的第二方向向栅电极施加拉伸应力第一个方向拉伸应力层可以覆盖凹陷的隔离区域和隔离区域和栅电极之间的有源区域的部分。在另外的实施例中，层间绝缘膜设置在拉伸应力层上，并被构造成沿着第二方向向栅电极施加拉伸应力。

8. 发明申请

US20070105297A1 Semiconductor devices and methods of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070105297A1
公开(公告)日：2007-05-10
申请号：US11593898
申请日：2006-11-07
申请人： Yong-kuk Jeong , Andrew-tae Kim , Dong-suk Shin
发明人： Yong-kuk Jeong , Andrew-tae Kim , Dong-suk Shin
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/76801 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/823864 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： Methods of manufacturing a semiconductor device include forming an NMOS transistor on a semiconductor substrate, forming a first interlayer dielectric layer on the NMOS transistor, and dehydrogenating the first interlayer dielectric layer. Dehydrogenating the first interlayer dielectric layer may change a stress of the first interlayer dielectric layer. In particular, the first interlayer dielectric layer may have a tensile stress of 200 MPa or more after dehydrogenization. Semiconductor devices including dehydrogenated interlayer dielectric layers are also provided.
摘要翻译：制造半导体器件的方法包括在半导体衬底上形成NMOS晶体管，在NMOS晶体管上形成第一层间电介质层，并使第一层间电介质层脱氢。使第一层间电介质层脱氢可以改变第一层间电介质层的应力。特别地，第一层间电介质层可以在脱氢后具有200MPa以上的拉伸应力。还提供了包括脱氢层间电介质层的半导体器件。

9. 发明申请

US20060177630A1 Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method 有权
标题翻译：形成半导体器件的金属互连的方法以及通过这种方法形成的金属互连
公开(公告)号：US20060177630A1
公开(公告)日：2006-08-10
申请号：US11336905
申请日：2006-01-23
申请人： Sun-jung Lee , Soo-geun Lee , Hong-jae Shin , Andrew-tae Kim , Seung-man Choi , Bong-seok Suh
发明人： Sun-jung Lee , Soo-geun Lee , Hong-jae Shin , Andrew-tae Kim , Seung-man Choi , Bong-seok Suh
IPC分类号： B32B3/04
CPC分类号： H01L21/76877 , H01L21/7684 , H01L21/76883 , Y10T428/24207
摘要： A metal interconnection of a semiconductor device, formed using a damascene process, has large grains and yet a smooth surface. First, a barrier layer and a metal layer are sequentially formed in an opening in an interlayer dielectric layer. A CMP process is carried out on the metal layer to form a metal interconnection remaining within the opening. Then, the metal interconnection is treated with plasma. The plasma treatment creates compressive stress in the metal interconnection, which stress produces hillocks at the surface of the metal interconnection. In addition, the plasma treatment process causes grains of the metal to grow, especially when the design rule is small, to thereby decrease the resistivity of the metal interconnection. The hillocks are then removed by a CMP process aimed at polishing the portion of the barrier layer that extends over the upper surface of the interlayer dielectric layer. Finally, a capping insulating layer is formed. The intentional forming of hillocks by the plasma treatment process at weak portions of the metal interconnection and the subsequent removal of the hillocks greatly reduces the possibility of any additional hillocks being produced at the surface of the metal interconnection, especially when the capping layer is formed.
摘要翻译：使用镶嵌工艺形成的半导体器件的金属互连具有大的晶粒并且具有光滑的表面。首先，在层间电介质层的开口中依次形成阻挡层和金属层。在金属层上进行CMP工艺以形成残留在开口内的金属互连。然后，用等离子体处理金属互连。等离子体处理在金属互连中产生压应力，该应力在金属互连表面产生小丘。此外，等离子体处理工艺使得金属晶粒生长，特别是当设计规则小时，从而降低金属互连的电阻率。然后通过CMP工艺去除小丘，目的是抛光在层间电介质层的上表面上延伸的阻挡层的部分。最后，形成封盖绝缘层。通过等离子体处理在金属互连的弱部分和随后的小丘的移除中有意形成小丘大大减少了在金属互连表面产生任何额外的小丘的可能性，特别是当形成覆盖层时。

10. 发明申请

US20110101492A1 SEMICONDUCTOR DEVICE HAVING THERMALLY FORMED AIR GAP IN WIRING LAYER AND METHOD OF FABRICATING SAME 有权
标题翻译：在接线层中形成热形成的空气隙的半导体器件及其制造方法
公开(公告)号：US20110101492A1
公开(公告)日：2011-05-05
申请号：US12987427
申请日：2011-01-10
申请人： Seok-jun WON , Andrew-tae KIM
发明人： Seok-jun WON , Andrew-tae KIM
IPC分类号： H01L23/48
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided. A unit wiring level of the semiconductor device includes; first and second wiring layers spaced apart from each other on a support layer, a large space formed adjacent to the first wiring layer and including a first air gap of predetermined width as measured from a sidewall of the first wiring layer, and a portion of a thermally degradable material layer formed on the support layer, small space formed between the first and second wiring layers, wherein the small space is smaller than the large space, and a second air gap at least partially fills the small space, and a porous insulating layer formed on the first and second air gaps.
摘要翻译：提供半导体器件。半导体器件的单位布线层包括：在支撑层上彼此间隔开的第一和第二布线层，与第一布线层相邻形成的大空间，并且包括从第一布线层的侧壁测量的预定宽度的第一气隙，形成在支撑层上的热降解材料层，形成在第一和第二布线层之间的小空间，其中小空间小于大空间，第二气隙至少部分地填充小空间，多孔绝缘层形成在第一和第二气隙上。

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