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31. 发明授权

US06867477B2 High gain bipolar transistor 有权
标题翻译：高增益双极晶体管
公开(公告)号：US06867477B2
公开(公告)日：2005-03-15
申请号：US10290975
申请日：2002-11-07
申请人： Jie Zheng , Peihua Ye , Marco Racanelli
发明人： Jie Zheng , Peihua Ye , Marco Racanelli
IPC分类号： H01L29/08 , H01L29/735 , H01L29/00 , H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/0808 , H01L29/735
摘要： According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor might be a lateral PNP bipolar transistor and the base may comprise, for example, N type single crystal silicon. The bipolar transistor further comprises an emitter having a top surface, where the emitter is situated on the top surface of the base. The emitter may comprise P+ type single crystal silicon-germanium, for example. The bipolar transistor further comprises an electron barrier layer situated directly on the top surface of the emitter. The electron barrier layer will cause an increase in the gain, or beta, of the bipolar transistor. The electron barrier layer may be a dielectric such as, for example, silicon oxide. In another embodiment, a floating N+ region, instead of the electron barrier layer, is utilized to increase the gain of the bipolar transistor.
摘要翻译：根据一个示例性实施例，双极晶体管包括具有顶表面的基座。双极晶体管可以是横向PNP双极晶体管，并且基极可以包括例如N型单晶硅。双极晶体管还包括具有顶表面的发射器，其中发射器位于基极的顶表面上。例如，发射极可以包括P +型单晶硅 - 锗。双极晶体管还包括直接位于发射极的顶表面上的电子势垒层。电子势垒层将引起双极晶体管的增益或β的增加。电子势垒层可以是电介质，例如氧化硅。在另一个实施例中，利用浮置N +区而不是电子势垒层来增加双极晶体管的增益。

32. 发明授权

US06809353B2 Method for fabricating a self-aligned bipolar transistor with planarizing layer and related structure 有权
公开(公告)号：US06809353B2
公开(公告)日：2004-10-26
申请号：US10442489
申请日：2003-05-21
申请人： Amol M Kalburge , Marco Racanelli
发明人： Amol M Kalburge , Marco Racanelli
IPC分类号： H01L310328
CPC分类号： H01L29/66287 , H01L29/66242 , H01L29/66318
摘要： According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises first and second link spacers situated on the top surface of the base. The bipolar transistor further comprises a sacrificial post situated on the top surface of the base between the first and second link spacers. The first and second link spacers may have a height, for example, approximately equal to or, in another embodiment, substantially less than a height of the sacrificial post. According to this exemplary embodiment, the bipolar transistor further comprises a non-sacrificial planarizing layer situated over the sacrificial post, first and second link spacers, and base. The non-sacrificial planarizing layer may comprise, for example, silicate glass. The sacrificial planarizing layer may have a height, for example, approximately equal to or, in another embodiment, greater than greater than a height of the first and second link spacers.

33. 发明授权

US06784467B1 Method for fabricating a self-aligned bipolar transistor and related structure 有权
标题翻译：制造自对准双极晶体管及相关结构的方法
公开(公告)号：US06784467B1
公开(公告)日：2004-08-31
申请号：US10218527
申请日：2002-08-13
申请人： Amol M Kalburge , Marco Racanelli
发明人： Amol M Kalburge , Marco Racanelli
IPC分类号： H01L310328
CPC分类号： H01L29/66287 , H01L29/0804 , H01L29/66242
摘要： According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a sacrificial post which, in one exemplary embodiment, is situated between first and second link spacers. The bipolar transistor also comprises a conformal layer situated over the sacrificial post. The conformal layer may comprise silicon oxide, for example. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer, the sacrificial post, and the base. The sacrificial planarizing layer has a first thickness in a first region between the first and second link spacers and a second thickness in a second region outside of the first and second link spacers, where the second thickness is generally greater than the first thickness. Another embodiment is a method that achieves the above-described bipolar transistor.
摘要翻译：根据一个示例性实施例，双极晶体管包括具有顶表面的基座。双极晶体管还包括在一个示例性实施例中位于第一和第二连接间隔物之间的牺牲柱。双极晶体管还包括位于牺牲柱上方的保形层。保形层可以包括例如氧化硅。根据该示例性实施例，双极晶体管还包括位于保形层，牺牲柱和基底之上的牺牲平坦化层。牺牲平坦化层在第一和第二连接间隔物之间的第一区域中具有第一厚度，并且在第一和第二连接间隔物外部的第二区域中具有第二厚度，其中第二厚度通常大于第一厚度。另一个实施例是实现上述双极晶体管的方法。

34. 发明授权

US06744322B1 High performance BiFET low noise amplifier 有权
标题翻译：高性能BiFET低噪声放大器
公开(公告)号：US06744322B1
公开(公告)日：2004-06-01
申请号：US10057098
申请日：2002-01-23
申请人： Pingxi Ma , Marco Racanelli
发明人： Pingxi Ma , Marco Racanelli
IPC分类号： H03F316
CPC分类号： H03F1/22 , H03F3/189 , H03F2200/294 , H03F2200/372
摘要： According to one exemplary embodiment, a circuit comprises a bipolar transistor having a base, an emitter, and a collector. For example, the bipolar transistor can be an NPN SiGe HBT. The base of the bipolar transistor is an input of the circuit. The emitter of the bipolar transistor is coupled to a first reference voltage. According to this exemplary embodiment, the circuit further comprises a field effect transistor having a gate, a source, and a drain. For example, the field effect transistor may be an NFET. The collector of the bipolar transistor is coupled to the source of the field effect transistor. The gate of the field effect transistor is coupled to a bias voltage. The drain of the field effect transistor is coupled to a second reference voltage. The drain of the field effect transistor is an output of the circuit.
摘要翻译：根据一个示例性实施例，电路包括具有基极，发射极和集电极的双极晶体管。例如，双极晶体管可以是NPN SiGe HBT。双极晶体管的基极是电路的输入。双极晶体管的发射极耦合到第一参考电压。根据该示例性实施例，电路还包括具有栅极，源极和漏极的场效应晶体管。例如，场效应晶体管可以是NFET。双极晶体管的集电极耦合到场效应晶体管的源极。场效应晶体管的栅极耦合到偏置电压。场效应晶体管的漏极耦合到第二参考电压。场效应晶体管的漏极是电路的输出。

35. 发明授权

US06680235B1 Method for fabricating a selective eptaxial HBT emitter 有权
标题翻译：制造选择性高能HBT发射体的方法
公开(公告)号：US06680235B1
公开(公告)日：2004-01-20
申请号：US10302308
申请日：2002-11-22
申请人： Greg D. U'Ren , Marco Racanelli , Klaus F. Schuegraf
发明人： Greg D. U'Ren , Marco Racanelli , Klaus F. Schuegraf
IPC分类号： H01L218222
CPC分类号： H01L29/66242 , H01L29/0817 , H01L29/7378
摘要： According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a top surface. The heterojunction bipolar transistor further comprises an epitaxial emitter selectively situated on the top surface of the base. For example, the epitaxial emitter may be N-type single-crystal silicon. The heterojunction bipolar transistor further comprises an etch stop layer situated on the top surface of the base, where the etch stop layer is in contact with the epitaxial emitter. The heterojunction bipolar transistor further comprises a first spacer and a second spacer situated on the etch stop layer, where the epitaxial emitter is situated between the first and second spacer. The first spacer and the second spacer, for example, may be LPCVD silicon nitride. The heterojunction bipolar transistor further comprises a dielectric layer deposited on the first and second spacers. The heterojunction bipolar transistor further comprises an antireflective coating layer deposited over the dielectric layer.
摘要翻译：根据一个示例性实施例，异质结双极晶体管包括具有顶表面的基极。异质结双极晶体管还包括选择性地位于基底的顶表面上的外延发射体。例如，外延发射极可以是N型单晶硅。异质结双极晶体管还包括位于基底顶表面上的蚀刻停止层，其中蚀刻停止层与外延发射体接触。异质结双极晶体管还包括位于蚀刻停止层上的第一间隔物和第二间隔物，其中外延发射体位于第一和第二间隔物之间。例如，第一间隔物和第二间隔物可以是LPCVD氮化硅。异质结双极晶体管还包括沉积在第一和第二间隔物上的电介质层。异质结双极晶体管还包括沉积在电介质层上的抗反射涂层。

36. 发明授权

US06627511B1 Reduced stress isolation for SOI devices and a method for fabricating 失效
标题翻译：降低SOI器件的应力隔离和制造方法
公开(公告)号：US06627511B1
公开(公告)日：2003-09-30
申请号：US08508874
申请日：1995-07-28
申请人： Marco Racanelli , Hyungcheol Shin , Heemyong Park
发明人： Marco Racanelli , Hyungcheol Shin , Heemyong Park
IPC分类号： H01L2176
CPC分类号： H01L21/76264 , H01L21/32 , H01L21/76267 , H01L21/76275 , H01L21/76281
摘要： A method for forming an isolation structure (22) on a SOI substrate (11) is provided. A three layer stack of an etchant barrier layer (16), a stress relief layer (17), and an oxide mask layer (18) is formed on the SOI substrate (11). The three layer stack is patterned and etched to expose portions of the etchant barrier layer (16). The silicon layer (13) below the exposed portions of the etchant barrier layer (16) is oxidized to form the isolation structure (22). The isolation structure (22) comprises a bird's head region (21) with a small encroachment which results in higher edge threshold voltage. The method requires minimum over-oxidation and provides for an isolation structure (22) that leaves the SOI substrate (11) planar. Minimal over-oxidation reduces the number of dislocations formed during the oxidation process and improves the source to drain leakage of the device.
摘要翻译：提供了一种在SOI衬底（11）上形成隔离结构（22）的方法。在SOI衬底（11）上形成蚀刻剂阻挡层（16），应力消除层（17）和氧化物掩模层（18）的三层堆叠。图案化和蚀刻三层堆叠以暴露蚀刻剂阻挡层（16）的部分。在蚀刻剂阻挡层（16）的暴露部分下面的硅层（13）被氧化以形成隔离结构（22）。隔离结构（22）包括具有小的侵入的鸟头区域（21），其导致较高的边缘阈值电压。该方法需要最小的过氧化并提供使SOI衬底（11）平坦离开的隔离结构（22）。最小的过氧化减少了在氧化过程中形成的位错数，并且改善了器件的源漏漏。

37. 发明授权

US06617619B1 Structure for a selective epitaxial HBT emitter 有权
标题翻译：用于选择性外延HBT发射极的结构
公开(公告)号：US06617619B1
公开(公告)日：2003-09-09
申请号：US10067034
申请日：2002-02-04
申请人： Greg D. U'Ren , Marco Racanelli , Klaus F. Schuegraf
发明人： Greg D. U'Ren , Marco Racanelli , Klaus F. Schuegraf
IPC分类号： H01L310328
CPC分类号： H01L29/66242 , H01L29/0817 , H01L29/7378
摘要： According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a top surface. The heterojunction bipolar transistor further comprises an epitaxial emitter selectively situated on the top surface of the base. For example, the epitaxial emitter may be N-type single-crystal silicon. The heterojunction bipolar transistor further comprises an etch stop layer situated on the top surface of the base, where the etch stop layer is in contact with the epitaxial emitter. The heterojunction bipolar transistor further comprises a first spacer and a second spacer situated on the etch stop layer, where the epitaxial emitter is situated between the first and second spacer. The first spacer and the second spacer, for example, may be LPCVD silicon nitride. The heterojunction bipolar transistor further comprises a dielectric layer deposited on the first and second spacers. The heterojunction bipolar transistor further comprises an antireflective coating layer deposited over the dielectric layer.
摘要翻译：根据一个示例性实施例，异质结双极晶体管包括具有顶表面的基极。异质结双极晶体管还包括选择性地位于基底的顶表面上的外延发射体。例如，外延发射极可以是N型单晶硅。异质结双极晶体管还包括位于基底顶表面上的蚀刻停止层，其中蚀刻停止层与外延发射体接触。异质结双极晶体管还包括位于蚀刻停止层上的第一间隔物和第二间隔物，其中外延发射体位于第一和第二间隔物之间。例如，第一间隔物和第二间隔物可以是LPCVD氮化硅。异质结双极晶体管还包括沉积在第一和第二间隔物上的电介质层。异质结双极晶体管还包括沉积在电介质层上的抗反射涂层。

38. 发明授权

US08598713B2 Deep silicon via for grounding of circuits and devices, emitter ballasting and isolation 有权
标题翻译：深硅通孔用于电路和器件的接地，发射极的镇流和隔离
公开(公告)号：US08598713B2
公开(公告)日：2013-12-03
申请号：US12800663
申请日：2010-05-20
申请人： Volker Blaschke , Todd Thibeault , Chris Cureton , Paul Hurwitz , Arjun Kar-Roy , David Howard , Marco Racanelli
发明人： Volker Blaschke , Todd Thibeault , Chris Cureton , Paul Hurwitz , Arjun Kar-Roy , David Howard , Marco Racanelli
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/743 , H01L2924/0002 , H01L2924/00
摘要： According to an exemplary embodiment, a semiconductor die including at least one deep silicon via is provided. The deep silicon via comprises a deep silicon via opening that extends through at least one pre-metal dielectric layer of the semiconductor die, at least one epitaxial layer of the semiconductor die, and partially into a conductive substrate of the semiconductor die. The deep silicon via further comprises a conductive plug situated in the deep silicon via opening and forming an electrical contact with the conductive substrate. The deep silicon via may include a sidewall dielectric layer and a bottom conductive layer. A method for making a deep silicon via is also disclosed. The deep silicon via is used to, for example, provide a ground connection for power transistors in the semiconductor die.
摘要翻译：根据示例性实施例，提供了包括至少一个深硅通孔的半导体管芯。深硅通孔包括深硅通孔开口，其延伸穿过半导体管芯的至少一个预金属介电层，半导体管芯的至少一个外延层，并且部分地延伸到半导体管芯的导电衬底中。深硅通孔还包括通过开口位于深硅中的导电塞，并与导电基底形成电接触。深硅通孔可以包括侧壁电介质层和底部导电层。还公开了制造深硅通孔的方法。深硅通孔用于例如为半导体管芯中的功率晶体管提供接地连接。

39. 发明授权

US07589009B1 Method for fabricating a top conductive layer in a semiconductor die and related structure 失效
标题翻译：在半导体管芯中制造顶部导电层的方法和相关结构
公开(公告)号：US07589009B1
公开(公告)日：2009-09-15
申请号：US11641925
申请日：2006-12-18
申请人： Arjun Kar-Roy , Marco Racanelli , David J. Howard
发明人： Arjun Kar-Roy , Marco Racanelli , David J. Howard
IPC分类号： H01L21/4763
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： According to an exemplary embodiment, a method for fabricating a top conductive layer in a semiconductor die includes forming a through-wafer via opening through at least one interlayer dielectric layer in a through-wafer via region of the semiconductor die. The method further includes extending the through-wafer via opening through a substrate of the semiconductor die to reach a target depth. The method further includes forming a through-wafer via conductive layer in the through-wafer via opening, and concurrently forming the top conductive layer over an exposed top metal segment.
摘要翻译：根据示例性实施例，用于在半导体管芯中制造顶部导电层的方法包括：通过半导体管芯的通孔区域中的至少一个层间电介质层开口形成贯通晶片。该方法还包括通过半导体管芯的衬底经由开口延伸穿透晶片以达到目标深度。该方法还包括通过开孔通过晶片的导电层形成贯通晶片，同时在暴露的顶部金属片上形成顶部导电层。

40. 发明授权

US07217613B2 Low cost fabrication of high resistivity resistors 有权
标题翻译：低成本制造高电阻率电阻器
公开(公告)号：US07217613B2
公开(公告)日：2007-05-15
申请号：US09833953
申请日：2001-04-11
申请人： Marco Racanelli
发明人： Marco Racanelli
IPC分类号： H01L21/8234
CPC分类号： H01L27/0629 , H01L27/1203 , H01L28/20
摘要： In one disclosed embodiment a layer is formed over a transistor gate and a field oxide region. For example, a polycrystalline silicon layer can be deposited over a PFET gate oxide and a silicon dioxide isolation region on the same chip. The layer is then doped over the transistor gate without doping the layer over the field oxide. A photoresist layer can be used as a barrier to implant doping, for example, to block N+ doping over the field oxide region. The entire layer is then doped, for example, with P type dopant after removal of the doping barrier. The second doping results in formation of a high resistivity resistor over the field oxide region, without affecting the transistor gate. Contact regions are then formed of a silicide, for example, for connecting the resistor to other devices.
摘要翻译：在一个公开的实施例中，在晶体管栅极和场氧化物区域上形成一层。例如，可以在同一芯片上的PFET栅极氧化物和二氧化硅隔离区上沉积多晶硅层。然后将该层掺杂在晶体管栅极上，而不会在场氧化物上掺杂层。光致抗蚀剂层可用作注入掺杂的势垒，例如阻挡在场氧化物区域上的N +掺杂。然后，在去除掺杂阻挡层之后，例如用P型掺杂剂掺杂整个层。第二掺杂导致在场氧化物区域上形成高电阻率电阻器，而不影响晶体管栅极。然后，接触区域由硅化物形成，例如用于将电阻器连接到其它器件。

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