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1. 发明申请

US20050040465A1 CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture 失效
标题翻译：具有沉积的升高源极/漏极的超薄SOI上的CMOS器件及其制造方法
公开(公告)号：US20050040465A1
公开(公告)日：2005-02-24
申请号：US10952286
申请日：2004-09-28
申请人： Heemyong Park , Byoung Lee , Paul Agnello , Dominic Schepis , Ghavam Shahidi
发明人： Heemyong Park , Byoung Lee , Paul Agnello , Dominic Schepis , Ghavam Shahidi
IPC分类号： H01L21/28 , H01L21/00 , H01L21/336 , H01L21/76 , H01L21/762 , H01L21/8238 , H01L21/84 , H01L27/01 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/74 , H01L29/76 , H01L29/78 , H01L29/786 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/78612 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/66772
摘要： A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer; forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and heating the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.
摘要翻译： CMOS器件的方法和结构包括在掩埋氧化物（BOX）衬底上沉积硅绝缘体（SOI）晶片，其中SOI晶片具有预定厚度; 在所述SOI晶片上形成栅电介质; 在所述BOX衬底上形成浅沟槽隔离（STI）区域，其中所述STI区域被配置为具有大致圆角; 在所述栅极电介质上形成栅极结构; 在SOI晶片上沉积注入层; 在SOI晶片和植入层中执行N型和P型掺杂剂注入之一; 以及加热所述器件以从所述注入层和所述SOI晶片形成源极和漏极区域，其中所述源极和漏极区域具有大于所述SOI晶片的预定厚度的厚度，其中所述栅极电介质位于所述STI区域之下。

2. 发明授权

US06509241B2 Process for fabricating an MOS device having highly-localized halo regions 失效
公开(公告)号：US06509241B2
公开(公告)日：2003-01-21
申请号：US09734754
申请日：2000-12-12
申请人： Heemyong Park , Anda C. Mocuta , Paul A. Ronsheim
发明人： Heemyong Park , Anda C. Mocuta , Paul A. Ronsheim
IPC分类号： H01L21336
CPC分类号： H01L29/66636 , H01L21/26506 , H01L21/26513 , H01L21/84 , H01L27/1203 , H01L29/1045 , H01L29/1083 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66772 , H01L29/78621 , H01L29/78684
摘要： A process for fabricating an MOS device having a highly-localized halo region includes the formation of a first halo region at a first surface of a silicon substrate, and a second halo region at a second surface of the silicon substrate. The second surface of the silicon substrate is formed by anisotropically etching the first surface of the silicon substrate to remove a portion of the material from the substrate. Both the first and second halo regions are formed by low-energy ion implantation. For the fabrication of an n-channel device, boron is implanted at an energy of no more than about 1 keV. Upon implantation and a subsequent annealing process, the first and second halo regions form a continuous halo region within the semiconductor substrate.

3. 发明授权

US5872374A Vertical semiconductor device 失效
标题翻译：垂直半导体器件
公开(公告)号：US5872374A
公开(公告)日：1999-02-16
申请号：US625016
申请日：1996-03-29
申请人： Zhirong Tang , Heemyong Park , Jenny M. Ford
发明人： Zhirong Tang , Heemyong Park , Jenny M. Ford
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/10 , H01L29/78 , H01L29/76
CPC分类号： H01L29/66666 , H01L21/823885 , H01L27/0928 , H01L29/1037 , H01L29/1045 , H01L29/7827
摘要： An n-channel device (10) and a p-channel device (11) are formed from a single epitaxial silicon layer (60,61). During the deposition of the single epitaxial silicon layer (60,61), dopants are added to the epitaxial reaction chamber and subsequently changed to define a drain region (24,33), a channel region (27,34), and a source region (30,35). The dopant concentration is modified during the formation of the channel region (27,34) to create a doping profile (50). The doping profile (50) has a first profile (51) that is constant and a second profile (52) that changes.
摘要翻译：由单个外延硅层（60,61）形成n沟道器件（10）和p沟道器件（11）。在沉积单个外延硅层（60,61）期间，将掺杂物添加到外延反应室中，随后改变为限定漏极区（24,33），沟道区（27,34）和源极区（30,35）。掺杂剂浓度在沟道区（27,34）的形成过程中被修改以产生掺杂分布（50）。掺杂分布（50）具有恒定的第一分布（51）和改变的第二分布（52）。

4. 发明授权

US06891228B2 CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture 失效
标题翻译：具有沉积的升高源极/漏极的超薄SOI上的CMOS器件及其制造方法
公开(公告)号：US06891228B2
公开(公告)日：2005-05-10
申请号：US10952286
申请日：2004-09-28
申请人： Heemyong Park , Byoung H. Lee , Paul D. Agnello , Dominic J. Schepis , Ghavam G. Shahidi
发明人： Heemyong Park , Byoung H. Lee , Paul D. Agnello , Dominic J. Schepis , Ghavam G. Shahidi
IPC分类号： H01L21/28 , H01L21/00 , H01L21/336 , H01L21/76 , H01L21/762 , H01L21/8238 , H01L21/84 , H01L27/01 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/74 , H01L29/76 , H01L29/78 , H01L29/786 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/78612 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/66772
摘要： A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer, forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and hearing the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.
摘要翻译： CMOS器件的方法和结构包括在掩埋氧化物（BOX）衬底上沉积硅绝缘体（SOI）晶片，其中SOI晶片具有预定厚度; 在所述SOI晶片上形成栅极电介质，在所述BOX衬底上形成浅沟槽隔离（STI）区域，其中所述STI区域被配置为具有大致圆角; 在所述栅极电介质上形成栅极结构; 在SOI晶片上沉积注入层; 在SOI晶片和植入层中执行N型和P型掺杂剂注入之一; 并且从所述注入层和所述SOI晶片听到所述器件以形成源极和漏极区域，其中所述源极和漏极区域具有大于所述SOI晶片的预定厚度的厚度，其中所述栅极电介质位于比所述STI区域低的位置。

5. 发明授权

US06303450B1 CMOS device structures and method of making same 有权
标题翻译： CMOS器件结构及其制作方法
公开(公告)号：US06303450B1
公开(公告)日：2001-10-16
申请号：US09717971
申请日：2000-11-21
申请人： Heemyong Park , Anda C. Mocuta , Werner Rausch
发明人： Heemyong Park , Anda C. Mocuta , Werner Rausch
IPC分类号： H01L21336
CPC分类号： H01L29/66772 , H01L29/41733 , H01L29/78618 , H01L29/78684
摘要： Disclosed is a method comprising providing a silicon surface with an underlying insulator layer, providing a plurality of gates adjacent to source/drain regions, growing source/drains between the said gates such that the source/drains are thicker in regions of larger gate-to-gate pitch, and doping the source/drains with one or more dopants such that the dopants abut the underlying insulator layer.
摘要翻译：公开了一种方法，包括向硅表面提供下面的绝缘体层，提供与源极/漏极区域相邻的多个栅极，在所述栅极之间生长源极/漏极，使得源极/漏极在较大的栅极 - - 门间距，并用一种或多种掺杂剂掺杂源极/漏极，使得掺杂剂邻接下面的绝缘体层。

6. 发明授权

US5780352A Method of forming an isolation oxide for silicon-on-insulator technology 失效
标题翻译：形成绝缘体上硅技术的隔离氧化物的方法
公开(公告)号：US5780352A
公开(公告)日：1998-07-14
申请号：US553801
申请日：1995-10-23
申请人： Heemyong Park , Wen-Ling Margaret Huang , Juergen Foerstner , Marco Racanelli
发明人： Heemyong Park , Wen-Ling Margaret Huang , Juergen Foerstner , Marco Racanelli
IPC分类号： H01L21/316 , H01L21/32 , H01L21/76 , H01L21/762 , H01L27/12
CPC分类号： H01L21/76264 , H01L21/32 , H01L21/76281
摘要： A method of forming an isolation oxide (30) on a silicon-on-insulator (SOI) substrate (21) includes disposing a mask layer (26, 27) over a region of a silicon layer (24) of the SOI substrate (21). The isolation oxide (30) is grown in a different region (28) of the silicon layer (24). The isolation oxide (30) is grown to a depth (32) within the silicon layer (24) of less than or equal to a thickness (29) of the silicon layer (24). After removing the mask layer (26, 27), the isolation oxide (30) is further grown in the different region (28) of the silicon layer (24) such that the isolation oxide (30) is coupled to a buried electrically insulating layer (23) within the SOI substrate (21). The buried electrically insulating layer (23) and the isolation oxide (30) electrically isolate an active region (43) of a semiconductor device (20).
摘要翻译：在绝缘体上硅（SOI）衬底（21）上形成隔离氧化物（30）的方法包括在SOI衬底（21）的硅层（24）的区域上设置掩模层（26,27））。隔离氧化物（30）生长在硅层（24）的不同区域（28）中。隔离氧化物（30）生长到硅层（24）内的深度（32）小于或等于硅层（24）的厚度（29）。在去除掩模层（26,27）之后，隔离氧化物（30）进一步生长在硅层（24）的不同区域（28）中，使得隔离氧化物（30）与掩埋电绝缘层（23）内。埋入的电绝缘层（23）和隔离氧化物（30）电绝缘半导体器件（20）的有源区（43）。

7. 发明授权

US06492232B1 Method of manufacturing vertical semiconductor device 失效
标题翻译：垂直半导体器件制造方法
公开(公告)号：US06492232B1
公开(公告)日：2002-12-10
申请号：US09563796
申请日：2000-05-02
申请人： Zhirong Tang , Heemyong Park , Jenny M. Ford
发明人： Zhirong Tang , Heemyong Park , Jenny M. Ford
IPC分类号： H01L21336
CPC分类号： H01L29/66666 , H01L21/823885 , H01L29/1045 , H01L29/7827
摘要： An n-channel device (10) and a p-channel device (11) are formed from a single epitaxial silicon layer (60,61). During the deposition of the single epitaxial silicon layer (60,61), dopants are added to the epitaxial reaction chamber and subsequently changed to define a drain region (24,33), a channel region (27,34), and a source region (30,35). The dopant concentration is modified during the formation of the channel region (27,34) to create a doping profile (50). The doping profile (50) has a first profile (51) that is constant and a second profile (52) that changes.
摘要翻译：由单个外延硅层（60,61）形成n沟道器件（10）和p沟道器件（11）。在沉积单个外延硅层（60,61）期间，将掺杂物添加到外延反应室中，随后改变为限定漏极区（24,33），沟道区（27,34）和源极区（30,35）。掺杂剂浓度在沟道区（27,34）的形成过程中被修改以产生掺杂分布（50）。掺杂分布（50）具有恒定的第一分布（51）和改变的第二分布（52）。

8. 发明授权

US06429084B1 MOS transistors with raised sources and drains 失效
标题翻译： MOS晶体管具有升高的源极和漏极
公开(公告)号：US06429084B1
公开(公告)日：2002-08-06
申请号：US09885828
申请日：2001-06-20
申请人： Heemyong Park , Fariborz Assaderaghi , Dominic J. Schepis
发明人： Heemyong Park , Fariborz Assaderaghi , Dominic J. Schepis
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L29/41783 , H01L29/458 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/66772 , H01L29/78618 , H01L29/78621
摘要： In raised source/drain CMOS processing, the prior art problem of lateral epi growth on the gate stack interfering physically with the raised S/D structures and producing device characteristics that vary along the length of the gate and the problem of overetch of the STI oxide during the preclean step is solved by using a sacrificial nitride layer to block both the STI region and the gate stack, together with a process sequence in which the halo and extension implants are performed after the S/D implant anneal.
摘要翻译：在升高的源极/漏极CMOS处理中，现有技术的栅极堆叠上的外延生长问题在物理上与升高的S / D结构物质干扰并产生沿栅极长度变化的器件特性以及STI氧化物的过蚀刻问题在预清洗步骤期间，通过使用牺牲氮化物层来阻止STI区域和栅极堆叠，以及在S / D注入退火之后执行卤素和延伸注入的工艺顺序来解决。

9. 发明授权

US06268640B1 Forming steep lateral doping distribution at source/drain junctions 失效
标题翻译：在源极/漏极结处形成陡峭的横向掺杂分布
公开(公告)号：US06268640B1
公开(公告)日：2001-07-31
申请号：US09373161
申请日：1999-08-12
申请人： Heemyong Park , Yuan Taur , Hsing-Jen C. Wann
发明人： Heemyong Park , Yuan Taur , Hsing-Jen C. Wann
IPC分类号： H01L2972
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26586 , H01L29/1083 , H01L29/7836
摘要： A semiconductor device is fabricated by implanting into a semiconductor substrate non-doping ions at a tilt angle of at least about 10° to laterally extend preamorphization of the substrate portion and then implanting into the substrate dopants for providing source/drain extensions or halo doping or both.
摘要翻译：半导体器件通过将半导体衬底注入至少约10°的倾斜角度的非掺杂离子来制造，以横向延伸衬底部分的预变形，然后将其注入到用于提供源极/漏极扩展或晕圈掺杂的衬底掺杂物中，都。

10. 发明授权

US5817561A Insulated gate semiconductor device and method of manufacture 失效
标题翻译：绝缘栅半导体器件及其制造方法
公开(公告)号：US5817561A
公开(公告)日：1998-10-06
申请号：US720509
申请日：1996-09-30
申请人： Heemyong Park , Vida Ilderem , Andreas A. Wild
发明人： Heemyong Park , Vida Ilderem , Andreas A. Wild
IPC分类号： H01L21/28 , H01L21/336 , H01L29/08 , H01L29/423 , H01L29/78 , H01L21/3205
CPC分类号： H01L29/66659 , H01L21/28114 , H01L21/2815 , H01L29/0847 , H01L29/42376 , H01L29/7835
摘要： An insulated gate semiconductor device (10) has a double spacer gate structure (45). To form the gate structure (45), a stack having sidewalls (22) is formed over a major surface (12) of a semiconductor substrate (11). A gate oxide (23) is then formed over the major surface (12) adjacent the sidewalls (22). A first polysilicon layer (24) is deposited on the gate oxide (23) and the stack. The first polysilicon layer (24) is etched to form a first conductive spacer (32) of the gate structure (45). A second polysilicon layer (44) is deposited on first spacer (32) and the stack. The second polysilicon layer (44) is then etched to form a second conductive spacer (46) of the gate structure (45). Because the double spacer gate structure (45) is formed without relying on photolithographic techniques, its size is smaller than the size of a gate structure formed using conventional photolithography.
摘要翻译：绝缘栅半导体器件（10）具有双间隔栅极结构（45）。为了形成栅极结构（45），在半导体衬底（11）的主表面（12）上形成具有侧壁（22）的叠层。然后在邻近侧壁（22）的主表面（12）上形成栅极氧化物（23）。第一多晶硅层（24）沉积在栅极氧化物（23）和堆叠上。蚀刻第一多晶硅层（24）以形成栅极结构（45）的第一导电间隔物（32）。第二多晶硅层（44）沉积在第一间隔物（32）和堆叠体上。然后蚀刻第二多晶硅层（44）以形成栅极结构（45）的第二导电间隔物（46）。由于双重间隔栅极结构（45）不依赖于光刻技术而形成，因此其尺寸小于使用常规光刻形成的栅极结构的尺寸。

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