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1. 发明授权

US07704874B1 Method for fabricating a frontside through-wafer via in a processed wafer and related structure 有权
标题翻译：用于在经处理的晶片中制造前侧贯穿晶片通孔的方法及相关结构
公开(公告)号：US07704874B1
公开(公告)日：2010-04-27
申请号：US11641500
申请日：2006-12-18
申请人： Arjun Kar-Roy , Marco Racanelli , David J. Howard
发明人： Arjun Kar-Roy , Marco Racanelli , David J. Howard
IPC分类号： H01L21/4763
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： According to an exemplary embodiment, a method for fabricating a frontside through-wafer via in a processed wafer includes forming a through-wafer via opening through at least one interlayer dielectric layer in a through-wafer via region of the processed wafer. The method further includes extending the through-wafer via opening through a substrate to a target depth. The method further includes forming a first conductive layer in the through-wafer via opening and over a through-wafer via pad, which is situated over the at least one interlayer dielectric layer. The first conductive layer in the through-wafer via opening forms an electrical connection between the substrate and the through-wafer via pad. The method further includes forming a second conductive layer on the backside surface of the processed wafer, where the second conductive layer is in electrical contact with the first conductive layer and the substrate.
摘要翻译：根据示例性实施例，一种用于在经处理的晶片中制造前侧贯通晶片通孔的方法包括通过开孔穿过晶片经过处理晶片的区域中的至少一个层间电介质层形成贯通晶片。该方法进一步包括将通过基板的开口穿过晶片延伸到目标深度。该方法还包括通过开口在穿通晶片中形成第一导电层，并且穿过位于至少一个层间介电层上的贯通晶片通孔焊盘。贯通晶片通孔开口中的第一导电层在衬底和贯通晶片通孔焊盘之间形成电连接。所述方法还包括在所述经处理晶片的背面上形成第二导电层，其中所述第二导电层与所述第一导电层和所述衬底电接触。

2. 发明授权

US08212331B1 Method for fabricating a backside through-wafer via in a processed wafer and related structure 有权
标题翻译：在加工晶片中制造背面通晶片通孔的方法及相关结构
公开(公告)号：US08212331B1
公开(公告)日：2012-07-03
申请号：US11787063
申请日：2007-04-13
申请人： Arjun Kar-Roy , Marco Racanelli , David J. Howard
发明人： Arjun Kar-Roy , Marco Racanelli , David J. Howard
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76898 , H01L21/6835 , H01L23/481 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , H01L2924/0002 , H01L2924/00
摘要： According to an exemplary embodiment, a method for fabricating a backside through-wafer via in a processed wafer includes forming a through-wafer via opening through a substrate and extending the through-wafer via opening through at least one interlayer dielectric layer situated over the substrate. The method further includes forming a metal layer in the through-wafer via opening, where the metal layer forms an electrical connection to substrate. The metal layer is also in electrical contact with an interconnect metal segment situated above the at least one interlayer dielectric layer. The method further includes performing a thinning process to reduce the substrate to a target thickness before forming the through-wafer via opening. The method further includes forming an electrically conductive passivation layer on the metal layer and over a bottom surface of the substrate, where the electrically conductive passivation layer is in electrical contact with the metal layer and the substrate.
摘要翻译：根据示例性实施例，一种用于在经处理的晶片中制造背面通晶片通孔的方法包括通过开口穿过衬底形成贯通晶片，并且通过开口延伸穿过晶片穿过位于衬底上方的至少一个层间介电层。该方法还包括在通孔开口中形成金属层，其中金属层与基底形成电连接。金属层也与位于至少一个层间介电层上方的互连金属片电接触。该方法还包括进行薄化处理以在通过开口形成通晶片之前将基板减小到目标厚度。该方法还包括在金属层上和衬底的底表面上形成导电钝化层，其中导电钝化层与金属层和衬底电接触。

3. 发明授权

US07897484B2 Fabricating a top conductive layer in a semiconductor die 有权
标题翻译：在半导体管芯中制造顶部导电层
公开(公告)号：US07897484B2
公开(公告)日：2011-03-01
申请号：US12462436
申请日：2009-08-03
申请人： Arjun Kar-Roy , Marco Racanelli , David J. Howard
发明人： Arjun Kar-Roy , Marco Racanelli , David J. Howard
IPC分类号： H01L21/00
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： According to an exemplary embodiment, a method for fabricating a top conductive layer in a semiconductor die includes forming a through-wafer via opening through at least one interlayer dielectric layer in a through-wafer via region of the semiconductor die. The method further includes extending the through-wafer via opening through a substrate of the semiconductor die to reach a target depth. The method further includes forming a through-wafer via conductive layer in the through-wafer via opening, and concurrently forming the top conductive layer over an exposed top metal segment.
摘要翻译：根据示例性实施例，用于在半导体管芯中制造顶部导电层的方法包括：通过半导体管芯的通孔区域中的至少一个层间电介质层开口形成贯通晶片。该方法还包括通过半导体管芯的衬底经由开口延伸穿透晶片以达到目标深度。该方法还包括通过开孔通过晶片的导电层形成贯通晶片，同时在暴露的顶部金属片上形成顶部导电层。

4. 发明申请

US20090298285A1 Fabricating a Top Conductive Layer in a Semiconductor Die 有权
标题翻译：在半导体模具中制造顶部导电层
公开(公告)号：US20090298285A1
公开(公告)日：2009-12-03
申请号：US12462436
申请日：2009-08-03
申请人： Arjun Kar-Roy , Marco Racanelli , David J. Howard
发明人： Arjun Kar-Roy , Marco Racanelli , David J. Howard
IPC分类号： H01L21/768
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： According to an exemplary embodiment, a method for fabricating a top conductive layer in a semiconductor die includes forming a through-wafer via opening through at least one interlayer dielectric layer in a through-wafer via region of the semiconductor die. The method further includes extending the through-wafer via opening through a substrate of the semiconductor die to reach a target depth. The method further includes forming a through-wafer via conductive layer in the through-wafer via opening, and concurrently forming the top conductive layer over an exposed top metal segment.
摘要翻译：根据示例性实施例，用于在半导体管芯中制造顶部导电层的方法包括：通过半导体管芯的通孔区域中的至少一个层间电介质层开口形成贯通晶片。该方法还包括通过半导体管芯的衬底经由开口延伸穿透晶片以达到目标深度。该方法还包括通过开孔通过晶片的导电层形成贯通晶片，同时在暴露的顶部金属片上形成顶部导电层。

5. 发明授权

US07589009B1 Method for fabricating a top conductive layer in a semiconductor die and related structure 失效
标题翻译：在半导体管芯中制造顶部导电层的方法和相关结构
公开(公告)号：US07589009B1
公开(公告)日：2009-09-15
申请号：US11641925
申请日：2006-12-18
申请人： Arjun Kar-Roy , Marco Racanelli , David J. Howard
发明人： Arjun Kar-Roy , Marco Racanelli , David J. Howard
IPC分类号： H01L21/4763
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： According to an exemplary embodiment, a method for fabricating a top conductive layer in a semiconductor die includes forming a through-wafer via opening through at least one interlayer dielectric layer in a through-wafer via region of the semiconductor die. The method further includes extending the through-wafer via opening through a substrate of the semiconductor die to reach a target depth. The method further includes forming a through-wafer via conductive layer in the through-wafer via opening, and concurrently forming the top conductive layer over an exposed top metal segment.
摘要翻译：根据示例性实施例，用于在半导体管芯中制造顶部导电层的方法包括：通过半导体管芯的通孔区域中的至少一个层间电介质层开口形成贯通晶片。该方法还包括通过半导体管芯的衬底经由开口延伸穿透晶片以达到目标深度。该方法还包括通过开孔通过晶片的导电层形成贯通晶片，同时在暴露的顶部金属片上形成顶部导电层。

6. 发明授权

US07772673B1 Deep trench isolation and method for forming same 有权
标题翻译：深沟槽隔离及其形成方法
公开(公告)号：US07772673B1
公开(公告)日：2010-08-10
申请号：US11724916
申请日：2007-03-16
申请人： Kevin Q. Yin , Amol Kalburge , David J. Howard , Arjun Kar-Roy , Dieter Dornisch
发明人： Kevin Q. Yin , Amol Kalburge , David J. Howard , Arjun Kar-Roy , Dieter Dornisch
IPC分类号： H01L21/04
CPC分类号： H01L29/0692 , H01L21/763 , H01L29/66272 , H01L29/732
摘要： According to one exemplary embodiment, a semiconductor die including at least one deep trench isolation region for isolating an electronic device (for example, a bipolar device) includes a trench situated in a substrate of the semiconductor die, where the trench has sides surrounding the electronic device, and where the trench has at least one trench chamfered corner formed between and connecting the sides of the trench. The at least one trench chamferred corner is formed between a chamfered corner of an outside wall of said trench and a corner of an inside wall of the trench. A trench corner width at the at least one trench chamfered corner is less than a trench side width along the sides of the trench.
摘要翻译：根据一个示例性实施例，包括用于隔离电子器件（例如，双极器件）的至少一个深沟槽隔离区域的半导体管芯包括位于半导体管芯的衬底中的沟槽，其中沟槽具有围绕电子器件器件，并且其中沟槽具有形成在沟槽的侧面之间并连接沟槽的侧面的至少一个沟槽倒角。所述至少一个沟槽倒角形成在所述沟槽的外壁的倒角角和沟槽的内壁的角部之间。在至少一个沟槽倒角处的沟槽角宽度小于沿着沟槽的侧面的沟槽侧宽度。

7. 发明授权

US07709949B2 Densely packed metal segments patterned in a semiconductor die 有权
标题翻译：图案化在半导体芯片中的密集金属片段
公开(公告)号：US07709949B2
公开(公告)日：2010-05-04
申请号：US11112194
申请日：2005-04-22
申请人： Tinghao F. Wang , Dieter Dornisch , Julia M. Wu , Hadi Abdul-Ridha , David J. Howard
发明人： Tinghao F. Wang , Dieter Dornisch , Julia M. Wu , Hadi Abdul-Ridha , David J. Howard
IPC分类号： H01L23/48
CPC分类号： H01L21/02071 , H01L21/32136 , H01L21/76885 , Y10S438/942 , Y10S438/945
摘要： A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the open region and etching the metal layer at a second etch rate to form a number of metal segments in the dense region, where the first etch rate is approximately equal to the second etch rate. The method further comprises performing a number of strip/passivate cycles to remove a polymer formed on sidewalls of the metal segments in the dense region. The sidewalls of the metal segments in the dense region undergo substantially no undercutting and residue is removed from the sidewalls of the metal segments in the dense region.
摘要翻译：在半导体管芯中图案化金属层的方法包括在金属层上形成掩模以限定开放区域和致密区域。该方法还包括以第一蚀刻速率蚀刻金属层以在开放区域中形成多个金属段，并以第二蚀刻速率蚀刻金属层，以在致密区域中形成多个金属段，其中第一蚀刻速率近似等于第二蚀刻速率。该方法还包括执行多个带/钝化循环以去除在致密区域中金属段的侧壁上形成的聚合物。致密区域中的金属段的侧壁基本上不会发生底切，并且在致密区域中的金属段的侧壁上除去残留物。

8. 发明授权

US06919272B2 Method for patterning densely packed metal segments in a semiconductor die and related structure 有权
标题翻译：图案化半导体管芯中紧密堆积的金属段和相关结构的方法
公开(公告)号：US06919272B2
公开(公告)日：2005-07-19
申请号：US10356447
申请日：2003-02-01
申请人： Tinghao F. Wang , Dieter Dornisch , Julia M. Wu , Hadi Abdul-Ridha , David J. Howard
发明人： Tinghao F. Wang , Dieter Dornisch , Julia M. Wu , Hadi Abdul-Ridha , David J. Howard
IPC分类号： H01L21/02 , H01L21/3205 , H01L21/3213 , H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/02071 , H01L21/32136 , H01L21/76885 , Y10S438/942 , Y10S438/945
摘要： A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the open region and etching the metal layer at a second etch rate to form a number of metal segments in the dense region, where the first etch rate is approximately equal to the second etch rate. The method further comprises performing a number of strip/passivate cycles to remove a polymer formed on sidewalls of the metal segments in the dense region. The sidewalls of the metal segments in the dense region undergo substantially no undercutting and residue is removed from the sidewalls of the metal segments in the dense region.
摘要翻译：在半导体管芯中图案化金属层的方法包括在金属层上形成掩模以限定开放区域和致密区域。该方法还包括以第一蚀刻速率蚀刻金属层以在开放区域中形成多个金属段，并以第二蚀刻速率蚀刻金属层，以在致密区域中形成多个金属段，其中第一蚀刻速率近似等于第二蚀刻速率。该方法还包括执行多个带/钝化循环以去除在致密区域中金属段的侧壁上形成的聚合物。致密区域中的金属段的侧壁基本上不会发生底切，并且在致密区域中的金属段的侧壁上除去残留物。

9. 发明授权

US4786917A Signal processing for a thermal printer 失效
标题翻译：热敏打印机的信号处理
公开(公告)号：US4786917A
公开(公告)日：1988-11-22
申请号：US56925
申请日：1987-06-03
申请人： Edward A. Hauschild , David J. Howard
发明人： Edward A. Hauschild , David J. Howard
IPC分类号： G06F3/12 , B41J2/355 , B41J35/18 , H04N1/23 , H04N1/40 , H04N1/407 , H04N1/409 , H04N1/58 , G01D15/10
CPC分类号： B41J2/3555 , B41J2/355 , B41J35/18 , H04N1/4092 , H04N1/58
摘要： A signal processing for a color thermal printing apparatus first corrects contrast and color and then provides edge enhancement.
摘要翻译：用于彩色热敏打印设备的信号处理首先校正对比度和颜色，然后提供边缘增强。

10. 发明授权

US09098610B2 Communication for implantable medical devices 有权
标题翻译：可植入医疗器械的通讯
公开(公告)号：US09098610B2
公开(公告)日：2015-08-04
申请号：US13334361
申请日：2011-12-22
申请人： Richard J. Polefko , David J. Howard , Scott G. Leyh , Steven E. Wilder
发明人： Richard J. Polefko , David J. Howard , Scott G. Leyh , Steven E. Wilder
IPC分类号： G06F15/16 , G06F19/00 , G06Q10/10
CPC分类号： H04B7/26 , A61N1/37252 , G06F19/00 , G06F19/3418 , G06Q10/10 , H04L45/745
摘要： Systems and methods for communication between an implantable medical device and an external device. Data blocks are generated and transmitted between the implantable device and the external device. The data blocks include a first flag indicating whether the data block is a first data block in a message and when the data block is a subsequent data block in a multiple data block message. When the first flag indicates that the data block is a first data block in a message, the data block also contains a device ID, a command token, and message content. When the first flag indicates that the data block is a subsequent data block in a multiple data block message, the data block contains additional message content that is appended to message content from a previously received data block.
摘要翻译：可植入医疗设备和外部设备之间的通信的系统和方法。数据块在可植入设备和外部设备之间生成和传输。数据块包括指示数据块是否是消息中的第一数据块的第一标志，以及数据块是否是多数据块消息中的后续数据块。当第一标志指示数据块是消息中的第一数据块时，数据块还包含设备ID，命令令牌和消息内容。当第一标志指示数据块是多数据块消息中的后续数据块时，数据块包含从先前接收的数据块附加到消息内容的附加消息内容。

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