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1. 发明授权

US08598713B2 Deep silicon via for grounding of circuits and devices, emitter ballasting and isolation 有权
标题翻译：深硅通孔用于电路和器件的接地，发射极的镇流和隔离
公开(公告)号：US08598713B2
公开(公告)日：2013-12-03
申请号：US12800663
申请日：2010-05-20
申请人： Volker Blaschke , Todd Thibeault , Chris Cureton , Paul Hurwitz , Arjun Kar-Roy , David Howard , Marco Racanelli
发明人： Volker Blaschke , Todd Thibeault , Chris Cureton , Paul Hurwitz , Arjun Kar-Roy , David Howard , Marco Racanelli
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/743 , H01L2924/0002 , H01L2924/00
摘要： According to an exemplary embodiment, a semiconductor die including at least one deep silicon via is provided. The deep silicon via comprises a deep silicon via opening that extends through at least one pre-metal dielectric layer of the semiconductor die, at least one epitaxial layer of the semiconductor die, and partially into a conductive substrate of the semiconductor die. The deep silicon via further comprises a conductive plug situated in the deep silicon via opening and forming an electrical contact with the conductive substrate. The deep silicon via may include a sidewall dielectric layer and a bottom conductive layer. A method for making a deep silicon via is also disclosed. The deep silicon via is used to, for example, provide a ground connection for power transistors in the semiconductor die.
摘要翻译：根据示例性实施例，提供了包括至少一个深硅通孔的半导体管芯。深硅通孔包括深硅通孔开口，其延伸穿过半导体管芯的至少一个预金属介电层，半导体管芯的至少一个外延层，并且部分地延伸到半导体管芯的导电衬底中。深硅通孔还包括通过开口位于深硅中的导电塞，并与导电基底形成电接触。深硅通孔可以包括侧壁电介质层和底部导电层。还公开了制造深硅通孔的方法。深硅通孔用于例如为半导体管芯中的功率晶体管提供接地连接。

2. 发明申请

US20110018109A1 Deep silicon via for grounding of circuits and devices, emitter ballasting and isolation 有权
标题翻译：深硅通孔用于电路和器件的接地，发射极的镇流和隔离
公开(公告)号：US20110018109A1
公开(公告)日：2011-01-27
申请号：US12800663
申请日：2010-05-20
申请人： Volker Blaschke , Todd Thibeault , Chris Cureton , Paul Hurwitz , Arjun Kar-Roy , David Howard , Marco Racanelli
发明人： Volker Blaschke , Todd Thibeault , Chris Cureton , Paul Hurwitz , Arjun Kar-Roy , David Howard , Marco Racanelli
IPC分类号： H01L29/06 , H01L23/532 , H01L21/768
CPC分类号： H01L21/743 , H01L2924/0002 , H01L2924/00
摘要： According to an exemplary embodiment, a semiconductor die including at least one deep silicon via is provided. The deep silicon via comprises a deep silicon via opening that extends through at least one pre-metal dielectric layer of the semiconductor die, at least one epitaxial layer of the semiconductor die, and partially into a conductive substrate of the semiconductor die. The deep silicon via further comprises a conductive plug situated in the deep silicon via opening and forming an electrical contact with the conductive substrate. The deep silicon via may include a sidewall dielectric layer and a bottom conductive layer. A method for making a deep silicon via is also disclosed. The deep silicon via is used to, for example, provide a ground connection for power transistors in the semiconductor die.
摘要翻译：根据示例性实施例，提供了包括至少一个深硅通孔的半导体管芯。深硅通孔包括深硅通孔开口，其延伸穿过半导体管芯的至少一个预金属介电层，半导体管芯的至少一个外延层，并且部分地延伸到半导体管芯的导电衬底中。深硅通孔还包括通过开口位于深硅中的导电塞，并与导电基底形成电接触。深硅通孔可以包括侧壁电介质层和底部导电层。还公开了制造深硅通孔的方法。深硅通孔用于例如为半导体管芯中的功率晶体管提供接地连接。

3. 发明授权

US07229908B1 System and method for manufacturing an out of plane integrated circuit inductor 有权
标题翻译：用于制造平面外集成电路电感的系统和方法
公开(公告)号：US07229908B1
公开(公告)日：2007-06-12
申请号：US10861563
申请日：2004-06-04
申请人： Sergei Drizlikh , Todd Thibeault
发明人： Sergei Drizlikh , Todd Thibeault
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L28/10
摘要： A system and method is described for manufacturing an out of plane integrated circuit inductor. A plurality of parallel metal bars are formed on a substrate and covered with a first passivation layer. A ferromagnetic core is then deposited over the first passivation layer with its length perpendicular to the plurality of parallel metal bars. A second passivation layer is deposited over the ferromagnetic core and vias are etched through the passivation layers to the alternate ends of the underlying parallel metal bars. A plurality of cross connection metal bars are then formed on the second passivation layer with vertical portions that fill the vias and connect the alternate ends of the plurality of parallel metal bars to form an inductor coil. A third passivation layer is then deposited over the cross connection metal bars.
摘要翻译：描述了用于制造平面外集成电路电感器的系统和方法。多个平行的金属棒形成在衬底上并被第一钝化层覆盖。然后将铁磁芯沉积在第一钝化层上，其长度垂直于多个平行金属棒。第二钝化层沉积在铁磁芯上，并且通孔通过钝化层蚀刻到下面的平行金属棒的交替端。然后在第二钝化层上形成多个交叉金属棒，垂直部分填充通孔并连接多个平行金属棒的交替端以形成电感线圈。然后在交叉连接金属棒上沉积第三钝化层。

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