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11. 发明授权

US5517057A Electronic modules with interconnected surface metallization layers 失效
标题翻译：具有互连表面金属化层的电子模块
公开(公告)号：US5517057A
公开(公告)日：1996-05-14
申请号：US451356
申请日：1995-05-26
申请人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , John E. Cronin , Wayne J. Howell , James M. Leas , Robert B. Phillips
发明人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , John E. Cronin , Wayne J. Howell , James M. Leas , Robert B. Phillips
IPC分类号： H01L23/538 , H01L21/98 , H01L25/065 , H01L25/07 , H01L25/18 , H01L23/48 , H01L23/522
CPC分类号： H01L25/50 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2224/24145 , H01L2224/48091 , H01L2224/49109 , H01L2225/0651 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06596 , H01L2924/30107
摘要： Methods of fabrication for electronic modules having electrically interconnected side and end surface metallization layers and associated electronic modules are set forth. The methods include providing a stack comprising a plurality of stacked IC chips. A side surface thin-film metallization layer is formed on the stack. Next, an end surface thin-film metallization layer is formed the stack such that the side surface and end surface thin-film metallization layers directly electrically interconnect. Alternatively, each IC chip of a stack may include an end surface metallization layer such that separate formation of an end surface metallization layer on an end surface of the stack is unnecessary. The methods also include forming an electronic module by first providing a long stack of IC chips, testing the chips of the stack, and then segmenting the long stack into multiple small stacks of functional IC chips based upon the test results. Specific details of electronic modules, IC chips contained therein, and stacks composed thereof are also set forth.
摘要翻译：阐述了具有电互连的侧表面金属化层和相关的电子模块的电子模块的制造方法。所述方法包括提供包括多个堆叠的IC芯片的堆叠。在堆叠上形成侧面薄膜金属化层。接下来，将端面薄膜金属化层形成为堆叠，使得侧表面和端面薄膜金属化层直接电互连。或者，堆叠的每个IC芯片可以包括端面金属化层，使得不需要在堆叠的端表面上分离形成端面金属化层。所述方法还包括通过首先提供长堆叠的IC芯片，测试堆叠的芯片，然后基于测试结果将长堆叠分成多个小堆功能IC芯片来形成电子模块。还阐述了电子模块，其中包含的IC芯片及其组成的具体细节。

12. 发明授权

US4511600A Solar cell metal spray process 失效
标题翻译：太阳能电池金属喷涂工艺
公开(公告)号：US4511600A
公开(公告)日：1985-04-16
申请号：US579126
申请日：1984-02-10
申请人： James M. Leas
发明人： James M. Leas
IPC分类号： H01L31/0224 , H01L31/18 , H01L21/283 , H01L31/04
CPC分类号： H01L31/022425 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： The present invention provides a method of forming a metal pattern on a solar cell comprising the steps of forcing a molten metal through an aligned array of orifices by use of gas pressure; vibrating the aligned array of orifices to form the molten metal issuing from the orifices into metal droplets; moving a solar cell collinearly with the aligned array of orifices; and allowing each series of metal droplets from a single orifice to fall onto a specific region of the solar cell to build up a metal layer of increasing thickness, each metal droplet being permitted sufficient time to solidify prior to allowing the next metal droplet to strike the metal layer.
摘要翻译：本发明提供了一种在太阳能电池上形成金属图案的方法，包括以下步骤：通过使用气体压力迫使熔融金属通过对准阵列的孔; 振动对准的孔口阵列以形成从孔口发出的熔融金属成金属液滴; 与对准的孔阵列共线地移动太阳能电池; 并且允许来自单个孔口的每个系列的金属液滴落入太阳能电池的特定区域以建立增加厚度的金属层，每个金属液滴在允许下一个金属液滴撞击之前被允许足够的时间凝固金属层。

13. 发明授权

US06980748B2 SiGe or germanium flip chip optical receiver 失效
标题翻译： SiGe或锗倒装芯片光接收机
公开(公告)号：US06980748B2
公开(公告)日：2005-12-27
申请号：US09942823
申请日：2001-08-30
申请人： James M. Leas
发明人： James M. Leas
IPC分类号： G02B6/43 , G06F1/10 , H01L31/103 , H04B10/06
CPC分类号： H01L31/1037 , G02B6/43 , G06F1/105
摘要： A synchronized optical clocking signal is provided to a plurality of optical receivers by providing a layer of a high absorption coefficient material, such as SiGe or Ge, on a front surface of a low absorption coefficient substrate, such as silicon. Diodes are formed in the germanium containing layer for receiving an optical signal and converting the optical signal into an electrical signal. An optical clocking signal is shined on the back surface of the silicon substrate. The light has a wavelength long enough so that it penetrates through the silicon substrate to the germanium containing layer. The wavelength is short enough so that the light is absorbed in the germanium containing layer and converted to the electrical clocking signal used for neighboring devices and circuits. The germanium concentration is graded so that minority carriers are quickly swept across junctions of the diodes and collected.
摘要翻译：通过在诸如硅的低吸收系数衬底的前表面上提供诸如SiGe或Ge的高吸收系数材料层，向多个光接收器提供同步光时钟信号。二氧化锗形成在含锗层中，用于接收光信号并将光信号转换为电信号。光时钟信号在硅衬底的背面上发光。光具有足够长的波长，使得其穿透硅衬底到含锗层。波长足够短，使得光被含锗层吸收并转换成用于相邻设备和电路的电时钟信号。锗浓度分级，使得少数载流子快速扫过二极管的接合点并收集。

14. 发明授权

US5980647A Metal removal cleaning process and apparatus 失效
标题翻译：金属去除清洗工艺及设备
公开(公告)号：US5980647A
公开(公告)日：1999-11-09
申请号：US893945
申请日：1997-07-15
申请人： Edward D. Buker , Edward W. Conrad , James M. Leas
发明人： Edward D. Buker , Edward W. Conrad , James M. Leas
IPC分类号： B08B3/04 , B08B3/12 , H01L21/00 , B08B7/04
CPC分类号： H01L21/67051 , B08B3/04 , B08B3/12 , B08B2203/0288
摘要： A megasonic liquid stream semiconductor wafer cleaning apparatus and method uniformly removes debris from all points on the surface of a semiconductor wafer. The wafer is rotated about a proscribed axis while the means for producing focused megasonic waves and a liquid stream of cleaning fluid is focused on the wafer so as to apply sufficient energy to clean the wafer yet not cause damage to the electronic circuity embedded in the wafer. A method is provided for moving the outlet port providing the stream of megasonic cleaning fluid across the wafer so that the amount of energy applied to any area of the wafer is relatively constant.
摘要翻译：兆声波液流半导体晶片清洁装置和方法从半导体晶片表面上的所有点均匀地去除碎屑。晶片围绕禁止的轴线旋转，而用于产生聚焦的超声波和清洁液体的液体的装置聚焦在晶片上，以便施加足够的能量来清洁晶片，而不会损害嵌入在晶片中的电子电路。提供了一种用于移动提供超声波清洗流体流过晶片的出口的方法，使得施加到晶片的任何区域的能量的量相对恒定。

15. 发明授权

US5557114A Optical fet 失效
标题翻译：光学胎
公开(公告)号：US5557114A
公开(公告)日：1996-09-17
申请号：US371916
申请日：1995-01-12
申请人： James M. Leas , Jack A. Mandelman
发明人： James M. Leas , Jack A. Mandelman
IPC分类号： H01L25/04 , H01L31/112 , H01L31/062 , H01L31/113
CPC分类号： H01L25/043 , H01L31/1126 , H01L2924/0002
摘要： An optical FET includes one or more light-responsive diodes stacked on the gate. Each diode includes a planar (horizontal) junction. The number of diodes is chosen to achieve a desired gate to source potential difference. An electrical connection connects the diode(s) to the source of the FET.
摘要翻译：光学FET包括堆叠在栅极上的一个或多个光响应二极管。每个二极管包括平面（水平）结。选择二极管的数量以实现期望的栅极到源极电位差。电气连接将二极管连接到FET的源极。

16. 发明授权

US5373893A Method and apparatus for cooling thermally massive parts in a continuous furnace 失效
标题翻译：用于在连续炉中冷却热块状部件的方法和装置
公开(公告)号：US5373893A
公开(公告)日：1994-12-20
申请号：US963500
申请日：1992-10-19
申请人： David E. Eisenmann , Peter M. Elenius , James M. Leas , Wagih M. Wazni
发明人： David E. Eisenmann , Peter M. Elenius , James M. Leas , Wagih M. Wazni
IPC分类号： C21D1/613 , C21D9/00 , F25D3/11 , F27D15/02 , F27D19/00 , F27D21/00 , G01R31/28 , F25D13/06
CPC分类号： G01R31/2875 , C21D1/613 , C21D9/0062 , F25D3/11 , F27D15/0266 , F27D2019/0034 , F27D2019/0068 , F27D21/00
摘要： A method and apparatus for cooling thermally massive parts includes directing a chilled gas onto an electrical component travelling on the belt of a continuous furnace. The belt is divided into a series of hot and cold zones to provide thermal stressing to the electrical component to detect early life failure. As the component cools, a constant thermal stress is maintained by either lowering the temperature or increasing the flow rate of the chilled gas.
摘要翻译：用于冷却热块状部件的方法和装置包括将冷却的气体引导到在连续炉的带上行进的电气部件上。皮带分为一系列热和冷区域，以向电气部件提供热应激，以检测早期的生命故障。当组件冷却时，通过降低温度或增加冷却气体的流速来保持恒定的热应力。

17. 发明授权

US5294257A Edge masking spin tool 失效
标题翻译：边缘掩蔽旋转工具
公开(公告)号：US5294257A
公开(公告)日：1994-03-15
申请号：US783753
申请日：1991-10-28
申请人： Howard L. Kelly , Hans-George H. Kolan , James M. Leas , Teruhiro Nakasogi
发明人： Howard L. Kelly , Hans-George H. Kolan , James M. Leas , Teruhiro Nakasogi
IPC分类号： B05C11/08 , G03F7/16 , H01L21/00 , H01L21/687 , B05C11/02
CPC分类号： H01L21/67126 , B05C11/08 , G03F7/162 , H01L21/6715 , H01L21/68735
摘要： An apparatus and method for spin coating a substrate with a liquid material which prevents the material from contacting the edge or backside of the substrate or forming an edge bead at the periphery of the substrate is disclosed. A spin chuck is equipped with a conformable elastomer which seals the edge of the substrate and forms a continuous surface with a planar surface of the substrate for the liquid material to flow off the substrate unimpeded during the spin coating process. As the elastomer is resilient, small variations in substrate size and shape are automatically compensated. None of the substrate area is lost to masking and/or removal processes as in the prior art, allowing the entire substrate area to be available for further processing.
摘要翻译：公开了一种用液体材料旋涂衬底的装置和方法，其防止材料接触衬底的边缘或背面或在衬底的周围形成边缘。旋转卡盘配备有适形弹性体，其密封基底的边缘并与基底的平坦表面形成连续表面，以使液体材料在旋涂过程中不受阻碍地流出基底。由于弹性体具有弹性，因此自动补偿基板尺寸和形状的小变化。如现有技术那样，掩模和/或去除过程中没有一个衬底区域损失，允许整个衬底区域可用于进一步处理。

18. 发明授权

US4901329A Integrated laser arrays and support circuits 失效
标题翻译：集成激光阵列和支持电路
公开(公告)号：US4901329A
公开(公告)日：1990-02-13
申请号：US344553
申请日：1989-04-25
申请人： James M. Leas
发明人： James M. Leas
IPC分类号： H01S5/026 , H01S5/028 , H01S5/18 , H01S5/40 , H01S5/42
CPC分类号： H01S5/028 , H01S5/0264 , H01S5/18 , H01S5/42 , H01S5/026 , H01S5/4025
摘要： A two dimensional, surface-emitting array of semiconductor lasers. Lasers disposed on a semiconductor substrate emit light in a direction substantially parallel to the substrate surface into a high index material in which the lasers are embedded. Internal reflectors composed of a low index material, also embedded in the high index material, reflect the laser beams to the surface of the array. The indexes of the low index material and the high index material are chosen so that none of the light enters the internal reflector, and all light is reflected to the laser array surface.
摘要翻译：半导体激光器的二维表面发射阵列。设置在半导体基板上的激光器将基板平行于基板表面的方向发光，成为嵌入激光器的高折射率材料。由低折射率材料组成的内部反射器也嵌入高折射率材料中，将激光束反射到阵列的表面。选择低折射率材料和高折射率材料的指标，使得没有一个光进入内部反射器，并且所有光被反射到激光器阵列表面。

19. 发明授权

US07394268B2 Carrier for test, burn-in, and first level packaging 失效
标题翻译：用于测试，老化和一级包装的载体
公开(公告)号：US07394268B2
公开(公告)日：2008-07-01
申请号：US11531140
申请日：2006-09-12
申请人： Claude L. Bertin , Wayne F. Ellis , Mark W. Kellogg , William R. Tonti , Jerzy M. Zalesinski , James M. Leas , Wayne J. Howell
发明人： Claude L. Bertin , Wayne F. Ellis , Mark W. Kellogg , William R. Tonti , Jerzy M. Zalesinski , James M. Leas , Wayne J. Howell
IPC分类号： G01R31/02
CPC分类号： G01R31/2867 , G11C5/04 , G11C29/06 , G11C29/1201 , G11C29/48 , G11C29/56016 , G11C29/785 , G11C2029/2602 , G11C2029/5602 , H01L22/22 , H01L22/32 , H01L2924/0002 , H01L2924/00
摘要： A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier.
摘要翻译：在载体上提供多个半导体器件用于测试或烧录。然后将载体切割以提供单个芯片上载波部件或多芯片载波部件。载体用作每个芯片的第一级封装。因此，载体用于测试和烧录和包装的双重目的。可以在每个芯片或载体上提供诸如内置自检引擎的引线减少机构，并且连接到载体的触点用于测试和老化步骤。切割后的最终包装包括至少一个已知的良好的模具，并且可以包括载体上的芯片阵列，例如SIMM或DIMM。最终的包装也可以是一堆芯片，每个芯片都安装在单独的载体上。堆叠的载体通过沿着堆叠的侧面安装的基板彼此连接，该基板沿着每个载体的边缘电连接到焊盘一排。

20. 发明授权

US06798017B2 Vertical dual gate field effect transistor 有权
标题翻译：垂直双栅场效应晶体管
公开(公告)号：US06798017B2
公开(公告)日：2004-09-28
申请号：US09944665
申请日：2001-08-31
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , James M. Leas , William H-L Ma , Paul A. Rabidoux
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , James M. Leas , William H-L Ma , Paul A. Rabidoux
IPC分类号： H01L2976
CPC分类号： H01L29/78642 , H01L21/2255 , H01L21/76897 , H01L21/823487 , H01L27/088 , H01L29/66666 , H01L29/7827 , H01L29/7831
摘要： A vertical transistor particularly suitable for high density integration includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.
摘要翻译：特别适用于高密度集成的垂直晶体管包括通过在沟槽中蚀刻或外延生长形成的半导体柱的相对侧上的潜在的独立栅极结构。栅极结构被绝缘材料包围，绝缘材料可选择性地蚀刻到围绕晶体管的隔离材料。通过选择性地蚀刻对绝缘材料有选择性的隔离材料，对柱的下端（例如，晶体管漏极）进行接触。柱的上端由盖和可选择性蚀刻材料的侧壁覆盖，使得栅极和源极连接开口也可以通过具有良好配准公差的选择性蚀刻制成。在平行于芯片表面的方向上的柱的尺寸由隔离区域和选择性蚀刻之间的距离限定，并且柱的高度由牺牲层的厚度限定。

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