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1. 发明授权

US5466634A Electronic modules with interconnected surface metallization layers and fabrication methods therefore 失效
标题翻译：因此，具有互连表面金属化层的电子模块和制造方法
公开(公告)号：US5466634A
公开(公告)日：1995-11-14
申请号：US359982
申请日：1994-12-20
申请人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , John E. Cronin , Wayne J. Howell , James M. Leas , Robert B. Phillips
发明人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , John E. Cronin , Wayne J. Howell , James M. Leas , Robert B. Phillips
IPC分类号： H01L23/538 , H01L21/98 , H01L25/065 , H01L25/07 , H01L25/18 , H01L21/44
CPC分类号： H01L25/50 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2224/24145 , H01L2224/48091 , H01L2224/49109 , H01L2225/0651 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06596 , H01L2924/30107
摘要： Methods of fabrication for electronic modules having electrically interconnected side and end surface metallization layers and associated electronic modules are set forth. The methods include providing a stack comprising a plurality of stacked IC chips. A side surface thin-film metallization layer is formed on the stack. Next, an end surface thin-film metallization layer is formed the stack such that the side surface and end surface thin-film metallization layers directly electrically interconnect. Alternatively, each IC chip of a stack may include an end surface metallization layer such that separate formation of an end surface metallization layer on an end surface of the stack is unnecessary. The methods also include forming an electronic module by first providing a long stack of IC chips, testing the chips of the stack, and then segmenting the long stack into multiple small stacks of functional IC chips based upon the test results. Specific details of electronic modules, IC chips contained therein, and stacks composed thereof are also set forth.
摘要翻译：阐述了具有电互连的侧表面金属化层和相关的电子模块的电子模块的制造方法。所述方法包括提供包括多个堆叠的IC芯片的堆叠。在堆叠上形成侧面薄膜金属化层。接下来，将端面薄膜金属化层形成为堆叠，使得侧表面和端面薄膜金属化层直接电互连。或者，堆叠的每个IC芯片可以包括端面金属化层，使得不需要在堆叠的端表面上分离形成端面金属化层。所述方法还包括通过首先提供长堆叠的IC芯片，测试堆叠的芯片，然后基于测试结果将长堆叠分成多个小堆功能IC芯片来形成电子模块。还阐述了电子模块，其中包含的IC芯片及其组成的具体细节。

2. 发明授权

US5517057A Electronic modules with interconnected surface metallization layers 失效
标题翻译：具有互连表面金属化层的电子模块
公开(公告)号：US5517057A
公开(公告)日：1996-05-14
申请号：US451356
申请日：1995-05-26
申请人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , John E. Cronin , Wayne J. Howell , James M. Leas , Robert B. Phillips
发明人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , John E. Cronin , Wayne J. Howell , James M. Leas , Robert B. Phillips
IPC分类号： H01L23/538 , H01L21/98 , H01L25/065 , H01L25/07 , H01L25/18 , H01L23/48 , H01L23/522
CPC分类号： H01L25/50 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2224/24145 , H01L2224/48091 , H01L2224/49109 , H01L2225/0651 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06596 , H01L2924/30107
摘要： Methods of fabrication for electronic modules having electrically interconnected side and end surface metallization layers and associated electronic modules are set forth. The methods include providing a stack comprising a plurality of stacked IC chips. A side surface thin-film metallization layer is formed on the stack. Next, an end surface thin-film metallization layer is formed the stack such that the side surface and end surface thin-film metallization layers directly electrically interconnect. Alternatively, each IC chip of a stack may include an end surface metallization layer such that separate formation of an end surface metallization layer on an end surface of the stack is unnecessary. The methods also include forming an electronic module by first providing a long stack of IC chips, testing the chips of the stack, and then segmenting the long stack into multiple small stacks of functional IC chips based upon the test results. Specific details of electronic modules, IC chips contained therein, and stacks composed thereof are also set forth.
摘要翻译：阐述了具有电互连的侧表面金属化层和相关的电子模块的电子模块的制造方法。所述方法包括提供包括多个堆叠的IC芯片的堆叠。在堆叠上形成侧面薄膜金属化层。接下来，将端面薄膜金属化层形成为堆叠，使得侧表面和端面薄膜金属化层直接电互连。或者，堆叠的每个IC芯片可以包括端面金属化层，使得不需要在堆叠的端表面上分离形成端面金属化层。所述方法还包括通过首先提供长堆叠的IC芯片，测试堆叠的芯片，然后基于测试结果将长堆叠分成多个小堆功能IC芯片来形成电子模块。还阐述了电子模块，其中包含的IC芯片及其组成的具体细节。

3. 发明授权

US5567654A Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging 失效
标题翻译：将薄层连接到单片电子模块表面的方法和工件以及相关的模块封装
公开(公告)号：US5567654A
公开(公告)日：1996-10-22
申请号：US313976
申请日：1994-09-28
申请人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , John E. Cronin , Wayne J. Howell , James M. Leas , David J. Perlman
发明人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , John E. Cronin , Wayne J. Howell , James M. Leas , David J. Perlman
IPC分类号： H01L21/98 , H01L23/498 , H01L25/065 , H01L25/18 , H01L21/60
CPC分类号： H01L25/50 , H01L23/49827 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/16145 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/49107 , H01L2224/49109 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06582 , H01L2225/06586 , H01L2225/06589 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01039 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15312 , H01L2924/1532 , H01L2924/16152 , H01L2924/16195 , H01L2924/30107
摘要： A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary support which is used to attach the thin-film layer to the electronic module. The disclosed techniques may also be used for attaching an interposer, which may include active circuity, to an electronic module. Specific details of the fabrication method, resulting multichip packages, and various thin-film structures are set forth.
摘要翻译：一种具有附接到侧表面的单独形成的薄膜层的制造方法和所得到的单片电子模块。该制造方法包括提供由堆叠的集成电路芯片组成的电子模块。在用于将薄膜层附着到电子模块的临时支架上分开形成薄膜层。所公开的技术还可以用于将可包括有源电路的插入件附接到电子模块。阐述了制造方法，所得到的多芯片封装以及各种薄膜结构的具体细节。

4. 发明授权

US5399516A Method of making shadow RAM cell having a shallow trench EEPROM 失效
标题翻译：制造具有浅沟槽EEPROM的阴影RAM单元的方法
公开(公告)号：US5399516A
公开(公告)日：1995-03-21
申请号：US930797
申请日：1992-09-21
申请人： Albert S. Bergendahl , Claude L. Bertin , John E. Cronin , Howard L. Kalter , Donald M. Kenney , Chung H. Lam , Hsing-San Lee
发明人： Albert S. Bergendahl , Claude L. Bertin , John E. Cronin , Howard L. Kalter , Donald M. Kenney , Chung H. Lam , Hsing-San Lee
IPC分类号： H01L27/10 , H01L21/8239 , H01L21/8242 , H01L21/8247 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/308
CPC分类号： H01L29/7882 , H01L27/105 , H01L27/1052 , H01L27/10829 , H01L27/115
摘要： A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the semiconductor substrate running between the DRAM devices such that each DRAM-EEPROM pair shares a common drain diffusion. The EEPROM cells are arranged in the trench such that there are discontinuous laterally disposed floating gate polysilicon electrodes and continuous horizontally disposed program and recall gate polysilicon electrodes. The floating gate is separated from the program and recall gates by a silicon rich nitride. The array of the invention provides high density shadow RAMs. Also disclosed are methods for the fabrication of devices of the invention.
摘要翻译：公开了一种形成在半导体衬底上的半导体器件存储器阵列，其包括设置成阵列的多个场效应晶体管DRAM器件。每个DRAM器件与非易失性EEPROM单元配对，并且EEPROM单元被布置在运行在DRAM器件之间的半导体衬底中的浅沟槽中，使得每个DRAM-EEPROM对共享共同的漏极扩散。 EEPROM单元布置在沟槽中，使得存在不连续的侧向设置的浮栅多晶硅电极和连续的水平布置的程序和调用栅极多晶硅电极。浮动栅极与程序分离，并通过富含硅的氮化物来调用栅极。本发明的阵列提供高密度影子RAM。还公开了用于制造本发明的装置的方法。

5. 发明授权

US5196722A Shadow ram cell having a shallow trench eeprom 失效
标题翻译：阴影柱塞细胞具有浅沟eeprom
公开(公告)号：US5196722A
公开(公告)日：1993-03-23
申请号：US848913
申请日：1992-03-12
申请人： Albert S. Bergendahl , Claude L. Bertin , John E. Cronin , Howard L. Kalter , Donald M. Kenney , Chung H. Lam , Hsing-San Lee
发明人： Albert S. Bergendahl , Claude L. Bertin , John E. Cronin , Howard L. Kalter , Donald M. Kenney , Chung H. Lam , Hsing-San Lee
IPC分类号： H01L27/105 , H01L27/108 , H01L29/788
CPC分类号： H01L27/10829 , H01L27/105 , H01L29/7881
摘要： A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the semiconductor substrate running between the DRAM devices such that each DRAM-EEPROM pair shares a common drain diffusion. The EEPROM cells are arranged in the trench such that there are discontinuous laterally disposed floating gate polysilicon electrodes and continuous horizontally disposed program and recall gate polysilicon electrodes. The floating gate is separated from the program and recall gates by a silicon rich nitride. The array of the invention provides high density shadow RAMs. Also disclosed are methods for the fabrication of devices of the invention.
摘要翻译：公开了一种形成在半导体衬底上的半导体器件存储器阵列，其包括设置成阵列的多个场效应晶体管DRAM器件。每个DRAM器件与非易失性EEPROM单元配对，并且EEPROM单元被布置在运行在DRAM器件之间的半导体衬底中的浅沟槽中，使得每个DRAM-EEPROM对共享共同的漏极扩散。 EEPROM单元布置在沟槽中，使得存在不连续的侧向设置的浮栅多晶硅电极和连续的水平布置的程序和调用栅极多晶硅电极。浮动栅极与程序分离，并通过富含硅的氮化物来调用栅极。本发明的阵列提供高密度影子RAM。还公开了用于制造本发明的装置的方法。

6. 发明授权

US6137129A High performance direct coupled FET memory cell 失效
标题翻译：高性能直接耦合FET存储单元
公开(公告)号：US6137129A
公开(公告)日：2000-10-24
申请号：US2825
申请日：1998-01-05
申请人： Claude L. Bertin , John E. Cronin , Erik L. Hedberg , Jack A. Mandelman
发明人： Claude L. Bertin , John E. Cronin , Erik L. Hedberg , Jack A. Mandelman
IPC分类号： H01L21/8244 , H01L27/11 , H01L27/108 , H01L29/74 , H01L29/76
CPC分类号： H01L27/11 , Y10S257/903
摘要： A pair of directly coupled Field Effect transistors (FETs), a latch of directly coupled FETS, a Static Random Access Memory (SRAM) cell including a latch of directly coupled FETs and the process of forming the directly coupled FET structure, latch and SRAM cell. The vertical FETs, which may be both PFETs, NFETs or one of each, are epi-grown NPN or PNP stacks separated by a gate oxide, SiO.sub.2. Each device's gate is the source or drain of the other device of the pair. The preferred embodiment latch includes two such pairs of directly coupled vertical FETs connected together to form cross coupled invertors. A pass gate layer is bonded to one surface of a layer of preferred embodiment latches to form an array of preferred embodiment SRAM cells. The SRAM cell may include one or two pass gates. The preferred embodiment SRAM process has three major steps. First, preferred embodiment latches are formed in an oxide layer on a silicon wafer. Second, the cell pass gates are formed on a pass gate or Input/Output (I/O) layer. Third, the I/O layer is bonded to and connected to the preferred latch layer.
摘要翻译：一对直接耦合的场效应晶体管（FET），直接耦合FETS的锁存器，包括直接耦合FET的锁存器的静态随机存取存储器（SRAM）单元和形成直接耦合的FET结构的过程，锁存器和SRAM单元。可以是PFET，NFET或者其中之一的垂直FET是由栅极氧化物SiO 2分离的外延生长的NPN或PNP堆叠。每个设备的门是该对的另一个设备的源或漏极。优选实施例锁存器包括两对这样的直接耦合的垂直FET对，连接在一起以形成交叉耦合的反相器。通路栅极层结合到优选实施例锁存器的一个表面上以形成优选实施例SRAM单元的阵列。 SRAM单元可以包括一个或两个传递门。优选实施例SRAM过程具有三个主要步骤。首先，优选实施例的锁存器形成在硅晶片上的氧化物层中。第二，在传输门或输入/输出（I / O）层上形成单元传输门。第三，I / O层被粘合并连接到优选的锁存层。

7. 发明授权

US5567653A Process for aligning etch masks on an integrated circuit surface using electromagnetic energy 失效
标题翻译：使用电磁能量在集成电路表面上对准蚀刻掩模的工艺
公开(公告)号：US5567653A
公开(公告)日：1996-10-22
申请号：US306042
申请日：1994-09-14
申请人： Claude L. Bertin , John E. Cronin , David J. Perlman
发明人： Claude L. Bertin , John E. Cronin , David J. Perlman
IPC分类号： H01L25/00 , H01L21/98 , H01L23/52 , H01L25/065 , H01L21/027 , H01L21/31
CPC分类号： H01L25/50 , H01L25/0657 , H01L2224/13022 , H01L2225/06524 , H01L2225/06551 , H01L2225/06593 , H01L2225/06596 , H01L2924/10253 , Y10S438/928 , Y10S438/975 , Y10S438/977
摘要： Methods for alignment of stacked integrated circuit chips and the resultant three-dimensional semiconductor structures. A thickness control layer is deposited, as needed, on each integrated circuit chip. The thickness of the layer is determined by the thickness of the chip following a grind stage in the fabrication process. Complementary patterns are etched into the thickness control layer of each chip and into adjacent chips. Upon stacking the chips in a three dimensional structure, precise alignment is obtained for interconnect pads which are disposed on the edges of each integrated circuit chip. Dense bus and I/O networks can be thereby supported on a face of the resultant three-dimensional structure.
摘要翻译：用于堆叠集成电路芯片和所得三维半导体结构的对准的方法。根据需要在每个集成电路芯片上沉积厚度控制层。该层的厚度由在制造过程中的研磨阶段之后的芯片的厚度确定。互补图案蚀刻到每个芯片的厚度控制层中并进入相邻的芯片。在三维结构中堆叠芯片时，对于布置在每个集成电路芯片的边缘上的互连焊盘，获得精确的对准。因此，可以在所得到的三维结构的表面上支持密集的总线和I / O网络。

8. 发明授权

US5532519A Cube wireability enhancement with chip-to-chip alignment and thickness control 失效
标题翻译：具有芯片对芯片对齐和厚度控制的立方线可提升性
公开(公告)号：US5532519A
公开(公告)日：1996-07-02
申请号：US375770
申请日：1995-01-20
申请人： Claude L. Bertin , John E. Cronin , David J. Perlman
发明人： Claude L. Bertin , John E. Cronin , David J. Perlman
IPC分类号： H01L25/00 , H01L21/98 , H01L23/52 , H01L25/065 , H01L23/538
CPC分类号： H01L25/50 , H01L25/0657 , H01L2224/13022 , H01L2225/06524 , H01L2225/06551 , H01L2225/06593 , H01L2225/06596 , H01L2924/10253 , Y10S438/928 , Y10S438/975 , Y10S438/977
摘要： Methods for alignment of stacked integrated circuit chips and the resultant three-dimensional semiconductor structures. A thickness control layer is deposited, as needed, on each integrated circuit chip. The thickness of the layer is determined by the thickness of the chip following a grind stage in the fabrication process. Complementary patterns are etched into the thickness control layer of each chip and into adjacent chips. Upon stacking the chips in a three dimensional structure, precise alignment is obtained for interconnect pads which are disposed on the edges of each integrated circuit chip. Dense bus and I/O networks can be thereby supported on a face of the resultant three-dimensional structure.
摘要翻译：用于堆叠集成电路芯片和所得三维半导体结构的对准的方法。根据需要在每个集成电路芯片上沉积厚度控制层。该层的厚度由在制造过程中的研磨阶段之后的芯片的厚度确定。互补图案蚀刻到每个芯片的厚度控制层中并进入相邻的芯片。在三维结构中堆叠芯片时，对于布置在每个集成电路芯片的边缘上的互连焊盘，获得精确的对准。因此，可以在所得到的三维结构的表面上支持密集的总线和I / O网络。

9. 发明授权

US06426530B1 High performance direct coupled FET memory cell 失效
标题翻译：高性能直接耦合FET存储单元
公开(公告)号：US06426530B1
公开(公告)日：2002-07-30
申请号：US09568663
申请日：2000-05-10
申请人： Claude L. Bertin , John E. Cronin , Erik L. Hedberg , Jack A. Mandelman
发明人： Claude L. Bertin , John E. Cronin , Erik L. Hedberg , Jack A. Mandelman
IPC分类号： H01L2976
CPC分类号： H01L27/11 , Y10S257/903
摘要： A pair of directly coupled Field Effect transistors (FETs), a latch of directly coupled FETs, a Static Random Access Memory (SRAM) cell including a latch of directly coupled FETs and the process of forming the directly coupled FET structure, latch and SRAM cell. The vertical FETs, which may be both PFETs, NFETs or one of each, are epi-grown NPN or PNP stacks separated by a gate oxide, SiO2. Each device's gate is the source or drain of the other device of the pair. The preferred embodiment latch includes two such pairs of directly coupled vertical FETs connected together to form cross coupled invertors. A pass gate layer is bonded to one surface of a layer of preferred embodiment latches to form an array of preferred embodiment SRAM cells. The SRAM cell may include one or two pass gates. The preferred embodiment SRAM process has three major steps. First, preferred embodiment latches are formed in an oxide layer on a silicon wafer. Second, the cell pass gates are formed on a pass gate or Input/Output (I/O) layer. Third, the I/O layer is bonded to and connected to the preferred latch layer.
摘要翻译：一对直接耦合的场效应晶体管（FET），直接耦合的FET的锁存器，包括直接耦合的FET的锁存器的静态随机存取存储器（SRAM）单元和形成直接耦合的FET结构的过程，锁存器和SRAM单元。可以是PFET，NFET或者其中之一的垂直FET是由栅极氧化物SiO 2分离的外延生长的NPN或PNP堆叠。每个设备的门是该对的另一个设备的源或漏极。优选实施例锁存器包括两对这样的直接耦合的垂直FET对，连接在一起以形成交叉耦合的反相器。通路栅极层结合到优选实施例锁存器的一个表面上以形成优选实施例SRAM单元的阵列。 SRAM单元可以包括一个或两个传递门。优选实施例SRAM过程具有三个主要步骤。首先，优选实施例的锁存器形成在硅晶片上的氧化物层中。第二，在传输门或输入/输出（I / O）层上形成单元传输门。第三，I / O层被粘合并连接到优选的锁存层。

10. 发明授权

US06213376B1 Stacked chip process carrier 失效
标题翻译：堆叠芯片加工载体
公开(公告)号：US06213376B1
公开(公告)日：2001-04-10
申请号：US09098828
申请日：1998-06-17
申请人： George C. Correia , John E. Cronin , Edmund J. Sprogis
发明人： George C. Correia , John E. Cronin , Edmund J. Sprogis
IPC分类号： B23K3704
CPC分类号： H01L21/6835 , B23K37/0408 , B23K2101/40 , H01L25/50 , H01L2221/68313 , H01L2224/05568 , H01L2224/05573 , H01L2224/056 , H01L2224/16 , H01L2924/30105 , Y10T29/53978 , H01L2924/00014
摘要： An apparatus used for holding a first semiconductor device in proper alignment to a second semiconductor device, whose size is different from the first device, while performing a C4 bond between the two devices. The apparatus for holding the two devices in proper alignment consists of a holding fixture, which includes upper and lower pocket receptacles for receiving the semiconductor devices. The semiconductor devices are placed into the respective upper and lower slots aligned to two or more edges of the holding fixture.
摘要翻译：一种用于在与两个装置之间执行C4键的同时保持尺寸与第一装置不同的第二半导体装置正确对准的装置。用于将两个装置保持正确对准的装置包括保持夹具，其包括用于接收半导体装置的上部和下部口袋容器。将半导体器件放置在与保持夹具的两个或更多个边缘对准的相应的上部和下部狭缝中。

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