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1. 发明授权

US06590258B2 SIO stacked DRAM logic 失效
标题翻译： Soi堆叠DRAM逻辑
公开(公告)号：US06590258B2
公开(公告)日：2003-07-08
申请号：US09998318
申请日：2001-12-03
申请人： Ramachandra Divakauni , Mark C. Hakey , William H-L. Ma , Jack A. Mandclman , William R. Tonti
发明人： Ramachandra Divakauni , Mark C. Hakey , William H-L. Ma , Jack A. Mandclman , William R. Tonti
IPC分类号： H01L2701
CPC分类号： H01L27/10867 , H01L22/32 , H01L23/481 , H01L23/535 , H01L27/10832 , H01L27/1203 , H01L2924/0002 , Y10S977/712 , Y10S977/721 , Y10S977/779 , Y10S977/90 , Y10S977/94 , H01L2924/00
摘要： A composite, layered, integrated circuit formed by bonding of insulator layers on wafers provides for combination of otherwise incompatible technologies such as trench capacitor DRAM arrays and high performance, low power, low voltage silicon on insulator (SOI) switching transistors and short signal propagation paths between devices formed on respective wafer layers of a chip. In preferred embodiments, an SOI wafer is formed by hydrophilic bonding of a wafer over an integrated circuit device and then cleaving a layer of the second wafer away using implanted hydrogen and low temperature heat treatment. Further wafers of various structures and compositions may be bonded thereover and connections between circuit elements and connection pads in respective wafers made using short vias that provide fast signal propagation as well as providing more numerous connections than can be provided on chip edges.
摘要翻译：通过在晶片上粘合绝缘体层而形成的复合层状集成电路提供了诸如沟槽电容器DRAM阵列和高性能，低功率，低电压绝缘体上硅（SOI）开关晶体管和短信号传播路径之类的不相容技术的组合在形成在芯片的各个晶片层上的器件之间。在优选实施例中，通过在集成电路器件上的晶片亲水键合然后使用注入的氢和低温热处理将第二晶片的层切割掉，形成SOI晶片。各种结构和组合物的其它晶片可以在其上结合，并且使用提供快速信号传播的短通孔制成的各个晶片中的电路元件和连接焊盘之间的连接以及提供比在芯片边缘上提供更多的连接。

2. 发明授权

US06462752B1 Automatic scrolling function for editors and browsers 失效
标题翻译：编辑器和浏览器的自动滚动功能
公开(公告)号：US06462752B1
公开(公告)日：2002-10-08
申请号：US09441028
申请日：1999-11-16
申请人： William H. L. Ma , Wayne M. Delia , William A. Ma
发明人： William H. L. Ma , Wayne M. Delia , William A. Ma
IPC分类号： G09G500
CPC分类号： G06F3/0485
摘要： An automatic scrolling and paging function is provided for use with an object/text editor or a browser, in which either scrolling or paging is automatically performed at a variable speed. A delay time is set as a parameter for control of the display; automatic display of the document is commenced by displaying a first portion of the document; a subsequent portion of the document is displayed after expiration of the delay time; and the display of portions of the document is iterated until the entire document has been displayed. The delay time is reset during the automatic display, thereby changing the rate at which successive portions of the document are displayed. The delay time may depend upon the location of the portion of the document; accordingly, successive portions of the document may be automatically displayed at a varying rate.
摘要翻译：提供了一种与对象/文本编辑器或浏览器一起使用的自动滚动和寻呼功能，其中以可变速度自动执行滚动或寻呼。将延迟时间设置为用于显示控制的参数; 通过显示文档的第一部分来开始文档的自动显示; 在延迟时间到期后显示文档的后续部分; 并重复显示文档的部分直到整个文档被显示。延迟时间在自动显示期间复位，从而改变显示文档的连续部分的速率。延迟时间可能取决于文档部分的位置; 因此，可以以变化的速率自动显示文档的连续部分。

3. 发明授权

US06444402B1 Method of making differently sized vias and lines on the same lithography level 失效
标题翻译：在相同光刻级别上制作不同尺寸的通孔和线的方法
公开(公告)号：US06444402B1
公开(公告)日：2002-09-03
申请号：US09532187
申请日：2000-03-21
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H-L. Ma
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H-L. Ma
IPC分类号： G03C500
CPC分类号： H01L21/31144 , G03F7/0035 , G03F7/40 , H01L21/0332 , H01L21/0337 , H01L21/76816
摘要： Features of two or more distinct sizes designed to optimize performance of an integrated circuit device are formed by transferring a pattern from a resist patterned with features of a single minimum feature size for which a resist exposure tool is optimized to a layer of preferably soluble material such as germanium oxide. Portions of this pattern are then enlarged using a block-out mask and the resulting pattern transferred to a further underlying layer preferably using an anisotropic reactive ion etch. The soluble material can then be removed leaving a robust mask with differing feature sizes for further processing. Preferably, Damascene conductive lines and vias are formed by providing an insulator as the further underlying material and filling the openings with metal or other conductive material.
摘要翻译：设计用于优化集成电路器件性能的两个或多个不同尺寸的特征通过将图案从具有抗蚀剂曝光工具优化的单个最小特征尺寸的特征的抗蚀剂转移到优选可溶性材料层而形成，作为氧化锗。然后使用阻挡掩模将该图案的部分放大，并且将所得到的图案优选地使用各向异性反应离子蚀刻转移到另一下层。然后可以去除可溶性材料，留下具有不同特征尺寸的坚固的掩模，用于进一步处理。优选地，通过提供绝缘体作为其他下层材料并用金属或其它导电材料填充开口来形成镶嵌导电线和通孔。

4. 发明授权

US07176089B2 Vertical dual gate field effect transistor 失效
标题翻译：垂直双栅场效应晶体管
公开(公告)号：US07176089B2
公开(公告)日：2007-02-13
申请号：US10853177
申请日：2004-05-26
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , James M. Leas , William H-L Ma , Paul A. Rabidoux
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , James M. Leas , William H-L Ma , Paul A. Rabidoux
IPC分类号： H01L21/336
CPC分类号： H01L29/78642 , H01L21/2255 , H01L21/76897 , H01L21/823487 , H01L27/088 , H01L29/66666 , H01L29/7827 , H01L29/7831
摘要： A method of manufacturing provides a vertical transistor particularly suitable for high density integration and which includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.
摘要翻译：一种制造方法提供特别适用于高密度积分的垂直晶体管，其包括通过在沟槽中蚀刻或外延生长而形成的半导体柱的相对侧上的潜在独立栅极结构。栅极结构被绝缘材料包围，绝缘材料可选择性地蚀刻到围绕晶体管的隔离材料。通过选择性地蚀刻对绝缘材料有选择性的隔离材料，对柱的下端（例如，晶体管漏极）进行接触。柱的上端由盖和可选择性蚀刻材料的侧壁覆盖，使得栅极和源极连接开口也可以通过具有良好配准公差的选择性蚀刻制成。在平行于芯片表面的方向上的柱的尺寸由隔离区域和选择性蚀刻之间的距离限定，并且柱的高度由牺牲层的厚度限定。

5. 发明授权

US06998332B2 Method of independent P and N gate length control of FET device made by sidewall image transfer technique 失效
标题翻译：由侧壁图像传输技术制造的FET器件的独立P和N栅极长度控制方法
公开(公告)号：US06998332B2
公开(公告)日：2006-02-14
申请号：US10754073
申请日：2004-01-08
申请人： Toshiharu Furukawa , Steven J. Holmes , William H-L Ma
发明人： Toshiharu Furukawa , Steven J. Holmes , William H-L Ma
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/2815
摘要： Disclosed is a method that forms a conductive layer on a substrate and patterns sacrificial structures above the conductive layer. Next, the invention forms sidewall spacers adjacent the sacrificial structures using a spacer material capable of undergoing dimensional change, after which the invention removes the sacrificial structures in processing that leaves the sidewall spacers in place. The invention then protects selected ones of the sidewall spacers using a sacrificial mask and leaves the other ones of the sidewall spacers unprotected. This allows the invention to selectively expose the unprotected sidewall spacers to processing that changes the size of the unprotected sidewall spacers. This causes the unprotected sidewall spacers have a different size than protected sidewall spacers. Then, the invention removes the sacrificial mask and patterns the conductive layer using the sidewall spacers as a gate conductor mask to create differently sized gate conductors on the substrate. Following this, the invention removes the sidewall spacers and forms the source, drain, and channel regions adjacent the gate conductors.
摘要翻译：公开了一种在基板上形成导电层并在导电层上方形成牺牲结构的方法。接下来，本发明使用能够经历尺寸变化的间隔物材料形成邻近牺牲结构的侧壁间隔，此后本发明在将侧壁间隔物留在适当位置的情况下去除牺牲结构。然后，本发明使用牺牲掩模保护所选择的侧壁间隔物，并且使侧壁间隔物中的其它侧壁隔离件不被保护。这允许本发明选择性地将未受保护的侧壁间隔物暴露于改变未受保护的侧壁间隔物的尺寸的处理。这导致未受保护的侧壁间隔件具有与受保护的侧壁间隔物不同的尺寸。然后，本发明移除牺牲掩模，并且使用侧壁间隔物作为栅极导体掩模来图案化导电层，以在衬底上产生不同尺寸的栅极导体。接下来，本发明移除侧壁间隔物并形成与栅极导体相邻的源极，漏极和沟道区域。

6. 发明授权

US06731315B1 Method for selecting display parameters of a magnifiable cursor 失效
标题翻译：选择可放大光标的显示参数的方法
公开(公告)号：US06731315B1
公开(公告)日：2004-05-04
申请号：US09450531
申请日：1999-11-30
申请人： William A. Ma , Wayne M. Delia , William H-L Ma
发明人： William A. Ma , Wayne M. Delia , William H-L Ma
IPC分类号： G06F300
CPC分类号： G06F3/0481 , G06F2203/04805
摘要： A computer display system which displays an image and a magnified portion of the image. The magnified portion of the image is selected un,der control of a pointing device connected to the computer. A method is described for changing the characteristics of the magnified portion. A configuration utility which creates the magnified portion of the display includes a menu of display properties for the magnified portion. The properties are selected from the display menu, and each refresh of the area within the magnified portion of the image is refreshed with the selected properties. In a text/browser application, the background color, text color, text style and size may be selected differently than the remaining portion of the image displayed on the computer display.
摘要翻译：一种显示图像和图像的放大部分的计算机显示系统。图像的放大部分被选择为连接到计算机的指示设备的控制。描述了用于改变放大部分的特性的方法。创建显示器的放大部分的配置实用程序包括用于放大部分的显示属性的菜单。从显示菜单中选择属性，并且用所选择的属性刷新图像的放大部分内的区域的每个刷新。在文本/浏览器应用程序中，背景颜色，文本颜色，文本样式和大小可能与计算机显示屏上显示的图像的剩余部分不同。

7. 发明授权

US06506653B1 Method using disposable and permanent films for diffusion and implant doping 失效
标题翻译：使用一次性和永久性膜进行扩散和注入掺杂的方法
公开(公告)号：US06506653B1
公开(公告)日：2003-01-14
申请号：US09524677
申请日：2000-03-13
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H-L Ma , Patricia M. Marmillion , Donald W. Rakowski
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H-L Ma , Patricia M. Marmillion , Donald W. Rakowski
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/2254 , H01L21/2255 , H01L21/823814 , H01L21/823842 , H01L29/665
摘要： Methods are provided that use disposable and permanent films to dope underlying layers through diffusion. Additionally, methods are provided that use disposable films during implantation doping and that provide a surface from which to dope underlying materials. Some of these disposable films can be created from a traditionally non-disposable film and made disposable. In this manner, solvents may be used that do not etch underlying layers of silicon-based materials. Preferably, deep implantation is performed to form source/drain regions, then an anneal step is performed to activate the dopants. A conformal layer is deposited and implanted with dopants. One or more anneal steps are performed to create very shallow extensions in the source/drain regions.
摘要翻译：提供了使用一次性和永久性膜通过扩散来掺杂下层的方法。此外，提供了在植入掺杂期间使用一次性膜的方法，并且提供了用于涂覆下层材料的表面。这些一次性膜中的一些可以由传统的非一次性膜制成并制成一次性的。以这种方式，可以使用不蚀刻硅基材料的下层的溶剂。优选地，进行深度注入以形成源极/漏极区域，然后执行退火步骤以激活掺杂剂。沉积保形层并用掺杂剂注入。执行一个或多个退火步骤以在源极/漏极区域中产生非常浅的延伸。

8. 发明授权

US06867143B1 Method for etching a semiconductor substrate using germanium hard mask 失效
标题翻译：使用锗硬掩模蚀刻半导体衬底的方法
公开(公告)号：US06867143B1
公开(公告)日：2005-03-15
申请号：US09599783
申请日：2000-06-22
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H-L. Ma
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H-L. Ma
IPC分类号： C23F4/00 , C23G1/00 , H01L21/302 , H01L21/308 , H01L21/3213
CPC分类号： H01L21/3081 , C23F4/00 , C23G1/00 , H01L21/3086 , H01L21/32134
摘要： An etching process using germanium hard mask (25) includes forming a dielectric layer (15) over a major surface (11) of a semiconductor substrate (10) and depositing a metallic germanium layer (22) over the dielectric layer (15). The metallic germanium layer (22) is patterned through a photo resist (24) to form the germanium hard mask (25). The dielectric layer (15) is selectively etched through the germanium hard mask (25) to form a dielectric hard mask (35), through which the semiconductor substrate (10) is subsequently etched. After forming the dielectric hard mask (35), the germanium hard mask (25) is stripped away by oxidizing the metallic germanium hard mask (25) to transform it into a layer (27) of germanium oxide and rinsing the semiconductor substrate (10) in water to remove the germanium oxide layer (27). Preferably, the germanium hard mask (25) is removed before etching the semiconductor substrate (10).
摘要翻译：使用锗硬掩模（25）的蚀刻工艺包括在半导体衬底（10）的主表面（11）上形成电介质层（15），并在电介质层（15）上沉积金属锗层（22）。通过光致抗蚀剂（24）将金属锗层（22）图案化以形成锗硬掩模（25）。通过锗硬掩模（25）选择性地蚀刻电介质层（15）以形成电介质硬掩模（35），随后蚀刻半导体衬底（10）。在形成电介质硬掩模（35）之后，通过氧化金属锗硬掩模（25）将锗硬掩模（25）剥离，将其转化成氧化锗层（27）并冲洗半导体衬底（10），在水中以除去氧化锗层（27）。优选地，在蚀刻半导体衬底（10）之前去除锗硬掩模（25）。

9. 发明授权

US06924200B2 Methods using disposable and permanent films for diffusion and implantation doping 失效
标题翻译：使用一次性和永久性膜进行扩散和注入掺杂的方法
公开(公告)号：US06924200B2
公开(公告)日：2005-08-02
申请号：US10222035
申请日：2002-08-16
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H-L Ma , Patricia M. Marmillion , Donald W. Rakowski
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H-L Ma , Patricia M. Marmillion , Donald W. Rakowski
IPC分类号： H01L21/225 , H01L21/336 , H01L21/8238 , H01L21/302 , H01L21/21
CPC分类号： H01L29/6659 , H01L21/2254 , H01L21/2255 , H01L21/823814 , H01L21/823842 , H01L29/665
摘要： Methods are provided that use disposable and permanent films to dope underlying layers through diffusion. Additionally, methods are provided that use disposable films during implantation doping and that provide a surface from which to dope underlying materials. Some of these disposable films can be created from a traditionally non-disposable film and made disposable. In this manner, solvents may be used that do not etch underlying layers of silicon-based materials. Preferably, deep implantation is performed to form source/drain regions, then an anneal step is performed to activate the dopants. A conformal layer is deposited and implanted with dopants. One or more anneal steps are performed to create very shallow extensions in the source/drain regions.
摘要翻译：提供了使用一次性和永久性膜通过扩散来掺杂下层的方法。此外，提供了在植入掺杂期间使用一次性膜的方法，并且提供了用于涂覆下层材料的表面。这些一次性膜中的一些可以由传统的非一次性膜制成并制成一次性的。以这种方式，可以使用不蚀刻硅基材料的下层的溶剂。优选地，进行深度注入以形成源极/漏极区域，然后执行退火步骤以激活掺杂剂。沉积保形层并用掺杂剂注入。执行一个或多个退火步骤以在源极/漏极区域中产生非常浅的延伸。

10. 发明授权

US06798017B2 Vertical dual gate field effect transistor 有权
标题翻译：垂直双栅场效应晶体管
公开(公告)号：US06798017B2
公开(公告)日：2004-09-28
申请号：US09944665
申请日：2001-08-31
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , James M. Leas , William H-L Ma , Paul A. Rabidoux
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , James M. Leas , William H-L Ma , Paul A. Rabidoux
IPC分类号： H01L2976
CPC分类号： H01L29/78642 , H01L21/2255 , H01L21/76897 , H01L21/823487 , H01L27/088 , H01L29/66666 , H01L29/7827 , H01L29/7831
摘要： A vertical transistor particularly suitable for high density integration includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.
摘要翻译：特别适用于高密度集成的垂直晶体管包括通过在沟槽中蚀刻或外延生长形成的半导体柱的相对侧上的潜在的独立栅极结构。栅极结构被绝缘材料包围，绝缘材料可选择性地蚀刻到围绕晶体管的隔离材料。通过选择性地蚀刻对绝缘材料有选择性的隔离材料，对柱的下端（例如，晶体管漏极）进行接触。柱的上端由盖和可选择性蚀刻材料的侧壁覆盖，使得栅极和源极连接开口也可以通过具有良好配准公差的选择性蚀刻制成。在平行于芯片表面的方向上的柱的尺寸由隔离区域和选择性蚀刻之间的距离限定，并且柱的高度由牺牲层的厚度限定。

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