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1. 发明授权

US07729153B2 276-pin buffered memory module with enhanced fault tolerance 失效
标题翻译： 276引脚缓冲存储器模块，具有增强的容错能力
公开(公告)号：US07729153B2
公开(公告)日：2010-06-01
申请号：US12060998
申请日：2008-04-02
申请人： Daniel M. Dreps , Frank D. Ferraiolo , Kevin C. Gower , Mark W. Kellogg , Roger A. Rippens
发明人： Daniel M. Dreps , Frank D. Ferraiolo , Kevin C. Gower , Mark W. Kellogg , Roger A. Rippens
IPC分类号： G11C5/02 , G11C5/06
CPC分类号： G11C5/04
摘要： A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.
摘要翻译：双列直插式存储器模块（DIMM）包括具有大约151.2至大约151.5毫米的长度的卡，连接到卡的多个单独的本地存储器件以及连接到卡的缓冲器装置，缓冲器装置被配置为将打包内存界面。该卡片包括至少276个配置在其上的针脚。

2. 发明授权

US07403409B2 276-pin buffered memory module with enhanced fault tolerance 有权
标题翻译： 276引脚缓冲存储器模块，具有增强的容错能力
公开(公告)号：US07403409B2
公开(公告)日：2008-07-22
申请号：US11735640
申请日：2007-04-16
申请人： Daniel M. Dreps , Frank D. Ferraiolo , Kevin C. Gower , Mark W. Kellogg , Roger A. Rippens
发明人： Daniel M. Dreps , Frank D. Ferraiolo , Kevin C. Gower , Mark W. Kellogg , Roger A. Rippens
IPC分类号： G11C5/06 , G11C5/02
CPC分类号： G11C5/04
摘要： A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.
摘要翻译：双列直插式存储器模块（DIMM）包括具有大约151.2至大约151.5毫米的长度的卡，连接到卡的多个单独的本地存储器件以及连接到卡的缓冲器装置，缓冲器装置被配置为将打包内存界面。该卡片包括至少276个配置在其上的针脚。

3. 发明授权

US07394268B2 Carrier for test, burn-in, and first level packaging 失效
标题翻译：用于测试，老化和一级包装的载体
公开(公告)号：US07394268B2
公开(公告)日：2008-07-01
申请号：US11531140
申请日：2006-09-12
申请人： Claude L. Bertin , Wayne F. Ellis , Mark W. Kellogg , William R. Tonti , Jerzy M. Zalesinski , James M. Leas , Wayne J. Howell
发明人： Claude L. Bertin , Wayne F. Ellis , Mark W. Kellogg , William R. Tonti , Jerzy M. Zalesinski , James M. Leas , Wayne J. Howell
IPC分类号： G01R31/02
CPC分类号： G01R31/2867 , G11C5/04 , G11C29/06 , G11C29/1201 , G11C29/48 , G11C29/56016 , G11C29/785 , G11C2029/2602 , G11C2029/5602 , H01L22/22 , H01L22/32 , H01L2924/0002 , H01L2924/00
摘要： A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier.
摘要翻译：在载体上提供多个半导体器件用于测试或烧录。然后将载体切割以提供单个芯片上载波部件或多芯片载波部件。载体用作每个芯片的第一级封装。因此，载体用于测试和烧录和包装的双重目的。可以在每个芯片或载体上提供诸如内置自检引擎的引线减少机构，并且连接到载体的触点用于测试和老化步骤。切割后的最终包装包括至少一个已知的良好的模具，并且可以包括载体上的芯片阵列，例如SIMM或DIMM。最终的包装也可以是一堆芯片，每个芯片都安装在单独的载体上。堆叠的载体通过沿着堆叠的侧面安装的基板彼此连接，该基板沿着每个载体的边缘电连接到焊盘一排。

4. 发明授权

US07389375B2 System, method and storage medium for a multi-mode memory buffer device 失效
标题翻译：用于多模式存储器缓冲器的系统，方法和存储介质
公开(公告)号：US07389375B2
公开(公告)日：2008-06-17
申请号：US10903366
申请日：2004-07-30
申请人： Kevin C. Gower , Mark W. Kellogg
发明人： Kevin C. Gower , Mark W. Kellogg
IPC分类号： G06F13/36
CPC分类号： G06F13/4243 , G06F13/4256 , G11C5/04
摘要： A multi-mode memory buffer device for use in various memory subsystem structures. The buffer device includes a packetized multi-transfer interface which is redriven to permit connection between a first memory assembly and cascaded memory assemblies. The buffer device also includes a memory interface adapted to connect to either a second memory assembly or directly to memory devices.
摘要翻译：一种用于各种存储器子系统结构的多模式存储器缓冲器件。缓冲装置包括打包的多传输接口，其被重新驱动以允许第一存储器组件和级联存储器组件之间的连接。缓冲装置还包括适于连接到第二存储器组件或直接连接到存储器件的存储器接口。

5. 发明申请

US20080133797A1 SYSTEM, METHOD AND STORAGE MEDIUM FOR A MULTI-MODE MEMORY BUFFER DEVICE 有权
标题翻译：用于多模式存储器缓冲器器件的系统，方法和存储介质
公开(公告)号：US20080133797A1
公开(公告)日：2008-06-05
申请号：US12029641
申请日：2008-02-12
申请人： Kevin C. Gower , Mark W. Kellogg
发明人： Kevin C. Gower , Mark W. Kellogg
IPC分类号： G06F13/16
CPC分类号： G06F13/4243 , G06F13/4256 , G11C5/04
摘要： A multi-mode memory buffer device for use in various memory subsystem structures. The buffer device includes a packetized multi-transfer interface which is redriven to permit connection between a first memory assembly and cascaded memory assemblies. The buffer device also includes a memory interface adapted to connect to either a second memory assembly or directly to memory devices.
摘要翻译：一种用于各种存储器子系统结构的多模式存储器缓冲器件。缓冲装置包括打包的多传输接口，其被重新驱动以允许第一存储器组件和级联存储器组件之间的连接。缓冲装置还包括适于连接到第二存储器组件或直接连接到存储器件的存储器接口。

6. 发明授权

US07296129B2 System, method and storage medium for providing a serialized memory interface with a bus repeater 失效
标题翻译：用于向总线中继器提供串行存储器接口的系统，方法和存储介质
公开(公告)号：US07296129B2
公开(公告)日：2007-11-13
申请号：US10903178
申请日：2004-07-30
申请人： Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
发明人： Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
IPC分类号： G06F12/00 , G06F13/00 , G11C5/06
CPC分类号： G06F13/4022
摘要： A packetized cascade memory system including a plurality of memory assemblies, a memory bus including multiple segments, a bus repeater module and a segment level sparing module. The bus repeater module is in communication with two or more of the memory assemblies via the memory bus. The segment level sparing module provides segment level sparing for the communication bus upon segment failure.
摘要翻译：包括多个存储器组件的分组级联存储器系统，包括多个段的存储器总线，总线中继器模块和段级备用模块。总线中继器模块经由存储器总线与两个或多个存储器组件通信。段级保护模块在段故障时为通信总线提供段级备用。

7. 发明授权

US07277988B2 System, method and storage medium for providing data caching and data compression in a memory subsystem 失效
标题翻译：用于在存储器子系统中提供数据缓存和数据压缩的系统，方法和存储介质
公开(公告)号：US07277988B2
公开(公告)日：2007-10-02
申请号：US10977846
申请日：2004-10-29
申请人： Kevin C. Gower , Mark W. Kellogg , Warren E. Maule , Thomas B. Smith, III , Robert B. Tremaine
发明人： Kevin C. Gower , Mark W. Kellogg , Warren E. Maule , Thomas B. Smith, III , Robert B. Tremaine
IPC分类号： G06F12/00
CPC分类号： G06F13/1684 , G06F12/0802 , G06F2212/401
摘要： A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.
摘要翻译：包括存储器控制器，一个或多个存储器模块，上游存储器总线和下游存储器总线的级联互连系统。一个或多个存储器模块包括具有高速缓存数据的第一存储器模块。存储器模块和存储器控制器通过分组化的多传输接口经由下游存储器总线和上游存储器总线互连。第一存储器模块和存储器控制器经由上游存储器总线和下游存储器总线直接通信。

8. 发明授权

US06467053B1 Captured synchronous DRAM fails in a working environment 有权
标题翻译：捕获的同步DRAM在工作环境中失败
公开(公告)号：US06467053B1
公开(公告)日：2002-10-15
申请号：US09340804
申请日：1999-06-28
申请人： Brian J. Connolly , Steven A. Grundon , Bruce G. Hazelzet , Mark W. Kellogg , James R. Mallabar
发明人： Brian J. Connolly , Steven A. Grundon , Bruce G. Hazelzet , Mark W. Kellogg , James R. Mallabar
IPC分类号： G06F11277
CPC分类号： G11C29/56 , G11C29/56012 , G11C2029/5602
摘要： A Synchronous DRAM memory test assembly that converts a normal PC or Workstation with a synchronous bus into a memory tester. The test assembly may be split into two segments: a diagnostic card and an adapter card to limit mechanical load on the system socket as well as permit varying form factors. This test assembly architecture supports memory bus speeds of 66 MHz and above, and provides easy access for a logic analyzer. The test assembly supports Registered and Unbuffered Synchronous DRAM products. The test assembly permits good and questionable synchronous modules to be compared using an external logic analyzer. It permits resolution of in-system fails that occur uniquely in system environments and may be otherwise difficult or impossible to replicate. The test assembly re-drives the system clocks with a phase lock loop (PLL) buffer to a memory module socket on the test assembly to permit timing adjustments to minimize the degradation to the system's memory bus timings due to the additional wire length and loading. The test assembly is programmable to adjust to varying bus timings such as: CAS (column address strobe) Latencies and Burst Length variations. It is designed with Field Programmable Gate Arrays (FPGAs) to allow for changes internally without modifying the test assembly.
摘要翻译：同步DRAM存储器测试组件，其将具有同步总线的普通PC或工作站转换为存储器测试器。测试组件可以分为两个部分：诊断卡和适配卡，以限制系统插座上的机械负载以及允许变化的外形尺寸。该测试组件架构支持66 MHz及以上的内存总线速度，并为逻辑分析仪提供方便的访问。测试组件支持注册和非缓冲同步DRAM产品。测试组件允许使用外部逻辑分析仪比较好的和有问题的同步模块。它允许解决在系统环境中唯一发生的系统内故障，并且可能难以或不可能复制。测试组件使用锁相环（PLL）缓冲区将系统时钟重新驱动到测试组件上的存储器模块插槽，以允许定时调整，以最大限度地减少系统的存储器总线时序由于额外的电线长度和负载而的劣化。测试组件可编程为适应变化的总线时序，例如：CAS（列地址选通）延迟和突发长度变化。它设计有现场可编程门阵列（FPGA），可在内部进行更改，无需修改测试组件。

9. 发明授权

US5513135A Synchronous memory packaged in single/dual in-line memory module and method of fabrication 失效
标题翻译：封装在单/双列直插式存储器模块中的同步存储器和制造方法
公开(公告)号：US5513135A
公开(公告)日：1996-04-30
申请号：US349154
申请日：1994-12-02
申请人： Timothy J. Dell , Lina S. Farah , George C. Feng , Mark W. Kellogg
发明人： Timothy J. Dell , Lina S. Farah , George C. Feng , Mark W. Kellogg
IPC分类号： G11C5/00 , G11C5/06
CPC分类号： G11C5/06 , G11C5/04
摘要： Multiple synchronous dynamic random access memories (SDRAMs) are packaged in a single or a dual in-line memory module to have similar physical and architectural characteristics of dynamic random access memories (DRAMs) packaged in single/dual in-line memory modules. A 168 pin SDRAM DIMM family is presented which requires no modification of existing connector, planar or memory controller components. The 168 pin SDRAM DIMM family includes 64 bit non-parity, 72 bit parity, 72 bit ECC and 80 bit ECC memory organizations. Special placement and wiring of decoupling capacitors about the SDRAMs and the buffer chips contained within the module are also presented to reduce simultaneous switching noises during read and write operations. A special wiring scheme for the decoupling capacitors is employed to reduce wiring inductance.
摘要翻译：多个同步动态随机存取存储器（SDRAM）被封装在单个或双列直插存储器模块中，以具有封装在单/双列直插式存储器模块中的动态随机存取存储器（DRAM）的类似物理和架构特性。提供了一个168针SDRAM DIMM系列，不需要修改现有的连接器，平面或内存控制器组件。 168引脚SDRAM DIMM系列包括64位非奇偶校验，72位奇偶校验，72位ECC和80位ECC内存组织。还提供了关于SDRAM和包含在模块内的缓冲器芯片的去耦电容器的特殊放置和布线，以减少读写操作期间的同时开关噪声。采用去耦电容器的特殊布线方案来减少布线电感。

10. 发明授权

US5452429A Error correction code on add-on cards for writing portions of data words 失效
标题翻译：用于写入数据字部分的附加卡上的错误纠正码
公开(公告)号：US5452429A
公开(公告)日：1995-09-19
申请号：US154191
申请日：1993-11-17
申请人： Daniel P. Fuoco , Christopher M. Herring , Mark W. Kellogg , Jorge E. Lenta
发明人： Daniel P. Fuoco , Christopher M. Herring , Mark W. Kellogg , Jorge E. Lenta
IPC分类号： G06F12/16 , G06F11/10
CPC分类号： G06F11/1056 , G06F11/1052
摘要： The present invention provides a computer system and method of using the same. Add-on memory cards for the system are provided which cards have error correction code logic on the card, and logic to do partial writes of data words. The system has a central processing unit (CPU), a BUS interconnecting the CPU and the add-on memory cards. The CPU or associated components are configured to write data and read data from the add-on memory as several data bytes constituting data words. The system is further configured either within the CPU or as a separate function to generate parity bits associated with each of the bytes of data the CPU writes to the add-on memory and to read parity bits associated with data the CPU reads from the add-on memory and regenerate new parity bits and compare the newly generated parity bits with the original parity bits to detect data errors on data read from the add-on memory. The system itself does not contain error correction code (ECC). The add-on memory has ECC logic to identify any byte having a single bit error in the data bytes or the parity bits written by the CPU to the add-on memory and to correct all single bit errors in data read from the add-on memory to the CPU. The error correcting code includes logic to generate parity bits in the data bytes written by the CPU to the add-on memory and logic to compare the parity bits written by the CPU with those generated by the error correcting code logic.
摘要翻译：本发明提供一种计算机系统及其使用方法。提供系统的附加存储卡，哪些卡在卡上具有纠错码逻辑，以及进行数据字的部分写入的逻辑。该系统具有一个中央处理单元（CPU），一个连接CPU和附加存储卡的总线。 CPU或相关组件被配置为写入数据并从附加存储器读取数据作为构成数据字的几个数据字节。该系统进一步配置在CPU内或作为单独功能，以产生与CPU写入附加存储器的每个数据字节相关联的奇偶校验位，并读取与CPU从附加存储器读取的数据相关联的奇偶校验位，并重新生成新的奇偶校验位，并将新生成的奇偶校验位与原始奇偶校验位进行比较，以检测从附加存储器读取的数据上的数据错误。系统本身不包含纠错码（ECC）。附加存储器具有ECC逻辑，用于识别在数据字节中具有单个位错误的任何字节或由CPU向附加存储器写入的奇偶校验位，并校正从附件读取的数据中的所有单个位错误内存到CPU。纠错码包括在由CPU向附加存储器写入的数据字节中生成奇偶校验位的逻辑，以及将由CPU写入的奇偶校验位与由纠错码逻辑生成的奇偶校验位进行比较的逻辑。

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