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1. 发明授权

US5373893A Method and apparatus for cooling thermally massive parts in a continuous furnace 失效
标题翻译：用于在连续炉中冷却热块状部件的方法和装置
公开(公告)号：US5373893A
公开(公告)日：1994-12-20
申请号：US963500
申请日：1992-10-19
申请人： David E. Eisenmann , Peter M. Elenius , James M. Leas , Wagih M. Wazni
发明人： David E. Eisenmann , Peter M. Elenius , James M. Leas , Wagih M. Wazni
IPC分类号： C21D1/613 , C21D9/00 , F25D3/11 , F27D15/02 , F27D19/00 , F27D21/00 , G01R31/28 , F25D13/06
CPC分类号： G01R31/2875 , C21D1/613 , C21D9/0062 , F25D3/11 , F27D15/0266 , F27D2019/0034 , F27D2019/0068 , F27D21/00
摘要： A method and apparatus for cooling thermally massive parts includes directing a chilled gas onto an electrical component travelling on the belt of a continuous furnace. The belt is divided into a series of hot and cold zones to provide thermal stressing to the electrical component to detect early life failure. As the component cools, a constant thermal stress is maintained by either lowering the temperature or increasing the flow rate of the chilled gas.
摘要翻译：用于冷却热块状部件的方法和装置包括将冷却的气体引导到在连续炉的带上行进的电气部件上。皮带分为一系列热和冷区域，以向电气部件提供热应激，以检测早期的生命故障。当组件冷却时，通过降低温度或增加冷却气体的流速来保持恒定的热应力。

2. 发明授权

US6037210A Memory cell with transfer device node in selective polysilicon 失效
标题翻译：具有选择性多晶硅传输器件节点的存储单元
公开(公告)号：US6037210A
公开(公告)日：2000-03-14
申请号：US49947
申请日：1998-03-30
申请人： James M. Leas
发明人： James M. Leas
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10861 , H01L27/10832
摘要： A memory cell is constructed with one electrode of the transfer device extending over a trench capacitor, saving about 6.5% of cell area. Selective polysilicon for a strap seeded from the trench is grown in the same step in which selective single crystal silicon seeded from the substrate is grown for the transfer device. At least a portion of the node diffusion is located in single crystal epitaxial silicon extending over the trench. The process eliminates the need for a separate strap masking step.
摘要翻译：存储单元被构造成具有在沟槽电容器上延伸的转移装置的一个电极，节省了细胞面积的约6.5％。用于从沟槽接种的带的选择性多晶硅在与从衬底接种的选择性单晶硅生长用于转移装置的相同步骤中生长。节点扩散的至少一部分位于在沟槽上延伸的单晶外延硅中。该过程消除了对单独的带屏蔽步骤的需要。

3. 发明授权

US5466634A Electronic modules with interconnected surface metallization layers and fabrication methods therefore 失效
标题翻译：因此，具有互连表面金属化层的电子模块和制造方法
公开(公告)号：US5466634A
公开(公告)日：1995-11-14
申请号：US359982
申请日：1994-12-20
申请人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , John E. Cronin , Wayne J. Howell , James M. Leas , Robert B. Phillips
发明人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , John E. Cronin , Wayne J. Howell , James M. Leas , Robert B. Phillips
IPC分类号： H01L23/538 , H01L21/98 , H01L25/065 , H01L25/07 , H01L25/18 , H01L21/44
CPC分类号： H01L25/50 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2224/24145 , H01L2224/48091 , H01L2224/49109 , H01L2225/0651 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06596 , H01L2924/30107
摘要： Methods of fabrication for electronic modules having electrically interconnected side and end surface metallization layers and associated electronic modules are set forth. The methods include providing a stack comprising a plurality of stacked IC chips. A side surface thin-film metallization layer is formed on the stack. Next, an end surface thin-film metallization layer is formed the stack such that the side surface and end surface thin-film metallization layers directly electrically interconnect. Alternatively, each IC chip of a stack may include an end surface metallization layer such that separate formation of an end surface metallization layer on an end surface of the stack is unnecessary. The methods also include forming an electronic module by first providing a long stack of IC chips, testing the chips of the stack, and then segmenting the long stack into multiple small stacks of functional IC chips based upon the test results. Specific details of electronic modules, IC chips contained therein, and stacks composed thereof are also set forth.
摘要翻译：阐述了具有电互连的侧表面金属化层和相关的电子模块的电子模块的制造方法。所述方法包括提供包括多个堆叠的IC芯片的堆叠。在堆叠上形成侧面薄膜金属化层。接下来，将端面薄膜金属化层形成为堆叠，使得侧表面和端面薄膜金属化层直接电互连。或者，堆叠的每个IC芯片可以包括端面金属化层，使得不需要在堆叠的端表面上分离形成端面金属化层。所述方法还包括通过首先提供长堆叠的IC芯片，测试堆叠的芯片，然后基于测试结果将长堆叠分成多个小堆功能IC芯片来形成电子模块。还阐述了电子模块，其中包含的IC芯片及其组成的具体细节。

4. 发明授权

US5135233A Pendulum toy 失效
标题翻译：钟摆玩具
公开(公告)号：US5135233A
公开(公告)日：1992-08-04
申请号：US624342
申请日：1990-11-29
申请人： James M. Leas , Sandra F. C. Leas , Zoe J. Leas
发明人： James M. Leas , Sandra F. C. Leas , Zoe J. Leas
IPC分类号： A63B67/10
CPC分类号： A63B67/10 , A63B2208/12
摘要： The present invention provides an apparatus and method for safely playing a catching, hitting, or throwing game with an infant or disabled adult. The object to be caught, hit, or thrown is made the base of a pendulum and the object is caught, hit, or thrown near the most elevated position/location of the arc of the pendulum, at which the object comes to rest and where it is therefore easiest to catch, hit, or throw. Means are included to avoid hazards of hanging, strangling, choking, and contusions.
摘要翻译：本发明提供一种用于安全地玩婴儿或残疾成人的捕捉，打击或投掷游戏的装置和方法。要抓住，撞击或投掷的物体被制成摆锤的基部，并且物体被捕获，撞击或抛在靠近摆锤弧的最高位置/位置附近因此，最容易抓住，打击或投掷。包括手段，以避免悬挂，窒息，窒息和挫伤的危险。

5. 发明授权

US07176089B2 Vertical dual gate field effect transistor 失效
标题翻译：垂直双栅场效应晶体管
公开(公告)号：US07176089B2
公开(公告)日：2007-02-13
申请号：US10853177
申请日：2004-05-26
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , James M. Leas , William H-L Ma , Paul A. Rabidoux
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , James M. Leas , William H-L Ma , Paul A. Rabidoux
IPC分类号： H01L21/336
CPC分类号： H01L29/78642 , H01L21/2255 , H01L21/76897 , H01L21/823487 , H01L27/088 , H01L29/66666 , H01L29/7827 , H01L29/7831
摘要： A method of manufacturing provides a vertical transistor particularly suitable for high density integration and which includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.
摘要翻译：一种制造方法提供特别适用于高密度积分的垂直晶体管，其包括通过在沟槽中蚀刻或外延生长而形成的半导体柱的相对侧上的潜在独立栅极结构。栅极结构被绝缘材料包围，绝缘材料可选择性地蚀刻到围绕晶体管的隔离材料。通过选择性地蚀刻对绝缘材料有选择性的隔离材料，对柱的下端（例如，晶体管漏极）进行接触。柱的上端由盖和可选择性蚀刻材料的侧壁覆盖，使得栅极和源极连接开口也可以通过具有良好配准公差的选择性蚀刻制成。在平行于芯片表面的方向上的柱的尺寸由隔离区域和选择性蚀刻之间的距离限定，并且柱的高度由牺牲层的厚度限定。

6. 发明授权

US5714039A Method for making sub-lithographic images by etching the intersection of two spacers 失效
标题翻译：通过蚀刻两个间隔物进行亚光刻图像的方法
公开(公告)号：US5714039A
公开(公告)日：1998-02-03
申请号：US539244
申请日：1995-10-04
申请人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , James M. Leas , Jack A. Mandelman
发明人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , James M. Leas , Jack A. Mandelman
IPC分类号： H01L21/306 , H01L21/033 , H01L21/311 , H01L21/3213 , H01L21/46 , H01L21/8242 , H01L27/108 , H01L21/3105
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： A method of forming a sub-lithographic image formed by the intersection of two spacers. A substrate with a first pattern of selectively etchable material with sidewalls that are substantially vertical is provided. A first sidewall spacer is formed of a material that is selectively etchable relative to the first pattern material. A second pattern of a selectively etchable material is formed with the second pattern intersecting the first pattern. The sidewalls of the second pattern are substantially vertical as well. A second sidewall spacer is formed of a material that is selectively etchable relative to the second pattern material. The second pattern material is etched to leave the second sidewall spacer. Alternatively, the first and/or second pattern materials may be totally removed, left in place, or planarized.
摘要翻译：一种形成由两个间隔物相交形成的亚光刻图像的方法。提供具有基本上垂直的侧壁的具有可选择性蚀刻材料的第一图案的衬底。第一侧壁间隔物由相对于第一图案材料可选择性蚀刻的材料形成。形成与第一图案相交的第二图案的可选择性蚀刻材料的第二图案。第二图案的侧壁也是基本垂直的。第二侧壁间隔件由相对于第二图案材料可选择地蚀刻的材料形成。蚀刻第二图案材料以离开第二侧壁间隔物。或者，第一和/或第二图案材料可以被完全去除，留在原位或平坦化。

7. 发明授权

US5567654A Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging 失效
标题翻译：将薄层连接到单片电子模块表面的方法和工件以及相关的模块封装
公开(公告)号：US5567654A
公开(公告)日：1996-10-22
申请号：US313976
申请日：1994-09-28
申请人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , John E. Cronin , Wayne J. Howell , James M. Leas , David J. Perlman
发明人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , John E. Cronin , Wayne J. Howell , James M. Leas , David J. Perlman
IPC分类号： H01L21/98 , H01L23/498 , H01L25/065 , H01L25/18 , H01L21/60
CPC分类号： H01L25/50 , H01L23/49827 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/16145 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/49107 , H01L2224/49109 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06582 , H01L2225/06586 , H01L2225/06589 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01039 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15312 , H01L2924/1532 , H01L2924/16152 , H01L2924/16195 , H01L2924/30107
摘要： A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary support which is used to attach the thin-film layer to the electronic module. The disclosed techniques may also be used for attaching an interposer, which may include active circuity, to an electronic module. Specific details of the fabrication method, resulting multichip packages, and various thin-film structures are set forth.
摘要翻译：一种具有附接到侧表面的单独形成的薄膜层的制造方法和所得到的单片电子模块。该制造方法包括提供由堆叠的集成电路芯片组成的电子模块。在用于将薄膜层附着到电子模块的临时支架上分开形成薄膜层。所公开的技术还可以用于将可包括有源电路的插入件附接到电子模块。阐述了制造方法，所得到的多芯片封装以及各种薄膜结构的具体细节。

8. 发明授权

US07132841B1 Carrier for test, burn-in, and first level packaging 失效
标题翻译：用于测试，老化和一级包装的载体
公开(公告)号：US07132841B1
公开(公告)日：2006-11-07
申请号：US09588617
申请日：2000-06-06
申请人： Claude L. Bertin , Wayne F. Ellis , Mark W. Kellogg , William R. Tonti , Jerzy M. Zalesinski , James M. Leas , Wayne J. Howell
发明人： Claude L. Bertin , Wayne F. Ellis , Mark W. Kellogg , William R. Tonti , Jerzy M. Zalesinski , James M. Leas , Wayne J. Howell
IPC分类号： G01R31/26 , G01R31/28
CPC分类号： G01R31/2867 , G11C5/04 , G11C29/06 , G11C29/1201 , G11C29/48 , G11C29/56016 , G11C29/785 , G11C2029/2602 , G11C2029/5602 , H01L22/22 , H01L22/32 , H01L2924/0002 , H01L2924/00
摘要： A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier. The carrier is formed of a flex material. It can also be formed of printed circuit board material. A window in the flex permits invoking redundancy on each chip after burn-in is complete, significantly improving yield as compared with present schemes that do not permit repair after burn-in.
摘要翻译：在载体上提供多个半导体器件用于测试或烧录。然后将载体切割以提供单个芯片上载波部件或多芯片载波部件。载体用作每个芯片的第一级封装。因此，载体用于测试和烧录和包装的双重目的。可以在每个芯片或载体上提供诸如内置自检引擎的引线减少机构，并且连接到载体的触点用于测试和老化步骤。切割后的最终包装包括至少一个已知的良好的模具，并且可以包括载体上的芯片阵列，例如SIMM或DIMM。最终的包装也可以是一堆芯片，每个芯片都安装在单独的载体上。堆叠的载体通过沿着堆叠的侧面安装的基板彼此连接，该基板沿着每个载体的边缘电连接到焊盘一排。载体由柔性材料形成。它也可以由印刷电路板材料形成。柔性窗口允许在烧坏完成后在每个芯片上调用冗余度，与不允许在老化后修复的现有方案相比，显着提高产量。

9. 发明授权

US5610409A Optical FET with diode adjacent gate 失效
标题翻译：具有二极管相邻栅极的光FET
公开(公告)号：US5610409A
公开(公告)日：1997-03-11
申请号：US643675
申请日：1996-05-06
申请人： James M. Leas , Jack A. Mandelman
发明人： James M. Leas , Jack A. Mandelman
IPC分类号： H01L25/04 , H01L31/112 , H01L29/04
CPC分类号： H01L25/043 , H01L31/1126 , H01L2924/0002
摘要： An optical FET includes one or more light-responsive diodes stacked on the gate. Each diode includes a planar (horizontal) junction. The number of diodes is chosen to achieve a desired gate to source potential difference. An electrical connection connects the diode(s) to the source of the FET.
摘要翻译：光学FET包括堆叠在栅极上的一个或多个光响应二极管。每个二极管包括平面（水平）结。选择二极管的数量以实现期望的栅极到源极电位差。电气连接将二极管连接到FET的源极。

10. 发明授权

US5517057A Electronic modules with interconnected surface metallization layers 失效
标题翻译：具有互连表面金属化层的电子模块
公开(公告)号：US5517057A
公开(公告)日：1996-05-14
申请号：US451356
申请日：1995-05-26
申请人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , John E. Cronin , Wayne J. Howell , James M. Leas , Robert B. Phillips
发明人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , John E. Cronin , Wayne J. Howell , James M. Leas , Robert B. Phillips
IPC分类号： H01L23/538 , H01L21/98 , H01L25/065 , H01L25/07 , H01L25/18 , H01L23/48 , H01L23/522
CPC分类号： H01L25/50 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2224/24145 , H01L2224/48091 , H01L2224/49109 , H01L2225/0651 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06596 , H01L2924/30107
摘要： Methods of fabrication for electronic modules having electrically interconnected side and end surface metallization layers and associated electronic modules are set forth. The methods include providing a stack comprising a plurality of stacked IC chips. A side surface thin-film metallization layer is formed on the stack. Next, an end surface thin-film metallization layer is formed the stack such that the side surface and end surface thin-film metallization layers directly electrically interconnect. Alternatively, each IC chip of a stack may include an end surface metallization layer such that separate formation of an end surface metallization layer on an end surface of the stack is unnecessary. The methods also include forming an electronic module by first providing a long stack of IC chips, testing the chips of the stack, and then segmenting the long stack into multiple small stacks of functional IC chips based upon the test results. Specific details of electronic modules, IC chips contained therein, and stacks composed thereof are also set forth.
摘要翻译：阐述了具有电互连的侧表面金属化层和相关的电子模块的电子模块的制造方法。所述方法包括提供包括多个堆叠的IC芯片的堆叠。在堆叠上形成侧面薄膜金属化层。接下来，将端面薄膜金属化层形成为堆叠，使得侧表面和端面薄膜金属化层直接电互连。或者，堆叠的每个IC芯片可以包括端面金属化层，使得不需要在堆叠的端表面上分离形成端面金属化层。所述方法还包括通过首先提供长堆叠的IC芯片，测试堆叠的芯片，然后基于测试结果将长堆叠分成多个小堆功能IC芯片来形成电子模块。还阐述了电子模块，其中包含的IC芯片及其组成的具体细节。

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