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91. 发明授权

US6153902A Vertical DRAM cell with wordline self-aligned to storage trench 有权
标题翻译：垂直DRAM单元与字线自对准到存储沟槽
公开(公告)号：US6153902A
公开(公告)日：2000-11-28
申请号：US374687
申请日：1999-08-16
申请人： Toshiharu Furukawa , Ulrike Gruening , David V. Horak , Jack A. Mandelman , Carl J. Radens , Thomas S. Rupp
发明人： Toshiharu Furukawa , Ulrike Gruening , David V. Horak , Jack A. Mandelman , Carl J. Radens , Thomas S. Rupp
IPC分类号： H01L27/108 , H01L21/8242 , H01L29/78 , H01L33/00
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A dynamic random access memory (DRAM) device. The DRAM device is formed in a substrate having a top surface and a trench with a sidewall formed in the substrate. A signal storage node is formed using a bottom portion of the trench and a signal transfer device is formed using an upper portion of the trench. The signal transfer device includes a first diffusion region coupled to the signal storage node and extending from the sidewall of the trench into the substrate, a second diffusion region formed in the substrate adjacent to the top surface of the substrate and adjacent the sidewall of the trench, a channel region extending along the sidewall of the trench between the first diffusion region and the second diffusion region, a gate insulator formed along the sidewall of the trench extending from the first diffusion region to the second diffusion region, a gate conductor filling the trench and having a top surface, and a wordline having a bottom adjacent the top surface of the gate conductor and a side aligned with the sidewall of the trench.
摘要翻译：动态随机存取存储器（DRAM）设备。 DRAM器件形成在具有顶表面的衬底和具有形成在衬底中的侧壁的沟槽中。使用沟槽的底部形成信号存储节点，并且使用沟槽的上部形成信号传送装置。信号传送装置包括耦合到信号存储节点并从沟槽的侧壁延伸到衬底中的第一扩散区域，形成在衬底中邻近衬底的顶表面并邻近沟槽的侧壁的第二扩散区域沿着沟槽的侧壁在第一扩散区域和第二扩散区域之间延伸的沟道区域，沿着从第一扩散区域延伸到第二扩散区域的沟槽的侧壁形成的栅极绝缘体，填充沟槽的栅极导体并且具有顶表面和字线，其具有邻近栅极导体的顶表面的底部和与沟槽的侧壁对准的一侧。

92. 发明授权

US5928967A Selective oxide-to-nitride etch process using C.sub.4 F.sub.8 /CO/Ar 失效
标题翻译：使用C4F8 / CO / Ar的选择性氧化物到氮化物蚀刻工艺
公开(公告)号：US5928967A
公开(公告)日：1999-07-27
申请号：US662754
申请日：1996-06-10
申请人： Carl J. Radens , Cynthia A. Fairchok
发明人： Carl J. Radens , Cynthia A. Fairchok
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/60 , H01L21/473
CPC分类号： H01L21/76897 , H01L21/31116
摘要： A dry etch process for use in the fabrication of integrated circuits which use SiN etch stop layers is disclosed. The process is conducted in a reactive-ion etch reactor and employs a gaseous etchant mixture comprised of octaflourocyclobutane (C.sub.4 F.sub.8), carbon monoxide (CO) and Ar. The specific process parameters effect the formation of a polymer on SiN but not on oxide, thereby resulting in a very high etch rate selectivity of the oxide to the nitride.
摘要翻译：公开了用于制造使用SiN蚀刻停止层的集成电路的干蚀刻工艺。该方法在反应离子蚀刻反应器中进行，并使用由八氟环丁烷（C 4 F 8），一氧化碳（CO）和Ar组成的气态蚀刻剂混合物。具体的工艺参数影响在SiN上形成聚合物而不影响氧化物，从而导致氧化物对氮化物的非常高的蚀刻速率选择性。

93. 发明授权

US09511918B2 Self-locking container 有权
标题翻译：自锁容器
公开(公告)号：US09511918B2
公开(公告)日：2016-12-06
申请号：US13340776
申请日：2011-12-30
申请人： Ira L. Allen , Lawrence A. Clevenger , Kevin S. Petrarca , Carl J. Radens
发明人： Ira L. Allen , Lawrence A. Clevenger , Kevin S. Petrarca , Carl J. Radens
IPC分类号： B65D79/02 , B65D55/10 , B65D41/04 , A61J1/03
CPC分类号： B65D79/02 , A61J1/03 , A61J2200/72 , B65D41/04 , B65D55/10 , B65D2213/00
摘要： Method and apparatus to provide a self-locking container to prevent unwanted access to materials stored in the container as a result of exposure to conditions that compromise the effectiveness or safety of the materials. A container may be threaded to receive a threaded lid, and the container may comprise a bolt movable within a channel from a retracted position, which allows the lid to be threadably connected or removed, to a locked position, which prevents removal of the lid. The bolt is movable to the locked position by a drive member, such as a bimetallic strip or a shape-memory element that drive the bolt in response to exposure to the condition that compromises the material.
摘要翻译：提供自锁容器的方法和装置，以防止由于暴露于损害材料的有效性或安全性的条件而导致存储在容器中的材料的不期望的访问。容器可以是螺纹以接收带螺纹的盖子，并且容器可以包括螺栓，该螺栓可在通道内从缩回位置移动，该缩回位置允许盖子被螺纹连接或移除到锁定位置，从而防止盖子移除。螺栓通过驱动构件（例如双金属条或形状记忆元件）可移动到锁定位置，该双金属条或形状记忆元件响应于暴露于损害材料的状况而驱动螺栓。

94. 发明授权

US08779511B2 Integration of fin-based devices and ETSOI devices 有权
标题翻译：集成了鳍式设备和ETSOI设备
公开(公告)号：US08779511B2
公开(公告)日：2014-07-15
申请号：US13530887
申请日：2012-06-22
申请人： Narasimhulu Kanike , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
发明人： Narasimhulu Kanike , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L27/088
CPC分类号： H01L27/1211 , H01L21/845
摘要： Thin semiconductor regions and thick semiconductor regions are formed oven an insulator layer. Thick semiconductor regions include at least one semiconductor fin. A gate conductor layer is patterned to form disposable planar gate electrodes over ETSOI regions and disposable side gate electrodes on sidewalls of semiconductor fins. End portions of the semiconductor fins are vertically recessed to provide thinned fin portions adjacent to an unthinned fin center portion. After appropriate masking by dielectric layers, selective epitaxy is performed on planar source and drain regions of ETSOI field effect transistors (FETs) to form raised source and drain regions. Further, fin source and drain regions are grown on the thinned fin portions. Source and drain regions, fins, and the disposable gate electrodes are planarized. The disposable gate electrodes are replaced with metal gate electrodes. FinFETs and ETSOI FETs are provided on the same semiconductor substrate.
摘要翻译：薄半导体区域和厚半导体区域被形成为绝缘体层。厚半导体区域包括至少一个半导体鳍片。图案化栅极导体层以在半导体鳍片的侧壁上的ETSOI区域和一次侧栅电极上形成一次性平面栅电极。半导体翅片的端部垂直凹入，以提供与未固定的翅片中心部分相邻的变薄的翅片部分。在通过介电层适当掩蔽之后，在ETSOI场效应晶体管（FET）的平面源极和漏极区域上进行选择性外延以形成升高的源极和漏极区域。此外，翅片源极和漏极区域在薄的鳍部上生长。源极和漏极区域，鳍片和一次性栅电极被平坦化。一次性栅电极被金属栅电极代替。 FinFET和ETSOI FET设置在相同的半导体衬底上。

95. 发明授权

US08704332B2 Metal oxide semiconductor field effect transistor (MOSFET) gate termination 有权
标题翻译：金属氧化物半导体场效应晶体管（MOSFET）门极端接
公开(公告)号：US08704332B2
公开(公告)日：2014-04-22
申请号：US13495081
申请日：2012-06-13
申请人： Christopher V. Baiocco , Daniel J. Jaeger , Carl J. Radens , Helen Wang
发明人： Christopher V. Baiocco , Daniel J. Jaeger , Carl J. Radens , Helen Wang
IPC分类号： H01L29/786 , H01L29/78 , H01L29/06
CPC分类号： H01L29/7816 , H01L21/28247 , H01L29/0642 , H01L29/0649 , H01L29/51 , H01L29/66477 , H01L29/66575 , H01L29/78
摘要： A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure.
摘要翻译：提供一种形成半导体器件的方法，其包括在半导体衬底中形成含有隔离区的氧化物以限定有源半导体区域。然后可以在有源半导体区域上形成包括高k栅极电介质层的覆盖栅极堆叠。覆盖栅极堆叠的至少一部分从有源半导体器件区域延伸到隔离区域。然后可以对覆盖栅极堆叠进行蚀刻以在隔离区域上提供开口。然后可以对由开口暴露的隔离区域的表面进行各向同性蚀刻，以在隔离区域内形成在高k栅极电介质层下延伸的底切区域。然后可以在填充底切区域的开口中形成密封电介质材料。然后可以对覆盖栅极堆叠进行构图以形成栅极结构。

96. 发明授权

US08665575B2 Solar module with overheat protection 有权
标题翻译：太阳能组件具有过热保护功能
公开(公告)号：US08665575B2
公开(公告)日：2014-03-04
申请号：US13166842
申请日：2011-06-23
申请人： Lawrence A. Clevenger , Harold J. Hovel , Rainer Krause , Zhengwen Li , Kevin S. Petrarca , Gerd Pfeiffer , Kevin Prettyman , Carl J. Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Harold J. Hovel , Rainer Krause , Zhengwen Li , Kevin S. Petrarca , Gerd Pfeiffer , Kevin Prettyman , Carl J. Radens , Brian C. Sapp
IPC分类号： H02H5/04
CPC分类号： H02H7/20 , H01L31/02021 , H02H5/047 , Y02E10/50
摘要： A photovoltaic module (10) with a plurality of solar cells (20) interconnected in serial and/or parallel arrangement within the module (10) is equipped with an overheat protection system (30) for suppressing damages of the photovoltaic module (10) due to defects of the solar cells (20). The overheat protection system (30) comprises a heat sensor (32) which is thermally coupled to a solar cell (20). The heat sensor (32) is physically integrated into an electrical switch (34, 36, 38) which is electrically connected to said solar cell (20).
摘要翻译：具有在模块（10）内以串联和/或并联布置互连的多个太阳能电池（20）的光伏模块（10）装备有过热保护系统（30），用于抑制光伏模块（10）的损坏涉及太阳能电池的缺陷（20）。过热保护系统（30）包括热耦合到太阳能电池（20）的热传感器（32）。热传感器（32）物理地集成在电连接到所述太阳能电池（20）的电开关（34,36,38）中。

97. 发明授权

US08421077B2 Replacement gate MOSFET with self-aligned diffusion contact 有权
标题翻译：具有自对准扩散接触的替代栅极MOSFET
公开(公告)号：US08421077B2
公开(公告)日：2013-04-16
申请号：US12795973
申请日：2010-06-08
申请人： Sameer H. Jain , Carl J. Radens , Shahab Siddiqui , Jay W. Strane
发明人： Sameer H. Jain , Carl J. Radens , Shahab Siddiqui , Jay W. Strane
IPC分类号： H01L29/10
CPC分类号： H01L29/7833 , H01L21/76834 , H01L21/76897 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659
摘要： A replacement gate field effect transistor includes at least one self-aligned contact that overlies a portion of a dielectric gate cap. A replacement gate stack is formed in a cavity formed by removal of a disposable gate stack. The replacement gate stack is subsequently recessed, and a dielectric gate cap having sidewalls that are vertically coincident with outer sidewalls of the gate spacer is formed by filling the recess over the replacement gate stack. An anisotropic etch removes the dielectric material of the planarization layer selective to the material of the dielectric gate cap, thereby forming at least one via cavity having sidewalls that coincide with a portion of the sidewalls of the gate spacer. A portion of each diffusion contact formed by filling the at least one via cavity overlies a portion of the gate spacer and protrudes into the dielectric gate cap.
摘要翻译：替代栅极场效应晶体管包括至少一个自对准接触，其覆盖在电介质栅极盖的一部分上。在通过去除一次性栅极堆叠而形成的空腔中形成替换栅极堆叠。替换栅极堆叠随后被凹入，并且具有与栅极间隔物的外侧壁垂直重合的侧壁的电介质栅极盖通过在该替代栅极叠层上填充该凹槽来形成。各向异性蚀刻去除对介电栅极盖的材料有选择性的平坦化层的电介质材料，从而形成具有与栅极间隔物的侧壁的一部分重合的侧壁的至少一个通孔。通过填充至少一个通孔形成的每个扩散接触部分覆盖在栅极间隔物的一部分上并且突出到电介质栅极帽中。

98. 发明授权

US08373239B2 Structure and method for replacement gate MOSFET with self-aligned contact using sacrificial mandrel dielectric 有权
公开(公告)号：US08373239B2
公开(公告)日：2013-02-12
申请号：US12795962
申请日：2010-06-08
申请人： Shahab Siddiqui , Michael P. Chudzik , Carl J. Radens
发明人： Shahab Siddiqui , Michael P. Chudzik , Carl J. Radens
IPC分类号： H01L21/70
CPC分类号： H01L29/66575 , H01L21/28088 , H01L21/76897 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66545
摘要： The present disclosure provides a method for forming a semiconductor device that includes forming a replacement gate structure overlying a channel region of a substrate. A mandrel dielectric layer is formed overlying source and drain regions of the substrate. The replacement gate structure is removed to provide an opening exposing the channel region of the substrate. A functional gate structure is formed over the channel region including a work function metal layer. A protective cap structure is formed over the functional gate structure. At least one via is etched through the mandrel dielectric layer selective to the protective cap structure to expose a portion of at least one of the source region and the drain region. A conductive fill is then formed in the vias to provide a contact to the at least one of the source region and the drain region.

99. 发明申请

US20120175694A1 STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM 有权
标题翻译：形成增强板阵列隔离装置的结构和方法
公开(公告)号：US20120175694A1
公开(公告)日：2012-07-12
申请号：US13408187
申请日：2012-02-29
申请人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
发明人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/108
CPC分类号： H01L27/10823 , H01L21/76264 , H01L21/84 , H01L27/10829 , H01L27/1087 , H01L27/10897 , H01L27/1203 , H01L29/0653 , H01L29/66181
摘要： A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.
摘要翻译：提供了一种存储器件，其包括绝缘体上半导体（SOI）衬底，其包括位于掩埋介电层顶部的第一半导体层，其中所述掩埋介电层覆盖在第二半导体层上。电容器存在于沟槽中，其中沟槽从第一半导体层的上表面延伸穿过埋入介质层并延伸到第二半导体层。保护性氧化物存在于位于第一半导体层附近的空隙中，并且传导晶体管存在于与电容器电连通的绝缘体上半导体衬底上。

100. 发明申请

US20110312136A1 STRUCTURE AND METHOD FOR COMPACT LONG-CHANNEL FETs 失效
标题翻译：紧凑型长沟道FET的结构和方法
公开(公告)号：US20110312136A1
公开(公告)日：2011-12-22
申请号：US13223940
申请日：2011-09-01
申请人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper
发明人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper
IPC分类号： H01L21/336
CPC分类号： H01L29/1037 , H01L29/6659 , H01L29/66621
摘要： A compact semiconductor structure including at least one FET located upon and within a surface of a semiconductor substrate in which the at least one FET includes a long channel length and/or a wide channel width and a method of fabricating the same are provided. In some embodiments, the ordered, nanosized pattern is oriented in a direction that is perpendicular to the current flow. In such an embodiment, the FET has a long channel length. In other embodiments, the ordered, nanosized pattern is oriented in a direction that is parallel to that of the current flow. In such an embodiment, the FET has a wide channel width. In yet another embodiment, one ordered, nanosized pattern is oriented in a direction perpendicular to the current flow, while another ordered, nanosized pattern is oriented in a direction parallel to the current flow. In such an embodiment, a FET having a long channel length and wide channel width is provided.
摘要翻译：一种紧凑的半导体结构，其包括至少一个位于半导体衬底的表面之上和之中的FET，其中所述至少一个FET包括长沟道长度和/或宽沟道宽度及其制造方法。在一些实施例中，有序的纳米尺寸图案在垂直于电流的方向上定向。在这样的实施例中，FET具有长的沟道长度。在其他实施例中，有序的纳米尺寸图案在平行于电流流动的方向上取向。在这样的实施例中，FET具有宽的通道宽度。在另一个实施例中，一个有序的纳米尺寸图案在垂直于电流的方向上定向，而另一个有序的纳米尺寸图案在平行于电流的方向上取向。在这样的实施例中，提供具有长沟道长度和宽沟道宽度的FET。

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