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1. 发明授权

US08299455B2 Semiconductor structures having improved contact resistance 有权
标题翻译：具有改善的接触电阻的半导体结构
公开(公告)号：US08299455B2
公开(公告)日：2012-10-30
申请号：US11872291
申请日：2007-10-15
申请人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper , Jay W. Strane
发明人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper , Jay W. Strane
IPC分类号： H01L29/06
CPC分类号： H01L21/28518 , B81B2207/07 , B81C1/00095 , B81C2201/0149 , H01L21/3086 , H01L21/76886 , H01L23/485 , H01L23/5226 , H01L29/41766 , H01L29/665 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.
摘要翻译：自组装聚合物技术用于在存在于半导体结构的导电接触区域中的材料内形成至少一个有序的纳米尺度图案。具有有序纳米尺寸图案的材料是场效应晶体管的互连结构或半导体源和漏极扩散区的导电材料。在接触区域内有序的纳米尺寸图案材料的存在增加了用于随后的接触形成的总面积（即界面面积），这又降低了结构的接触电阻。接触电阻的降低又改善了通过结构的电流的流动。除了上述之外，本发明的方法和结构不影响结构的结电容，因为结面积保持不变。

2. 发明申请

US20110312136A1 STRUCTURE AND METHOD FOR COMPACT LONG-CHANNEL FETs 失效
标题翻译：紧凑型长沟道FET的结构和方法
公开(公告)号：US20110312136A1
公开(公告)日：2011-12-22
申请号：US13223940
申请日：2011-09-01
申请人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper
发明人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper
IPC分类号： H01L21/336
CPC分类号： H01L29/1037 , H01L29/6659 , H01L29/66621
摘要： A compact semiconductor structure including at least one FET located upon and within a surface of a semiconductor substrate in which the at least one FET includes a long channel length and/or a wide channel width and a method of fabricating the same are provided. In some embodiments, the ordered, nanosized pattern is oriented in a direction that is perpendicular to the current flow. In such an embodiment, the FET has a long channel length. In other embodiments, the ordered, nanosized pattern is oriented in a direction that is parallel to that of the current flow. In such an embodiment, the FET has a wide channel width. In yet another embodiment, one ordered, nanosized pattern is oriented in a direction perpendicular to the current flow, while another ordered, nanosized pattern is oriented in a direction parallel to the current flow. In such an embodiment, a FET having a long channel length and wide channel width is provided.
摘要翻译：一种紧凑的半导体结构，其包括至少一个位于半导体衬底的表面之上和之中的FET，其中所述至少一个FET包括长沟道长度和/或宽沟道宽度及其制造方法。在一些实施例中，有序的纳米尺寸图案在垂直于电流的方向上定向。在这样的实施例中，FET具有长的沟道长度。在其他实施例中，有序的纳米尺寸图案在平行于电流流动的方向上取向。在这样的实施例中，FET具有宽的通道宽度。在另一个实施例中，一个有序的纳米尺寸图案在垂直于电流的方向上定向，而另一个有序的纳米尺寸图案在平行于电流的方向上取向。在这样的实施例中，提供具有长沟道长度和宽沟道宽度的FET。

3. 发明申请

US20120132966A1 SEMICONDUCTOR STRUCTURES HAVING IMPROVED CONTACT RESISTANCE 有权
标题翻译：具有改善接触电阻的半导体结构
公开(公告)号：US20120132966A1
公开(公告)日：2012-05-31
申请号：US11872291
申请日：2007-10-15
申请人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper , Jay W. Strane
发明人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper , Jay W. Strane
IPC分类号： H01L29/78 , H01L21/768 , H01L23/52
CPC分类号： H01L21/28518 , B81B2207/07 , B81C1/00095 , B81C2201/0149 , H01L21/3086 , H01L21/76886 , H01L23/485 , H01L23/5226 , H01L29/41766 , H01L29/665 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.
摘要翻译：自组装聚合物技术用于在存在于半导体结构的导电接触区域中的材料内形成至少一个有序的纳米尺度图案。具有有序纳米尺寸图案的材料是场效应晶体管的互连结构或半导体源和漏极扩散区的导电材料。在接触区域内有序的纳米尺寸图案材料的存在增加了用于随后的接触形成的总面积（即界面面积），这又降低了结构的接触电阻。接触电阻的降低又改善了通过结构的电流的流动。除了上述之外，本发明的方法和结构不影响结构的结电容，因为结面积保持不变。

4. 发明申请

US20120208332A1 SEMICONDUCTOR STRUCTURES HAVING IMPROVED CONTACT RESISTANCE 有权
公开(公告)号：US20120208332A1
公开(公告)日：2012-08-16
申请号：US13454709
申请日：2012-04-24
申请人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper , Jay W. Strane
发明人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper , Jay W. Strane
IPC分类号： H01L21/336
CPC分类号： H01L21/28518 , B81B2207/07 , B81C1/00095 , B81C2201/0149 , H01L21/3086 , H01L21/76886 , H01L23/485 , H01L23/5226 , H01L29/41766 , H01L29/665 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.

5. 发明授权

US08013367B2 Structure and method for compact long-channel FETs 失效
标题翻译：紧凑型长沟道FET的结构和方法
公开(公告)号：US08013367B2
公开(公告)日：2011-09-06
申请号：US11937161
申请日：2007-11-08
申请人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper
发明人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/1037 , H01L29/6659 , H01L29/66621
摘要： A compact semiconductor structure including at least one FET located upon and within a surface of a semiconductor substrate in which the at least one FET includes a long channel length and/or a wide channel width and a method of fabricating the same are provided. In some embodiments, the ordered, nanosized pattern is oriented in a direction that is perpendicular to the current flow. In such an embodiment, the FET has a long channel length. In other embodiments, the ordered, nanosized pattern is oriented in a direction that is parallel to that of the current flow. In such an embodiment, the FET has a wide channel width. In yet another embodiment, one ordered, nanosized pattern is oriented in a direction perpendicular to the current flow, while another ordered, nanosized pattern is oriented in a direction parallel to the current flow. In such an embodiment, a FET having a long channel length and wide channel width is provided.
摘要翻译：一种紧凑的半导体结构，其包括至少一个位于半导体衬底的表面之上和之中的FET，其中所述至少一个FET包括长沟道长度和/或宽沟道宽度及其制造方法。在一些实施例中，有序的纳米尺寸图案在垂直于电流的方向上取向。在这样的实施例中，FET具有长的沟道长度。在其他实施例中，有序的纳米尺寸图案在平行于电流流动的方向上取向。在这样的实施例中，FET具有宽的通道宽度。在另一个实施例中，一个有序的纳米尺寸图案在垂直于电流的方向上定向，而另一个有序的纳米尺寸图案在平行于电流的方向上取向。在这样的实施例中，提供具有长沟道长度和宽沟道宽度的FET。

6. 发明申请

US20090121261A1 STRUCTURE AND METHOD FOR COMPACT LONG-CHANNEL FETs 失效
标题翻译：紧凑型长沟道FET的结构和方法
公开(公告)号：US20090121261A1
公开(公告)日：2009-05-14
申请号：US11937161
申请日：2007-11-08
申请人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper
发明人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/1037 , H01L29/6659 , H01L29/66621
摘要： A compact semiconductor structure including at least one FET located upon and within a surface of a semiconductor substrate in which the at least one FET includes a long channel length and/or a wide channel width and a method of fabricating the same are provided. In some embodiments, the ordered, nanosized pattern is oriented in a direction that is perpendicular to the current flow. In such an embodiment, the FET has a long channel length. In other embodiments, the ordered, nanosized pattern is oriented in a direction that is parallel to that of the current flow. In such an embodiment, the FET has a wide channel width. In yet another embodiment, one ordered, nanosized pattern is oriented in a direction perpendicular to the current flow, while another ordered, nanosized pattern is oriented in a direction parallel to the current flow. In such an embodiment, a FET having a long channel length and wide channel width is provided.
摘要翻译：一种紧凑的半导体结构，其包括至少一个位于半导体衬底的表面之上和之中的FET，其中所述至少一个FET包括长沟道长度和/或宽沟道宽度及其制造方法。在一些实施例中，有序的纳米尺寸图案在垂直于电流的方向上取向。在这样的实施例中，FET具有长的沟道长度。在其他实施例中，有序的纳米尺寸图案在平行于电流流动的方向上取向。在这样的实施例中，FET具有宽的通道宽度。在另一个实施例中，一个有序的纳米尺寸图案在垂直于电流的方向上定向，而另一个有序的纳米尺寸图案在平行于电流的方向上取向。在这样的实施例中，提供具有长沟道长度和宽沟道宽度的FET。

7. 发明授权

US08685809B2 Semiconductor structures having improved contact resistance 有权
标题翻译：具有改善的接触电阻的半导体结构
公开(公告)号：US08685809B2
公开(公告)日：2014-04-01
申请号：US13454709
申请日：2012-04-24
申请人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper , Jay W. Strane
发明人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper , Jay W. Strane
IPC分类号： H01L21/336
CPC分类号： H01L21/28518 , B81B2207/07 , B81C1/00095 , B81C2201/0149 , H01L21/3086 , H01L21/76886 , H01L23/485 , H01L23/5226 , H01L29/41766 , H01L29/665 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.
摘要翻译：自组装聚合物技术用于在存在于半导体结构的导电接触区域中的材料内形成至少一个有序的纳米尺度图案。具有有序纳米尺寸图案的材料是场效应晶体管的互连结构或半导体源和漏极扩散区的导电材料。在接触区域内有序的纳米尺寸图案材料的存在增加了用于随后的接触形成的总面积（即界面面积），这又降低了结构的接触电阻。接触电阻的降低又改善了通过结构的电流的流动。除了上述之外，本发明的方法和结构不影响结构的结电容，因为结面积保持不变。

8. 发明授权

US08487355B2 Structure and method for compact long-channel FETs 失效
标题翻译：紧凑型长沟道FET的结构和方法
公开(公告)号：US08487355B2
公开(公告)日：2013-07-16
申请号：US13223940
申请日：2011-09-01
申请人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper
发明人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/1037 , H01L29/6659 , H01L29/66621
摘要： A compact semiconductor structure including at least one FET located upon and within a surface of a semiconductor substrate in which the at least one FET includes a long channel length and/or a wide channel width and a method of fabricating the same are provided. In some embodiments, the ordered, nanosized pattern is oriented in a direction that is perpendicular to the current flow. In such an embodiment, the FET has a long channel length. In other embodiments, the ordered, nanosized pattern is oriented in a direction that is parallel to that of the current flow. In such an embodiment, the FET has a wide channel width. In yet another embodiment, one ordered, nanosized pattern is oriented in a direction perpendicular to the current flow, while another ordered, nanosized pattern is oriented in a direction parallel to the current flow. In such an embodiment, a FET having a long channel length and wide channel width is provided.
摘要翻译：一种紧凑的半导体结构，其包括至少一个位于半导体衬底的表面之上和之中的FET，其中所述至少一个FET包括长沟道长度和/或宽沟道宽度及其制造方法。在一些实施例中，有序的纳米尺寸图案在垂直于电流的方向上取向。在这样的实施例中，FET具有长的沟道长度。在其他实施例中，有序的纳米尺寸图案在平行于电流流动的方向上取向。在这样的实施例中，FET具有宽的通道宽度。在另一个实施例中，一个有序的纳米尺寸图案在垂直于电流的方向上定向，而另一个有序的纳米尺寸图案在平行于电流的方向上取向。在这样的实施例中，提供具有长沟道长度和宽沟道宽度的FET。

9. 发明授权

US09058455B2 Backside integration of RF filters for RF front end modules and design structure 有权
标题翻译：用于RF前端模块的RF滤波器的背面集成和设计结构
公开(公告)号：US09058455B2
公开(公告)日：2015-06-16
申请号：US13354705
申请日：2012-01-20
申请人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
发明人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
IPC分类号： G06F17/50 , H01L21/768 , H01L23/48 , H03H9/64 , H01L23/00 , H01L27/06 , H01L49/02 , H01L23/66 , H01L25/16
CPC分类号： H01L41/293 , G06F17/5063 , G06F17/5068 , H01L21/76898 , H01L23/481 , H01L23/66 , H01L24/03 , H01L24/05 , H01L24/24 , H01L25/16 , H01L27/0694 , H01L28/40 , H01L41/0815 , H01L41/25 , H01L2224/03009 , H01L2224/0401 , H01L2224/04105 , H01L2224/0557 , H01L2224/05572 , H01L2224/06181 , H01L2224/12105 , H01L2224/14181 , H01L2224/16145 , H01L2224/24145 , H01L2225/06548 , H03H9/64
摘要： A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.
摘要翻译：在半导体衬底的背面上的集成射频（RF）滤波器的设计结构包括：在衬底的第一侧上的器件; 在衬底的背面上的射频（RF）滤波器; 以及至少一个衬底导体，其从所述衬底的前侧延伸到所述衬底的所述背面并将所述RF滤波器电耦合到所述器件。

10. 发明授权

US08973250B2 Methods of manufacturing a micro-electro-mechanical system (MEMS) structure 有权
标题翻译：制造微电子机械系统（MEMS）结构的方法
公开(公告)号：US08973250B2
公开(公告)日：2015-03-10
申请号：US13164323
申请日：2011-06-20
申请人： Christopher V. Jahnes , Anthony K. Stamper
发明人： Christopher V. Jahnes , Anthony K. Stamper
IPC分类号： H04R31/00 , B81B3/00 , B81C1/00 , B81B7/00 , H01L41/113 , H01L41/09
CPC分类号： B81B3/001 , B81B3/0021 , B81B3/0059 , B81B3/0072 , B81B7/0006 , B81B7/008 , B81B2201/016 , B81B2203/0163 , B81C1/00015 , B81C1/0015 , B81C1/00476 , G06F17/5045 , H01L41/094 , H01L41/1134 , H01L41/1138 , Y10T29/49002 , Y10T29/49005 , Y10T29/4908 , Y10T29/49121
摘要： Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are provided. The method of forming a MEMS structure includes forming a wiring layer on a substrate comprising actuator electrodes and a contact electrode. The method further includes forming a MEMS beam above the wiring layer. The method further includes forming at least one spring attached to at least one end of the MEMS beam. The method further includes forming an array of mini-bumps between the wiring layer and the MEMS beam.
摘要翻译：提供微机电系统（MEMS）结构，制造方法和设计结构。形成MEMS结构的方法包括在包括致动器电极和接触电极的基板上形成布线层。该方法还包括在布线层上方形成MEMS光束。该方法还包括形成至少一个连接到MEMS梁的至少一端的弹簧。该方法还包括在布线层和MEMS光束之间形成微小凸块的阵列。

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