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1. 发明授权

US09898177B2 Display processing method and portable mobile terminal 有权
公开(公告)号：US09898177B2
公开(公告)日：2018-02-20
申请号：US13824832
申请日：2011-09-21
申请人： Geng Wang , Ran Sun
发明人： Geng Wang , Ran Sun
IPC分类号： G06F3/00 , G06F3/0484 , G06F3/0482 , G06F3/0488
CPC分类号： G06F3/04845 , G06F3/0482 , G06F3/04842 , G06F3/04883 , G06F2203/04104
摘要： A display processing method that is applied in a portable mobile terminal, to display multiple objects on a touch screen of the portable mobile terminal. The method includes obtaining a touch point that is a point created when an operating object contacts/almost touches the touch screen; determining a preset area with the touch point being the center; determining a first object and a second object, among multiple objects, each intersecting with the preset area on at least one point; determining a first information of the movement of the first object, the first information indicating moving the first object from a first position to a second position, the first position being the original position of the first object displayed on the touch screen; and moving the first object from the first position to the second position according to the first information.

2. 发明申请

US20160188178A1 Display Processing Method And Portable Mobile Terminal 有权
标题翻译：显示处理方法和便携式移动终端
公开(公告)号：US20160188178A1
公开(公告)日：2016-06-30
申请号：US13824832
申请日：2011-09-21
申请人： Geng Wang , Ran Sun
发明人： Geng Wang , Ran Sun
IPC分类号： G06F3/0484 , G06T7/00 , G06F3/0482 , G06F3/0488
CPC分类号： G06F3/04845 , G06F3/0482 , G06F3/04842 , G06F3/04883 , G06F2203/04104
摘要： A display processing method that is applied in a portable mobile terminal, to display multiple objects on a touch screen of the portable mobile terminal. The method includes obtaining a touch point that is a point created when an operating object contacts/almost touches the touch screen; determining a preset area with the touch point being the center; determining a first object and a second object, among multiple objects, each intersecting with the preset area on at least one point; determining a first information of the movement of the first object, the first information indicating moving the first object from a first position to a second position, the first position being the original position of the first object displayed on the touch screen; and moving the first object from the first position to the second position according to the first information.
摘要翻译：一种应用于便携式移动终端中的显示处理方法，用于在便携式移动终端的触摸屏上显示多个对象。该方法包括获得触摸点，该触摸点是当操作对象接触/几乎触摸触摸屏时创建的点; 以触摸点为中心确定预设区域; 确定在多个对象中的第一对象和第二对象，每个对象至少在一个点上与预设区域相交; 确定所述第一对象的移动的第一信息，所述第一信息指示将所述第一对象从第一位置移动到第二位置，所述第一位置是在所述触摸屏上显示的所述第一对象的原始位置; 以及根据第一信息将第一物体从第一位置移动到第二位置。

3. 发明授权

US09076817B2 Epitaxial extension CMOS transistor 有权
标题翻译：外延扩展CMOS晶体管
公开(公告)号：US09076817B2
公开(公告)日：2015-07-07
申请号：US13198152
申请日：2011-08-04
申请人： Chengwen Pei , Geng Wang , Yanli Zhang
发明人： Chengwen Pei , Geng Wang , Yanli Zhang
IPC分类号： H01L29/66 , H01L29/51
CPC分类号： H01L29/6656 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/66628 , H01L29/66636
摘要： A pair of horizontal-step-including trenches are formed in a semiconductor layer by forming a pair of first trenches having a first depth around a gate structure on the semiconductor layer, forming a disposable spacer around the gate structure to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth greater than the first depth. The disposable spacer is removed, and selective epitaxy is performed to form an integrated epitaxial source and source extension region and an integrated epitaxial drain and drain extension region. A replacement gate structure can be formed after deposition and planarization of a planarization dielectric layer and subsequent removal of the gate structure and laterally expand the gate cavity over expitaxial source and drain extension regions. Alternately, a contact-level dielectric layer can be deposited directly on the integrated epitaxial regions and contact via structures can be formed therein.
摘要翻译：通过在半导体层上形成围绕栅极结构的第一深度的一对第一沟槽，在半导体层中形成一对水平台阶包含的沟槽，在栅极结构周围形成一次性间隔物，以覆盖第一并且通过形成大于第一深度的第二深度的一对第二沟槽。去除一次性间隔物，并进行选择性外延以形成集成的外延源和源极延伸区域以及集成的外延漏极和漏极延伸区域。可以在平坦化介电层的沉积和平坦化之后形成替代栅极结构，并且随后去除栅极结构并且在外延源极和漏极延伸区域上横向扩展栅极腔。或者，可以将接触电介质层直接沉积在集成的外延区上，并且可以在其中形成接触通孔结构。

4. 发明授权

US08691697B2 Self-aligned devices and methods of manufacture 失效
标题翻译：自对准装置和制造方法
公开(公告)号：US08691697B2
公开(公告)日：2014-04-08
申请号：US12943956
申请日：2010-11-11
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/302 , B44C1/22
CPC分类号： H01L21/31056 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： A method includes forming patterned lines on a substrate having a predetermined pitch. The method further includes forming spacer sidewalls on sidewalls of the patterned lines. The method further includes forming material in a space between the spacer sidewalls of adjacent patterned lines. The method further includes forming another patterned line from the material by protecting the material in the space between the spacer sidewalls of adjacent patterned lines while removing the spacer sidewalls. The method further includes transferring a pattern of the patterned lines and the another patterned line to the substrate.
摘要翻译：一种方法包括在具有预定间距的基底上形成图案线。该方法还包括在图案化线的侧壁上形成间隔壁。该方法还包括在相邻图案线的间隔壁侧壁之间的空间中形成材料。该方法还包括通过在相邻图案化线的间隔壁侧壁之间的空间中保护材料同时去除间隔壁侧壁而从该材料形成另一图案化线。该方法还包括将图案化线和另一图案化线的图案转移到衬底。

5. 发明授权

US08637958B2 Structure and method for forming isolation and buried plate for trench capacitor 有权
标题翻译：用于形成沟槽电容器的隔离和掩埋板的结构和方法
公开(公告)号：US08637958B2
公开(公告)日：2014-01-28
申请号：US13617576
申请日：2012-09-14
申请人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi Todi , Geng Wang
发明人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi Todi , Geng Wang
IPC分类号： H01L21/02
CPC分类号： H01L29/945 , H01L21/76229 , H01L21/84 , H01L29/66181
摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.
摘要翻译：公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区。该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

6. 发明授权

US08575670B2 Embedded dynamic random access memory device formed in an extremely thin semiconductor on insulator (ETSOI) substrate 有权
标题翻译：在非常薄的半导体绝缘体（ETSOI）衬底上形成的嵌入式动态随机存取存储器件
公开(公告)号：US08575670B2
公开(公告)日：2013-11-05
申请号：US13316056
申请日：2011-12-09
申请人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L27/10861 , H01L28/91 , H01L29/945
摘要： A memory device including an SOI substrate with a buried dielectric layer having a thickness of less than 30 nm, and a trench extending through an SOI layer and the buried dielectric layer into the base semiconductor layer of the SOI substrate. A capacitor is present in a lower portion of the trench. A dielectric spacer is present on the sidewalls of an upper portion of the trench. The dielectric spacer is present on the portions of the trench where the sidewalls are provided by the SOI layer and the buried dielectric layer. A conductive material fill is present in the upper portion of the trench. A semiconductor device is present on the SOI layer that is adjacent to the trench. The semiconductor device is in electrical communication with the capacitor through the conductive material fill.
摘要翻译：一种存储器件，包括具有厚度小于30nm的掩埋介电层的SOI衬底，以及穿过SOI层的延伸沟槽和埋入电介质层到SOI衬底的基底半导体层中的沟槽。电容器存在于沟槽的下部。电介质垫片存在于沟槽上部的侧壁上。介质间隔物存在于沟槽的部分，其中侧壁由SOI层和埋入的介电层提供。导电材料填充物存在于沟槽的上部。半导体器件存在于与沟槽相邻的SOI层上。半导体器件通过导电材料填充与电容器电连通。

7. 发明授权

US08536649B2 Method to reduce threshold voltage variability with through gate well implant 失效
标题翻译：通过栅极井注入降低阈值电压变化的方法
公开(公告)号：US08536649B2
公开(公告)日：2013-09-17
申请号：US13608860
申请日：2012-09-10
申请人： Geng Wang , Joseph Ervin , Jeffrey B. Johnson , Paul C. Parries
发明人： Geng Wang , Joseph Ervin , Jeffrey B. Johnson , Paul C. Parries
IPC分类号： H01L29/66
CPC分类号： H01L29/66772 , H01L21/2652 , H01L29/78696
摘要： The present disclosure provides a semiconductor device that may include a substrate including a semiconductor layer overlying an insulating layer. A gate structure that is present on a channel portion of the semiconductor layer. A first dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the first dopant region is present within the lower portion of the gate conductor and the upper portion of the semiconductor layer. A second dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the second dopant region is present within the lower portion of the semiconductor layer.
摘要翻译：本公开提供了一种半导体器件，其可以包括包括覆盖绝缘层的半导体层的衬底。存在于半导体层的沟道部分上的栅极结构。第一掺杂区存在于半导体层的沟道部分中，其中第一掺杂区的峰值浓度存在于栅极导体的下部和半导体层的上部之间。第二掺杂剂区域存在于半导体层的沟道部分中，其中第二掺杂剂区域的峰值浓度存在于半导体层的下部。

8. 发明授权

US08507915B2 Low resistance embedded strap for a trench capacitor 有权
公开(公告)号：US08507915B2
公开(公告)日：2013-08-13
申请号：US13307787
申请日：2011-11-30
申请人： Karen A. Nummy , Chengwen Pei , Werner A. Rausch , Geng Wang
发明人： Karen A. Nummy , Chengwen Pei , Werner A. Rausch , Geng Wang
IPC分类号： H01L29/94
CPC分类号： H01L21/4846 , H01L21/82 , H01L27/10867 , H01L29/66181 , H01L29/66636 , H01L29/945
摘要： A trench is formed in a semiconductor substrate, and is filled with a node dielectric layer and at least one conductive material fill portion that functions as an inner electrode. The at least one conductive material fill portion includes a doped polycrystalline semiconductor fill portion. A gate stack for an access transistor is formed on the semiconductor substrate, and a gate spacer is formed around the gate stack. A source/drain trench is formed between an outer sidewall of the gate spacer and a sidewall of the doped polycrystalline semiconductor fill portion. An epitaxial source region and a polycrystalline semiconductor material portion are simultaneously formed by a selective epitaxy process such that the epitaxial source region and the polycrystalline semiconductor material portion contact each other without a gap therebetween. The polycrystalline semiconductor material portion provides a robust low resistance conductive path between the source region and the inner electrode.

9. 发明授权

US08372721B2 Work function engineering for eDRAM MOSFETs 有权
标题翻译： eDRAM MOSFET的工作功能工程
公开(公告)号：US08372721B2
公开(公告)日：2013-02-12
申请号：US13343850
申请日：2012-01-05
申请人： Xiangdong Chen , Herbert L. Ho , Geng Wang
发明人： Xiangdong Chen , Herbert L. Ho , Geng Wang
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/10894 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： Embedded DRAM MOSFETs including an array NFET having a gate stack comprising a high-K dielectric layer upon which is deposited a first metal oxide layer (CD1) then a conductive layer (TiN), and then a polysilicon layer (Poly). A logic PFET having substantially the same gate stack as the array NFET, and a logic NFET having a third gate stack comprising the high-K dielectric layer upon which is deposited the conductive layer (TiN) and then the polysilicon layer (Poly), without the first metal oxide layer (CD1) between the high-K dielectric layer and the conductive layer (TiN). The array NFET may therefore have a higher gate stack work function than the logic NFET, but substantially the same gate stack work function as the logic PFET.
摘要翻译：嵌入式DRAM MOSFET包括阵列NFET，其具有包括高K电介质层的栅极堆叠，在其上沉积第一金属氧化物层（CD1），然后沉积导电层（TiN），然后沉积多晶硅层（Poly）。具有与阵列NFET基本相同的栅极叠层的逻辑PFET，以及具有第三栅极堆叠的逻辑NFET，其包括高K电介质层，在其上沉积导电层（TiN），然后沉积多晶硅层（Poly）高K电介质层与导电层（TiN）之间的第一金属氧化物层（CD1）。因此，阵列NFET可以具有比逻辑NFET更高的栅极堆叠功函数，但是与逻辑PFET基本上相同的栅极堆叠功能。

10. 发明申请

US20130032868A1 TRENCH CAPACITOR WITH SPACER-LESS FABRICATION PROCESS 失效
标题翻译：具有无间隙制造工艺的TRENCH电容器
公开(公告)号：US20130032868A1
公开(公告)日：2013-02-07
申请号：US13198100
申请日：2011-08-04
申请人： Chengwen Pei , Xi Li , Geng Wang
发明人： Chengwen Pei , Xi Li , Geng Wang
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L29/0692 , H01L21/3081 , H01L21/3086 , H01L21/84 , H01L27/1087 , H01L27/1203 , H01L29/66181 , H01L29/945
摘要： A trench capacitor and method of fabrication are disclosed. The SOI region is doped such that a selective isotropic etch used for trench widening does not cause appreciable pullback of the SOI region, and no spacers are needed in the upper portion of the trench.
摘要翻译：公开了一种沟槽电容器和制造方法。掺杂SOI区域使得用于沟槽加宽的选择性各向同性蚀刻不会导致SOI区域的明显的回退，并且在沟槽的上部不需要间隔物。

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