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1. 发明申请

WO2007125366A2 DIGITAL-TO-ANALOGUE CONVERTERS 审中-公开
标题翻译：数字到模拟转换器
公开(公告)号：WO2007125366A2
公开(公告)日：2007-11-08
申请号：PCT/GB2007050217
申请日：2007-04-26
申请人： ARTIMI INC , CARROLL BRIAN STEPHEN
发明人： CARROLL BRIAN STEPHEN
IPC分类号： H03M5/18 , H03M1/68 , H03M7/06 , H04L25/49
CPC分类号： H04L25/4925 , H03M1/745 , H04L27/2626
摘要： Digital-to-Analogue Converters This invention generally relates to digital-to-analogue converters (DACs). More particularly it relates to differential, current-steering DACs with reduced small signal differential non-linearity. A differential current-steering digital-to-analogue converter (DAC), the DAC comprising: a digital input to receive a binary code comprising a plurality of bits defining a signed digital value for conversion into a signed differential analogue output signal; a pair of differential analogue output lines to provide said differential analogue output; and a set of binary-weighted steerable substantially constant current generators each coupled to said differential output lines and having a control input to receive a signal derived from said digital input to control current steering to said differential output lines responsive to said binary input code; wherein a said steerable substantially constant current generator comprises a ternary substantially constant current generator configured to generate a three-state differential current in response to a ternary signal on said control input; wherein each of said ternary current generators is associated with a bit of said binary code; and wherein said DAC further comprises a code converter coupled between said DAC digital input and said control inputs of said steerable current generators to convert said binary input code to a ternary code to control said steerable current generators.
摘要翻译：数模转换器本发明一般涉及数模转换器（DAC）。更具体地说，它涉及具有减小的小信号差分非线性的差分，电流导向DAC。一种差分电流转向数模转换器（DAC），该DAC包括：数字输入端，用于接收包含多个位的二进制码，该位定义用于转换为有符号差分模拟输出信号的带符号数字值; 一对差分模拟输出线，用于提供所述差分模拟输出; 以及一组二进制加权的可操作的恒定恒定电流发生器，每一个都耦合到所述差分输出线并具有一个控制输入端，用于接收从所述数字输入端导出的信号，以响应于所述二进制输入码来控制对所述差分输出线路的电流转向; 其特征在于，一个所述可操纵的基本恒定的电流发生器包括三元基本上恒定的电流发生器，其被配置为响应于所述控制输入上的三进制信号产生三态差动电流; 其中每个所述三进制电流发生器与所述二进制码的位相关联; 并且其中所述DAC还包括耦合在所述DAC数字输入和所述可控电流发生器的所述控制输入之间的代码转换器，以将所述二进制输入代码转换为三进制代码以控制所述可转向电流发生器。

2. 发明申请

WO2007125366A3 DIGITAL-TO-ANALOGUE CONVERTERS 审中-公开
公开(公告)号：WO2007125366A3
公开(公告)日：2007-11-08
申请号：PCT/GB2007/050217
申请日：2007-04-26
申请人： ARTIMI INC , CARROLL, Brian Stephen
发明人： CARROLL, Brian Stephen
IPC分类号： H03M5/18 , H03M7/06 , H04L25/49 , H03M1/68
摘要： Digital-to-Analogue Converters This invention generally relates to digital-to-analogue converters (DACs). More particularly it relates to differential, current-steering DACs with reduced small signal differential non-linearity. A differential current-steering digital-to-analogue converter (DAC), the DAC comprising: a digital input to receive a binary code comprising a plurality of bits defining a signed digital value for conversion into a signed differential analogue output signal; a pair of differential analogue output lines to provide said differential analogue output; and a set of binary-weighted steerable substantially constant current generators each coupled to said differential output lines and having a control input to receive a signal derived from said digital input to control current steering to said differential output lines responsive to said binary input code; wherein a said steerable substantially constant current generator comprises a ternary substantially constant current generator configured to generate a three-state differential current in response to a ternary signal on said control input; wherein each of said ternary current generators is associated with a bit of said binary code; and wherein said DAC further comprises a code converter coupled between said DAC digital input and said control inputs of said steerable current generators to convert said binary input code to a ternary code to control said steerable current generators.

3. 发明申请

WO2018161153A1 MODULATION FOR A DATA BIT STREAM 审中-公开
公开(公告)号：WO2018161153A1
公开(公告)日：2018-09-13
申请号：PCT/CA2018/050218
申请日：2018-02-26
申请人： BLACKBERRY LIMITED
发明人： QU, Shouxing
IPC分类号： H03M5/18 , H04L27/02
摘要： In some examples, a binary bit stream of input bits is encoded into a three-amplitude bipolar symbol stream of symbols, the encoding using a coding rule that specifies setting a value of a respective symbol of the symbol stream based on a respective input bit of the binary bit stream and a prior input bit of the binary bit stream that is prior to the respective input bit, the coding rule further specifying that adjacent non-zero pulses keep the same polarity. A radio frequency (RF) carrier signal is modulated using the symbol stream to produce a modulated RF signal.

4. 发明申请

WO98044635A1 DUOBINARY CODING AND MODULATION TECHNIQUE FOR OPTICAL COMMUNICATION SYSTEMS 审中-公开
标题翻译：光通信系统的移动编码和调制技术
公开(公告)号：WO98044635A1
公开(公告)日：1998-10-08
申请号：PCT/CA1998/000275
申请日：1998-03-25
IPC分类号： G02F1/01 , H03M5/16 , H03M5/18 , H04B10/00 , H04B10/04 , H04B10/06 , H04B10/142 , H04B10/152 , H04B10/155 , H04L25/497 , G02F1/225
CPC分类号： H04B10/5055 , H03M5/18 , H04B10/505 , H04B10/5167
摘要： A method for encoding a binary input sequence x(0,1) to obtain a duobinary output sequence y(+1,0,-1) is provided. The duobinary coding technique always provides an output bit yk =0 when the corresponding bit xk =0; bits yk alternatively assume a logical level "+1" and "-1" whenever an input bit xk-1=0 changes to xk=1, and the output bit yk maintains the logical level "+1" or "-1" whenever the corresponding bit xk maintains the logical level "1". A coding device for encoding a binary input sequence x(0,1) to a duobinary output sequence y(+1,0,-1) is also provided, comprising a D-type flip-flop for generating a binary switch signal. A first AND circuit receives the input sequence and the switch signal, and provides a first binary sequence a(0,1), while a second AND circuit receives the input sequence and the complement of the switch signal and provides a second binary sequence b(0,1). These first and second binary sequences are applied to a summer to obtain the output sequence y(+1,0,-1). A method for differentially driving an M-Z modulator using a virtual ground level is also provided, which reduces the peak-to-peak drive voltage by a factor of two.
摘要翻译：提供了一种用于对二进制输入序列x（0,1）进行编码以获得双二进制输出序列y（+ 1,0，-1）的方法。当对应的位xk = 0时，双向编码技术总是提供输出位yk = 0; 只要输入位xk-1 = 0改变为xk = 1，位yk或者假设逻辑电平“+1”和“-1”，并且输出位yk每当维持逻辑电平“+1”或“-1” 对应的位xk保持逻辑电平“1”。还提供了用于将二进制输入序列x（0,1）编码到双二进制输出序列y（+ 1,0，-1）的编码装置，包括用于产生二进制开关信号的D型触发器。第一AND电路接收输入序列和开关信号，并提供第一二进制序列a（0,1），而第二AND电路接收输入序列和开关信号的补码，并提供第二二进制序列b（ 0,1）。将这些第一和第二二进制序列应用于加法器以获得输出序列y（+ 1,0，-1）。还提供了一种用于使用虚拟接地电平差分驱动M-Z调制器的方法，其将峰 - 峰驱动电压降低了二倍。

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