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    • 2. 发明申请
    • TRI-VALUE DECODER CIRCUIT AND METHOD
    • 三值解码器电路和方法
    • WO2005119919A2
    • 2005-12-15
    • PCT/US2005019831
    • 2005-06-06
    • TEXAS INSTRUMENTS INCSTULIK PAULCHEUNG HUGO
    • STULIK PAULCHEUNG HUGO
    • H03M1/36H03M1/38H03M7/00H03M7/06
    • H03M1/38H03M7/06
    • A tri-value decoder and method for decoding at least three states of an input signal are provided. An exemplary tri-value decoder and method can facilitate decoding of input signals without the use of threshold values and/or forcing a tri-state input signal to a mid-rail value for tri-state detection, and with less dependence on variations in product, process and temperature. An exemplary tri-value decoder circuit comprises a switch circuit 402, a feedback loop 404 and a sequence detector 406. Switch circuit 402 includes a pull-up switch MP and a pull-down switch MN, with optional current-limiting resistors, controlled by an output Q of a flip-flop 408 of feedback loop 404 to provide a sampled sequence of the tri-state input signal to the sequence detector 406. Sequence detector 406 decodes the tri-state input signal into a two-bit digital signal by detecting at least two samples of the tri-state input signal during a sampling period.
    • 提供了三值解码器和用于解码输入信号的至少三种状态的方法。 示例性三值解码器和方法可以有助于解码输入信号而不使用阈值和/或强制三态输入信号到三态检测的中间轨值,并且对产品变化的依赖性较小 ,工艺和温度。 示例性三值解码器电路包括开关电路402,反馈环路404和序列检测器406.开关电路402包括上拉开关MP和下拉开关MN,其中可选的限流电阻由 反馈回路404的触发器408的输出Q,以向该序列检测器406提供三态输入信号的采样序列。序列检测器406通过检测将三态输入信号解码为2位数字信号 在采样周期内,三态输入信号的至少两个样本。