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1. 发明申请

WO2009132013A1 PROGRAMMABLE STREAMING PROCESSOR WITH MIXED PRECISION INSTRUCTION EXECUTION 审中-公开
标题翻译：具有混合精度指令执行的可编程流水处理器
公开(公告)号：WO2009132013A1
公开(公告)日：2009-10-29
申请号：PCT/US2009/041268
申请日：2009-04-21
申请人： QUALCOMM INCORPORATED , DU, Yun , YU, Chun , JIAO, Guofang , MOLLOY, Stephen
发明人： DU, Yun , YU, Chun , JIAO, Guofang , MOLLOY, Stephen
IPC分类号： G06T15/00 , G06F1/32
CPC分类号： G06T15/005 , G06F8/47
摘要： The disclosure relates to a programmable streaming processor that is capable of executing mixed-precision (e.g., full-precision, half-precision) instructions using different execution units. The various execution units are each capable of using graphics data to execute instructions at a particular precision level. An exemplary programmable shader processor includes a controller and multiple execution units. The controller is configured to receive an instruction for execution and to receive an indication of a data precision for execution of the instruction. The controller is also configured to receive a separate conversion instruction that, when executed, converts graphics data associated with the instruction to the indicated data precision. When operable, the controller selects one of the execution units based on the indicated data precision. The controller then causes the selected execution unit to execute the instruction with the indicated data precision using the graphics data associated with the instruction.
摘要翻译：本公开涉及一种能够使用不同的执行单元执行混合精度（例如，全精度，半精度）指令的可编程流处理器。各种执行单元都能够使用图形数据来执行特定精度级别的指令。示例性可编程着色器处理器包括控制器和多个执行单元。控制器被配置为接收用于执行的指令并且接收用于执行指令的数据精度的指示。控制器还被配置为接收单独的转换指令，该指令在执行时将与指令相关联的图形数据转换为所指示的数据精度。当可操作时，控制器基于指示的数据精度选择一个执行单元。然后，控制器使所选择的执行单元使用与指令相关联的图形数据，以指示的数据精度执行指令。

2. 发明申请

WO2008039950A1 GRAPHICS PROCESSING UNIT WITH UNIFIED VERTEX CACHE AND SHADER REGISTER FILE 审中-公开
标题翻译：具有统一VERTEX CACHE和SHADER寄存器文件的图形处理单元
公开(公告)号：WO2008039950A1
公开(公告)日：2008-04-03
申请号：PCT/US2007/079784
申请日：2007-09-27
申请人： QUALCOMM Incorporated , JIAO, Guofang , YU, Chun , DU, Yun
发明人： JIAO, Guofang , YU, Chun , DU, Yun
IPC分类号： G06T15/00
CPC分类号： G06T15/005
摘要： Techniques are described for processing computerized images with a graphics processing unit (GPU) using a unified vertex cache and shader register file. The techniques include creating a shared shader coupled to the GPU pipeline and a unified vertex cache and shader register file coupled to the shared shader to substantially eliminate data movement within the GPU pipeline. The GPU pipeline sends image geometry information based on an image geometry for an image to the shared shader. The shared shader performs vertex shading to generate vertex coordinates and attributes of vertices in the image. The shared shader then stores the vertex attributes in the unified vertex cache and shader register file, and sends only the vertex coordinates of the vertices back to the GPU pipeline. The GPU pipeline processes the image based on the vertex coordinates, and the shared shader processes the image based on the vertex attributes.
摘要翻译：描述了使用统一的顶点高速缓存和着色器寄存器文件处理具有图形处理单元（GPU）的计算机化图像的技术。这些技术包括创建耦合到GPU流水线的共享着色器和耦合到共享着色器的统一顶点高速缓存和着色器寄存器文件，以基本上消除GPU流水线内的数据移动。 GPU管道将基于图像的图像几何的图像几何信息发送到共享着色器。共享着色器执行顶点着色以生成图像中顶点坐标和顶点属性。共享着色器然后将顶点属性存储在统一的顶点缓存和着色器寄存器文件中，并且仅将顶点的顶点坐标发送回GPU管道。 GPU流水线基于顶点坐标处理图像，共享着色器基于顶点属性处理图像。

3. 发明申请

WO2007140338A2 GRAPHICS PROCESSOR WITH ARITHMETIC AND ELEMENTARY FUNCTION UNITS 审中-公开
标题翻译：具有算术和元素功能单元的图形处理器
公开(公告)号：WO2007140338A2
公开(公告)日：2007-12-06
申请号：PCT/US2007/069803
申请日：2007-05-25
申请人： QUALCOMM Incorporated , BOURD, Alexei, V. , DU, Yun , YU, Chun , JIAO, Guofang
发明人： BOURD, Alexei, V. , DU, Yun , YU, Chun , JIAO, Guofang
IPC分类号： G06F9/38
CPC分类号： G06T1/20 , G06F9/30167 , G06F9/383 , G06F9/3851 , G06F9/3885
摘要： A graphics processor capable of efficiently performing arithmetic operations and computing elementary functions is described. The graphics processor has at least one arithmetic logic unit (ALU) that can perform arithmetic operations and at least one elementary function unit that can compute elementary functions. The ALU(s) and elementary function unit(s) may be arranged such that they can operate in parallel to improve throughput. The graphics processor may also include fewer elementary function units than ALUs, e.g., four ALUs and a single elementary function unit. The four ALUs may perform an arithmetic operation on (1) four components of an attribute for one pixel or (2) one component of an attribute for four pixels. The single elementary function unit may operate on one component of one pixel at a time. The use of a single elementary function unit may reduce cost while still providing good performance.
摘要翻译：描述能够有效执行算术运算和计算基本功能的图形处理器。图形处理器具有至少一个可执行算术运算的算术逻辑单元（ALU）和至少一个可以计算基本功能的基本功能单元。 ALU和基本功能单元可以被布置成使得它们可以并行操作以提高吞吐量。图形处理器还可以包括比ALU更少的基本功能单元，例如四个ALU和单个基本功能单元。四个ALU可以对（1）四个像素的属性的四个分量或（2）四个像素的属性的一个分量执行算术运算。单个基本功能单元可以一次操作一个像素的一个分量。使用单个基本功能单元可以降低成本，同时仍然提供良好的性能。

4. 发明申请

WO2008101210A2 EFFICIENT 2-D AND 3-D GRAPHICS PROCESSING 审中-公开
标题翻译：有效的二维和三维图形处理
公开(公告)号：WO2008101210A2
公开(公告)日：2008-08-21
申请号：PCT/US2008/054162
申请日：2008-02-15
申请人： QUALCOMM Incorporated , JIAO, Guofang , DORBIE, Angus M. , YUN, Jay C. , DU, Yun , YU, Chun
发明人： JIAO, Guofang , DORBIE, Angus M. , YUN, Jay C. , DU, Yun , YU, Chun
IPC分类号： G06T15/00
CPC分类号： G06T15/005 , G06T11/40 , G09G5/363
摘要： Techniques for supporting both 2-D and 3-D graphics are described. A graphics processing unit (GPU) may perform 3-D graphics processing in accordance with a 3-D graphics pipeline to render 3-D images and may also perform 2-D graphics processing in accordance with a 2-D graphics pipeline to render 2-D images. Each stage of the 2-D graphics pipeline may be mapped to at least one stage of the 3-D graphics pipeline. For example, a clipping, masking and scissoring stage in 2-D graphics may be mapped to a depth test stage in 3-D graphics. Coverage values for pixels within paths in 2-D graphics may be determined using rasterization and depth test stages in 3-D graphics. A paint generation stage and an image interpolation stage in 2-D graphics may be mapped to a fragment shader stage in 3-D graphics. A blending stage in 2-D graphics may be mapped to a blending stage in 3-D graphics.
摘要翻译：描述了支持2-D和3-D图形的技术。图形处理单元（GPU）可以根据3-D图形流水线执行3D图形处理以渲染3-D图像，并且还可以根据2-D图形流水线执行2-D图形处理以呈现2 -D图像。 2-D图形管线的每个阶段可以映射到3-D图形流水线的至少一个阶段。例如，2-D图形中的裁剪，掩蔽和裁剪阶段可能被映射到3-D图形中的深度测试阶段。 2-D图形中路径内像素的覆盖值可以使用3-D图形中的光栅化和深度测试阶段来确定。 2-D图形中的油漆生成阶段和图像插值阶段可以映射到3-D图形中的片段着色器阶段。 2-D图形中的混合阶段可以映射到3-D图形的混合阶段。

5. 发明申请

WO2008049110A2 PROGRAMMABLE BLENDING IN A GRAPHICS PROCESSING UNIT 审中-公开
标题翻译：图形处理单元中的可编程混合
公开(公告)号：WO2008049110A2
公开(公告)日：2008-04-24
申请号：PCT/US2007/081952
申请日：2007-10-19
申请人： QUALCOMM Incorporated , JIAO, Guofang , YU, Chun , CHEN, Lingjun, Frank , DU, Yun
发明人： JIAO, Guofang , YU, Chun , CHEN, Lingjun, Frank , DU, Yun
IPC分类号： G06T15/50
CPC分类号： G06T15/503 , G06T2210/32
摘要： Techniques for implementing blending equations for various blending modes with a base set of operations are described. Each blending equation may be decomposed into a sequence of operations. In one design, a device includes a processing unit that implements a set of operations for multiple blending modes and a storage unit that stores operands and results. The processing unit receives a sequence of instructions for a sequence of operations for a blending mode selected from the plurality of blending modes and executes each instruction in the sequence to perform blending in accordance with the selected blending mode. The processing unit may include (a) an ALU that performs at least one operation in the base set, e.g., a dot product, (b) a pre-formatting unit that performs gamma correction and alpha scaling of inbound color values, and (c) a post-formatting unit that performs gamma compression and alpha scaling of outbound color values.
摘要翻译：描述了用于具有基本操作集合的用于各种混合模式的混合方程的技术。每个混合方程可以分解为一系列操作。在一种设计中，设备包括一个处理单元，该处理单元实现多种混合模式的一组操作，以及存储操作数和结果的存储单元。处理单元接收用于从多个混合模式中选择的混合模式的操作序列的指令序列，并且执行该顺序中的每个指令以根据所选择的混合模式执行混合。处理单元可以包括（a）执行基本集合中的至少一个操作的ALU，例如点积，（b）执行伽马校正和入站颜色值的α缩放的预格式化单元，以及（c ）一个后格式化单元，用于执行出色色彩值的伽玛压缩和alpha缩放。

6. 发明申请

WO2008048940A3 GRAPHICS PROCESSING UNIT WITH SHARED ARITHMETIC LOGIC UNIT 审中-公开
公开(公告)号：WO2008048940A3
公开(公告)日：2008-04-24
申请号：PCT/US2007/081428
申请日：2007-10-15
申请人： QUALCOMM INCORPORATED , JIAO, Guofang , RUTTENBERG, Brain , YU, Chun , DU, Yun
发明人： JIAO, Guofang , RUTTENBERG, Brain , YU, Chun , DU, Yun
IPC分类号： G06T15/00
摘要： This disclosure describes a graphics processing unit (GPU) pipeline that uses one or more shared arithmetic logic units (ALUs). In order to facilitate such sharing of ALUs, the stages of the disclosed GPU pipeline may be rearranged relative to conventional GPU pipelines. In addition, by rearranging the stages of the GPU pipeline, efficiencies may be achieved in the image processing. Unlike conventional GPU pipelines, for example, an attribute gradient setup stage can be located much later in the pipeline, and the attribute interpolator stage may immediately follow the attribute gradient setup stage. This allows sharing of an ALU by the attribute gradient setup and attribute interpolator stages. Several other techniques and features for the GPU pipeline are also described, which may improve performance and possibly achieve additional processing efficiencies.

7. 发明申请

WO2008019261A3 GRAPHICS PROCESSING UNIT WITH EXTENDED VERTEX CACHE 审中-公开
公开(公告)号：WO2008019261A3
公开(公告)日：2008-02-14
申请号：PCT/US2007/074882
申请日：2007-07-31
申请人： QUALCOMM Incorporated , JIAO, Guofang , RUTTENBERG, Brian , YU, Chun , DU, Yun
发明人： JIAO, Guofang , RUTTENBERG, Brian , YU, Chun , DU, Yun
IPC分类号： G06T15/00
摘要： Techniques are described for processing computerized images with a graphics processing unit (GPU) using an extended vertex cache. The techniques include creating an extended vertex cache coupled to a GPU pipeline to reduce an amount of data passing through the GPU pipeline. The GPU pipeline receives an image geometry for an image, and stores attributes for vertices within the image geometry in the extended vertex cache. The GPU pipeline only passes vertex coordinates that identify the vertices and vertex cache index values that indicate storage locations of the attributes for each of the vertices in the extended vertex cache to other processing stages along the GPU pipeline. The techniques described herein defer the setup of attribute gradients to just before attribute interpolation in the GPU pipeline. The vertex attributes may be retrieved from the extended vertex cache for attribute gradient setup just before attribute interpolation in the GPU pipeline.

8. 发明申请

WO2009049255A3 DEMAND-BASED POWER CONTROL IN A GRAPHICS PROCESSING UNIT 审中-公开
公开(公告)号：WO2009049255A3
公开(公告)日：2009-04-16
申请号：PCT/US2008/079644
申请日：2008-10-10
申请人： QUALCOMM INCORPORATED , DU, Yun , YU, Chun , JIAO, Guofang
发明人： DU, Yun , YU, Chun , JIAO, Guofang
IPC分类号： G06F1/32 , G06F9/38
摘要： Disclosed herein is power controller for use with a graphics processing unit. The power controller monitors, manages and controls power supplied to components of a pipeline of the graphics processing unit. The power controller determining whether and to what extent power is to be supplied to a pipeline component based on status information received by the power controller in connection with the pipeline component. The power controller is capable of identifying a trend using the received status information, and determining whether and to what extent power is to be supplied to a pipeline component based on the identified trend.

9. 发明申请

WO2008128097A2 PROGRAMMABLE GRAPHICS PROCESSING ELEMENT 审中-公开
标题翻译：可编程图形处理元件
公开(公告)号：WO2008128097A2
公开(公告)日：2008-10-23
申请号：PCT/US2008/060103
申请日：2008-04-11
申请人： QUALCOMM INCORPORATED , JIAO, Guofang , CHEN, Lingjun Frank , YU, Chun , DU, Yun
发明人： JIAO, Guofang , CHEN, Lingjun Frank , YU, Chun , DU, Yun
IPC分类号： G06T15/00 , G06F13/10 , G06T15/40 , G06T15/50
CPC分类号： G06T15/005 , G06T15/40 , G06T15/503
摘要： In general, this disclosure describes techniques for performing graphics operations using programmable processing units in a graphics processing unit (GPU). As described herein, a GPU includes a graphics pipeline that includes a programmable graphics processing element (PGPE). In accordance with the techniques described herein, an arbitrary set of instructions is loaded into the PGPE. Subsequently, the PGPE may execute the set of instructions in order to generate a new pixel object. A pixel object describes a displayable pixel. The new pixel object may represent a result of performing a graphics operation on a first pixel object. A display device may display a pixel described by the new pixel object.
摘要翻译：通常，本公开描述了使用图形处理单元（GPU）中的可编程处理单元执行图形操作的技术。如本文所述，GPU包括包括可编程图形处理元件（PGPE）的图形流水线。根据本文描述的技术，任意一组指令被加载到PGPE中。随后，PGPE可以执行该组指令以便生成新的像素对象。像素对象描述可显示像素。新的像素对象可以表示对第一像素对象执行图形操作的结果。显示装置可以显示由新像素对象描述的像素。

10. 发明申请

WO2008036852A1 GRAPHICS PROCESSORS WITH PARALLEL SCHEDULING AND EXECUTION OF THREADS 审中-公开
标题翻译：具有并行调度和螺旋执行的图形处理器
公开(公告)号：WO2008036852A1
公开(公告)日：2008-03-27
申请号：PCT/US2007/079087
申请日：2007-09-20
申请人： QUALCOMM Incorporated , JIAO, Guofang , DU, Yun , YU, Chun
发明人： JIAO, Guofang , DU, Yun , YU, Chun
IPC分类号： G06T15/00
CPC分类号： G06T15/005
摘要： A graphics processor capable of parallel scheduling and execution of multiple threads, and techniques for achieving parallel scheduling and execution, are described. The graphics processor may include multiple hardware units and a scheduler. The hardware units are operable in parallel, with each hardware unit supporting a respective set of operations. The hardware units may include an ALU core, an elementary function core, a logic core, a texture sampler, a load control unit, some other hardware unit, or a combination thereof. The scheduler dispatches instructions for multiple threads to the hardware units concurrently. The graphics processor may further include an instruction cache to store instructions for threads and register banks to store data. The instruction cache and register banks may be shared by the hardware units.
摘要翻译：描述了能够并行调度和执行多个线程的图形处理器以及用于实现并行调度和执行的技术。图形处理器可以包括多个硬件单元和调度器。硬件单元可并行操作，每个硬件单元支持相应的一组操作。硬件单元可以包括ALU核，基本功能核心，逻辑核心，纹理采样器，负载控制单元，一些其他硬件单元或其组合。调度器将多个线程的指令同时分配到硬件单元。图形处理器还可以包括指令高速缓存以存储线程和寄存器组以存储数据的指令。指令高速缓存和寄存器组可以由硬件单元共享。

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