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1. 发明申请

WO2008128097A3 PROGRAMMABLE GRAPHICS PROCESSING ELEMENT 审中-公开
标题翻译：可编程图形处理单元
公开(公告)号：WO2008128097A3
公开(公告)日：2008-12-24
申请号：PCT/US2008060103
申请日：2008-04-11
申请人： QUALCOMM INC , JIAO GUOFANG , CHEN LINGJUN FRANK , YU CHUN , DU YUN
发明人： JIAO GUOFANG , CHEN LINGJUN FRANK , YU CHUN , DU YUN
IPC分类号： G06F13/10 , G06T15/00 , G06T15/40 , G06T15/50
CPC分类号： G06T15/005 , G06T15/40 , G06T15/503
摘要： In general, this disclosure describes techniques for performing graphics operations using programmable processing units in a graphics processing unit (GPU). As described herein, a GPU includes a graphics pipeline that includes a programmable graphics processing element (PGPE). In accordance with the techniques described herein, an arbitrary set of instructions is loaded into the PGPE. Subsequently, the PGPE may execute the set of instructions in order to generate a new pixel object. A pixel object describes a displayable pixel. The new pixel object may represent a result of performing a graphics operation on a first pixel object. A display device may display a pixel described by the new pixel object.
摘要翻译：一般来说，本发明描述用于使用图形处理单元（GPU）中的可编程处理单元来执行图形操作的技术。如这里所描述的，GPU包括包含可编程图形处理元件（PGPE）的图形管线。根据这里描述的技术，任意指令集被加载到PGPE中。随后，PGPE可以执行该组指令以便生成新的像素对象。像素对象描述可显示的像素。新像素对象可以表示对第一像素对象执行图形操作的结果。显示设备可以显示由新像素对象描述的像素。

2. 发明申请

WO2008101210A2 EFFICIENT 2-D AND 3-D GRAPHICS PROCESSING 审中-公开
标题翻译：有效的二维和三维图形处理
公开(公告)号：WO2008101210A2
公开(公告)日：2008-08-21
申请号：PCT/US2008/054162
申请日：2008-02-15
申请人： QUALCOMM Incorporated , JIAO, Guofang , DORBIE, Angus M. , YUN, Jay C. , DU, Yun , YU, Chun
发明人： JIAO, Guofang , DORBIE, Angus M. , YUN, Jay C. , DU, Yun , YU, Chun
IPC分类号： G06T15/00
CPC分类号： G06T15/005 , G06T11/40 , G09G5/363
摘要： Techniques for supporting both 2-D and 3-D graphics are described. A graphics processing unit (GPU) may perform 3-D graphics processing in accordance with a 3-D graphics pipeline to render 3-D images and may also perform 2-D graphics processing in accordance with a 2-D graphics pipeline to render 2-D images. Each stage of the 2-D graphics pipeline may be mapped to at least one stage of the 3-D graphics pipeline. For example, a clipping, masking and scissoring stage in 2-D graphics may be mapped to a depth test stage in 3-D graphics. Coverage values for pixels within paths in 2-D graphics may be determined using rasterization and depth test stages in 3-D graphics. A paint generation stage and an image interpolation stage in 2-D graphics may be mapped to a fragment shader stage in 3-D graphics. A blending stage in 2-D graphics may be mapped to a blending stage in 3-D graphics.
摘要翻译：描述了支持2-D和3-D图形的技术。图形处理单元（GPU）可以根据3-D图形流水线执行3D图形处理以渲染3-D图像，并且还可以根据2-D图形流水线执行2-D图形处理以呈现2 -D图像。 2-D图形管线的每个阶段可以映射到3-D图形流水线的至少一个阶段。例如，2-D图形中的裁剪，掩蔽和裁剪阶段可能被映射到3-D图形中的深度测试阶段。 2-D图形中路径内像素的覆盖值可以使用3-D图形中的光栅化和深度测试阶段来确定。 2-D图形中的油漆生成阶段和图像插值阶段可以映射到3-D图形中的片段着色器阶段。 2-D图形中的混合阶段可以映射到3-D图形的混合阶段。

3. 发明申请

WO2008049110A2 PROGRAMMABLE BLENDING IN A GRAPHICS PROCESSING UNIT 审中-公开
标题翻译：图形处理单元中的可编程混合
公开(公告)号：WO2008049110A2
公开(公告)日：2008-04-24
申请号：PCT/US2007/081952
申请日：2007-10-19
申请人： QUALCOMM Incorporated , JIAO, Guofang , YU, Chun , CHEN, Lingjun, Frank , DU, Yun
发明人： JIAO, Guofang , YU, Chun , CHEN, Lingjun, Frank , DU, Yun
IPC分类号： G06T15/50
CPC分类号： G06T15/503 , G06T2210/32
摘要： Techniques for implementing blending equations for various blending modes with a base set of operations are described. Each blending equation may be decomposed into a sequence of operations. In one design, a device includes a processing unit that implements a set of operations for multiple blending modes and a storage unit that stores operands and results. The processing unit receives a sequence of instructions for a sequence of operations for a blending mode selected from the plurality of blending modes and executes each instruction in the sequence to perform blending in accordance with the selected blending mode. The processing unit may include (a) an ALU that performs at least one operation in the base set, e.g., a dot product, (b) a pre-formatting unit that performs gamma correction and alpha scaling of inbound color values, and (c) a post-formatting unit that performs gamma compression and alpha scaling of outbound color values.
摘要翻译：描述了用于具有基本操作集合的用于各种混合模式的混合方程的技术。每个混合方程可以分解为一系列操作。在一种设计中，设备包括一个处理单元，该处理单元实现多种混合模式的一组操作，以及存储操作数和结果的存储单元。处理单元接收用于从多个混合模式中选择的混合模式的操作序列的指令序列，并且执行该顺序中的每个指令以根据所选择的混合模式执行混合。处理单元可以包括（a）执行基本集合中的至少一个操作的ALU，例如点积，（b）执行伽马校正和入站颜色值的α缩放的预格式化单元，以及（c ）一个后格式化单元，用于执行出色色彩值的伽玛压缩和alpha缩放。

4. 发明申请

WO2008048940A3 GRAPHICS PROCESSING UNIT WITH SHARED ARITHMETIC LOGIC UNIT 审中-公开
公开(公告)号：WO2008048940A3
公开(公告)日：2008-04-24
申请号：PCT/US2007/081428
申请日：2007-10-15
申请人： QUALCOMM INCORPORATED , JIAO, Guofang , RUTTENBERG, Brain , YU, Chun , DU, Yun
发明人： JIAO, Guofang , RUTTENBERG, Brain , YU, Chun , DU, Yun
IPC分类号： G06T15/00
摘要： This disclosure describes a graphics processing unit (GPU) pipeline that uses one or more shared arithmetic logic units (ALUs). In order to facilitate such sharing of ALUs, the stages of the disclosed GPU pipeline may be rearranged relative to conventional GPU pipelines. In addition, by rearranging the stages of the GPU pipeline, efficiencies may be achieved in the image processing. Unlike conventional GPU pipelines, for example, an attribute gradient setup stage can be located much later in the pipeline, and the attribute interpolator stage may immediately follow the attribute gradient setup stage. This allows sharing of an ALU by the attribute gradient setup and attribute interpolator stages. Several other techniques and features for the GPU pipeline are also described, which may improve performance and possibly achieve additional processing efficiencies.

5. 发明申请

WO2008048940A2 GRAPHICS PROCESSING UNIT WITH SHARED ARITHMETIC LOGIC UNIT 审中-公开
标题翻译：具有共享算术逻辑单元的图形处理单元
公开(公告)号：WO2008048940A2
公开(公告)日：2008-04-24
申请号：PCT/US2007081428
申请日：2007-10-15
申请人： QUALCOMM INC , JIAO GUOFANG , RUTTENBERG BRAIN , YU CHUN , DU YUN
发明人： JIAO GUOFANG , RUTTENBERG BRAIN , YU CHUN , DU YUN
IPC分类号： G06T15/00
CPC分类号： G06T15/005
摘要： This disclosure describes a graphics processing unit (GPU) pipeline that uses one or more shared arithmetic logic units (ALUs). In order to facilitate such sharing of ALUs, the stages of the disclosed GPU pipeline may be rearranged relative to conventional GPU pipelines. In addition, by rearranging the stages of the GPU pipeline, efficiencies may be achieved in the image processing. Unlike conventional GPU pipelines, for example, an attribute gradient setup stage can be located much later in the pipeline, and the attribute interpolator stage may immediately follow the attribute gradient setup stage. This allows sharing of an ALU by the attribute gradient setup and attribute interpolator stages. Several other techniques and features for the GPU pipeline are also described, which may improve performance and possibly achieve additional processing efficiencies.
摘要翻译：本公开描述了使用一个或多个共享算术逻辑单元（ALU）的图形处理单元（GPU）流水线。为了促进ALU的这种共享，所公开的GPU流水线的阶段可以相对于传统的GPU管线重新排列。此外，通过重新排列GPU流水线的各个阶段，可以在图像处理中实现效率。与传统GPU流水线不同，例如，属性梯度建立阶段可以在流水线后面定位，并且属性内插器阶段可以立即跟随属性梯度建立阶段。这允许通过属性渐变设置和属性内插器阶段共享ALU。还描述了用于GPU流水线的若干其它技术和特征，其可以提高性能并且可能实现额外的处理效率。

6. 发明申请

WO2008027823A1 DEPENDENT INSTRUCTION THREAD SCHEDULING 审中-公开
标题翻译：相关指令线程调度
公开(公告)号：WO2008027823A1
公开(公告)日：2008-03-06
申请号：PCT/US2007/076867
申请日：2007-08-27
申请人： QUALCOMM INCORPORATED , DU, Yun , YU, Chun , JIAO, Golf
发明人： DU, Yun , YU, Chun , JIAO, Golf
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3824 , G06F9/3838
摘要： A thread scheduler includes context units for managing the execution of threads where each context unit includes a load reference counter for maintaining a counter value indicative of a difference between a number of data requests and a number of data returns associated with the particular context unit. A context controller of the thread context unit is configured to refrain from forwarding an instruction of a thread when the counter value is nonzero and the instruction includes a data dependency indicator indicating the instruction requires data returned by a previous instruction.
摘要翻译：线程调度器包括用于管理线程执行的上下文单元，其中每个上下文单元包括负载参考计数器，用于维持指示多个数据请求与与特定上下文单元相关联的数据返回数量之间的差异的计数器值。线程上下文单元的上下文控制器被配置为当计数器值非零时避免转发线程的指令，并且该指令包括指示该指令需要先前指令返回的数据的数据依赖指示符。

7. 发明申请

WO2008019261A3 GRAPHICS PROCESSING UNIT WITH EXTENDED VERTEX CACHE 审中-公开
公开(公告)号：WO2008019261A3
公开(公告)日：2008-02-14
申请号：PCT/US2007/074882
申请日：2007-07-31
申请人： QUALCOMM Incorporated , JIAO, Guofang , RUTTENBERG, Brian , YU, Chun , DU, Yun
发明人： JIAO, Guofang , RUTTENBERG, Brian , YU, Chun , DU, Yun
IPC分类号： G06T15/00
摘要： Techniques are described for processing computerized images with a graphics processing unit (GPU) using an extended vertex cache. The techniques include creating an extended vertex cache coupled to a GPU pipeline to reduce an amount of data passing through the GPU pipeline. The GPU pipeline receives an image geometry for an image, and stores attributes for vertices within the image geometry in the extended vertex cache. The GPU pipeline only passes vertex coordinates that identify the vertices and vertex cache index values that indicate storage locations of the attributes for each of the vertices in the extended vertex cache to other processing stages along the GPU pipeline. The techniques described herein defer the setup of attribute gradients to just before attribute interpolation in the GPU pipeline. The vertex attributes may be retrieved from the extended vertex cache for attribute gradient setup just before attribute interpolation in the GPU pipeline.

8. 发明申请

WO2008131203A3 COMPUTER MEMORY ADDRESSING MODE EMPLOYING MEMORY SEGMENTING AND MASKING 审中-公开
标题翻译：使用内存分割和掩码的计算机存储器寻址模式
公开(公告)号：WO2008131203A3
公开(公告)日：2009-06-04
申请号：PCT/US2008060793
申请日：2008-04-18
申请人： QUALCOMM INC , ZHANG BO , JIAO GUOFANG , YUN JAY CHUNSUP , DU YUN
发明人： ZHANG BO , JIAO GUOFANG , YUN JAY CHUNSUP , DU YUN
IPC分类号： G06F9/30 , G06F9/312 , G06F9/355
CPC分类号： G06F9/345 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/30138 , G06F9/3016 , G06F9/342 , G06F9/3877
摘要： A computer addressing mode and memory access method rely on a memory segment identifier and a memory segment mask for indicating memory locations. In this addressing mode, a processor receives an instruction comprising the memory segment identifier and memory segment mask. The processor employs a two-level address decoding scheme to access individual memory locations. Under this decoding scheme, the processor decodes the memory segment identifier to select a particular memory segment. Each memory segment includes a predefined number of memory locations. The processor selects memory locations within the memory segment based on mask bits set in the memory segment mask. The disclosed addressing mode is advantageous because it allows non-consecutive memory locations to be efficiently accessed.
摘要翻译：计算机寻址模式和存储器访问方法依赖于存储器段标识符和用于指示存储器位置的存储器段掩码。在该寻址模式中，处理器接收包括存储器段标识符和存储器段掩码的指令。处理器采用两级地址解码方案来访问各个存储单元。在该解码方案下，处理器解码存储器段标识符以选择特定存储器段。每个存储器段包括预定义数量的存储器位置。处理器基于在存储器段掩码中设置的掩码位来选择存储器段内的存储器位置。所公开的寻址模式是有利的，因为它允许有效地访问非连续存储器位置。

9. 发明申请

WO2009055731A1 SERVER-BASED CODE COMPILATION 审中-公开
标题翻译：基于服务器的代码编译
公开(公告)号：WO2009055731A1
公开(公告)日：2009-04-30
申请号：PCT/US2008/081205
申请日：2008-10-24
申请人： QUALCOMM INCORPORATED , CHEN, Lingjun , DU, Yun , YU, Chun , JIAO, Guofang
发明人： CHEN, Lingjun , DU, Yun , YU, Chun , JIAO, Guofang
IPC分类号： G06F9/45
CPC分类号： G06F8/41
摘要： A server is disclosed that includes an interface to a data communication network, a compiler library that stores a plurality of different compilers, and compiler selection logic responsive to data received at the interface and including logic. The compiler selection logic is configured to select one of the plurality of different compilers based on an evaluation of the received data. The selected compiler generates compiled output data and the compiled output data is communicated over the data communication network to a client.
摘要翻译：公开了一种服务器，其包括对数据通信网络的接口，存储多个不同编译器的编译器库，以及响应于在接口处接收的数据并包括逻辑的编译器选择逻辑。编译器选择逻辑被配置为基于对接收到的数据的评估来选择多个不同编译器之一。所选择的编译器生成编译的输出数据，并且编译的输出数据通过数据通信网络传送到客户机。

10. 发明申请

WO2009018385A3 SCHEME FOR PACKING AND LINKING OF VARIABLES IN GRAPHICS SYSTEMS 审中-公开
标题翻译：在图形系统中包含和链接变量的方案
公开(公告)号：WO2009018385A3
公开(公告)日：2009-03-26
申请号：PCT/US2008071655
申请日：2008-07-30
申请人： QUALCOMM INC , JIAO GUOFANG , BOURD ALEXEI V , YU CHUN , CHEN LINGJUN , DU YUN
发明人： JIAO GUOFANG , BOURD ALEXEI V , YU CHUN , CHEN LINGJUN , DU YUN
IPC分类号： G06T1/60
CPC分类号： G06T1/60 , G06T15/005
摘要： A wireless device which performs a first-level compiler packing process and a second-level hardware packing process on varyings. The compiler packing process packs two or more shader variables (varyings or attributes) whose sum of components equals M into a shared M-dimensional (MD) vector register. The hardware packing consecutively packs M components of the shader variables (varyings or attributes) and any remaining variables into a vertex cache or other storage medium.
摘要翻译：执行第一级编译器打包处理的无线设备和关于变化的二级硬件打包过程。编译器打包过程将两个或更多个成分等于M的着色器变量（变化或属性）打包成共享的M维（MD）向量寄存器。硬件包装将着色器变量（变化或属性）的M个组件以及任何剩余变量包含在顶点缓存或其他存储介质中。

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