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1. 发明申请

WO2018052513A1 PROCESS VARIATION POWER CONTROL IN THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICS) (3DICS) 审中-公开
标题翻译：三维（3D）集成电路（ICS）中的工艺变化功率控制（3DICS）
公开(公告)号：WO2018052513A1
公开(公告)日：2018-03-22
申请号：PCT/US2017/041616
申请日：2017-07-12
申请人： QUALCOMM INCORPORATED
发明人： SAMSON, Giby , PU, Yu , DU, Yang
IPC分类号： H03K19/003 , H01L27/06 , H03K3/03
摘要： Systems and methods for process variation power control in three- dimensional integrated circuits, 3DICs, are disclosed. In an exemplary aspect, at least one process variation sensor (324, 326) is placed in each tier (302) of a 3DIC (300). The process variation sensors report information related to a speed characteristic for elements within the respective tier to a decision logic (328). The decision logic is programmed to weight output from the process variation sensors according to relative importance of logic path segments (310, 320) in the respective tiers. The weighted outputs are combined to generate a power control signal that is sent to a power management unit (PMU). By weighting the importance of the logic path segments, a compromise voltage may be generated by the PMU which is "good enough" for all the elements in the various tiers to provide acceptable performance.
摘要翻译：公开了用于三维集成电路3DIC中的过程变化功率控制的系统和方法。在示例性方面，至少一个过程变化传感器（324,326）被放置在3DIC（300）的每个层（302）中。过程变化传感器将与相应层内的元件的速度特性相关的信息报告给判定逻辑（328）。判定逻辑被编程为根据相应层中的逻辑路径段（310,320）的相对重要性对来自过程变化传感器的输出进行加权。加权输出被组合以生成被发送到电力管理单元（PMU）的电力控制信号。通过对逻辑路径段的重要性进行加权，可以由PMU产生妥协电压，其“足够好” 为各层级中的所有元素提供可接受的性能。

2. 发明申请

WO2017053006A1 TECHNIQUES TO IDENTIFY A PROCESS CORNER 审中-公开
标题翻译：识别过程角的技术
公开(公告)号：WO2017053006A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/049028
申请日：2016-08-26
申请人： QUALCOMM INCORPORATED
发明人： PU, Yu , SAMSON, Giby , YUEN, Kendrick Hoy Leong
IPC分类号： G01R31/28 , G01R31/30 , H01L21/66
CPC分类号： G01R31/2851 , G01R31/2884 , G01R31/3004 , H01L22/14 , H01L22/34
摘要： Methods and apparatus for identifying a process corner are provided. Provided is an exemplary method for identifying a process corner of an integrated circuit (IC). The IC has a first asymmetrical ring oscillator (ARO1) including pull-up transistors that have a low threshold voltage (LVT) and pull-down transistors that have a regular threshold voltage (RVT), and has a second asymmetrical ring oscillator (ARO2) including pull-up transistors that have an RVT and pull-down transistors having an LVT. The exemplary method includes applying an ultra-low power supply voltage to the ARO1 and the ARO2 that causes the integrated circuit to operate near a verge of malfunction, measuring an output frequency of the ARO1, measuring an output frequency of the ARO2, calculating a calculated ratio of the output frequency of the ARO1 and the output frequency of the ARO2, and comparing the calculated ratio to a fiduciary ratio to identify the process corner.
摘要翻译：提供了用于识别过程角的方法和装置。提供了一种用于识别集成电路（IC）的处理角的示例性方法。 IC具有第一不对称环形振荡器（ARO1），其包括具有低阈值电压（LVT）的上拉晶体管和具有规则阈值电压（RVT）的下拉晶体管，并且具有第二不对称环形振荡器（ARO2）包括具有具有LVT的RVT和下拉晶体管的上拉晶体管。该示例性方法包括将超低电源电压施加到ARO1和ARO2，使得集成电路在故障边缘附近操作，测量ARO1的输出频率，测量ARO2的输出频率，计算计算出的 ARO1的输出频率与ARO2的输出频率的比值，并将计算出的比率与受托比率进行比较，以识别过程角。

3. 发明申请

WO2020247509A2 DUAL-MODE HIGH-BANDWIDTH SRAM WITH SELF-TIMED CLOCK CIRCUIT 审中-公开
公开(公告)号：WO2020247509A2
公开(公告)日：2020-12-10
申请号：PCT/US2020/035937
申请日：2020-06-03
申请人： QUALCOMM INCORPORATED
发明人： NGUYEN, Hoan Huu , ATALLAH, Francois Ibrahim , BOWMAN, Keith Alan , YINGLING, Daniel , JEONG, Jihoon , PU, Yu
IPC分类号： G11C7/10 , G11C11/416 , G11C11/419 , G11C7/06 , G11C7/08 , G11C7/22 , G11C11/417 , G11C11/418 , G11C7/062 , G11C7/065 , G11C7/1045 , G11C7/1051 , G11C7/1072 , G11C7/14
摘要： A dual-mode memory is provided that includes a self-timed clock circuit for asserting a sense enable signal for a sense amplifier. In a low-bandwidth read mode, the self-timed clock circuit asserts the sense enable signal only once during a memory clock cycle. The sense amplifier then senses only a single bit from a group of multiplexed columns. In a high-bandwidth read mode, the self-timed clock circuit successively asserts the sense enable signal so that the sense amplifier successively senses bits from the multiplexed columns.

4. 发明申请

WO2018038802A3 ADAPTIVE POWER REGULATION METHODS AND SYSTEMS 审中-公开
公开(公告)号：WO2018038802A3
公开(公告)日：2018-03-01
申请号：PCT/US2017/039388
申请日：2017-06-27
申请人： QUALCOMM INCORPORATED
发明人： SAMSON, Giby , BOWMAN, Keith, Alan , PU, Yu , ATALLAH, Francois, Ibrahim
IPC分类号： G06F1/32 , G11C5/14 , G11C29/04 , G11C29/02
摘要： Adaptive power regulation methods and systems are disclosed. In one aspect, one or more process sensors for memory elements are provided, which report information relating to inherent speed characteristics of sub-elements within the memory elements. Based on this reported information, a controller ascertains an appropriate power level to insure a proper data retention voltage (DRV) is applied on voltage rails by a power management unit (PMU) circuit. By using the proper DRV based on the speed characteristics of the sub-elements within the memory elements, power conservation is achieved.

5. 发明申请

WO2018038802A2 ADAPTIVE POWER REGULATION METHODS AND SYSTEMS 审中-公开
标题翻译：自适应功率调节方法和系统
公开(公告)号：WO2018038802A2
公开(公告)日：2018-03-01
申请号：PCT/US2017/039388
申请日：2017-06-27
申请人： QUALCOMM INCORPORATED
发明人： SAMSON, Giby , BOWMAN, Keith, Alan , PU, Yu , ATALLAH, Francois, Ibrahim
IPC分类号： G06F1/32 , G11C5/14
摘要： Adaptive power regulation methods and systems are disclosed. In one aspect, one or more process sensors for memory elements are provided, which report information relating to inherent speed characteristics of sub-elements within the memory elements. Based on this reported information, a controller ascertains an appropriate power level to insure a proper data retention voltage (DRV) is applied on voltage rails by a power management unit (PMU) circuit. By using the proper DRV based on the speed characteristics of the sub-elements within the memory elements, power conservation is achieved.
摘要翻译：公开了自适应功率调节方法和系统。在一个方面，提供了用于存储器元件的一个或多个处理传感器，其报告与存储器元件内的子元件的固有速度特性有关的信息。基于这个报告的信息，控制器确定适当的功率水平以确保电源管理单元（PMU）电路在电压轨上施加正确的数据保持电压（DRV）。通过基于存储器元件内的子元件的速度特性来使用适当的DRV，实现节能。

6. 发明申请

WO2017039896A1 AREA AND POWER EFFICIENT SWITCHABLE SUPPLY NETWORK FOR POWERING MULTIPLE DIGITAL ISLANDS 审中-公开
标题翻译：为多个数字岛屿供电的区域和功率有效的可切换供电网络
公开(公告)号：WO2017039896A1
公开(公告)日：2017-03-09
申请号：PCT/US2016/044451
申请日：2016-07-28
申请人： QUALCOMM INCORPORATED
发明人： SHI, Chunlei , PU, Yu , EASTON, Kenneth, David , YUEN, Kendrick, Hoy, Leong , SAMSON, Giby
IPC分类号： G06F1/32 , H03K19/00
CPC分类号： H02J3/38 , G06F1/3287 , H02J2003/388 , H03K19/0016
摘要： A switchable supply network for powering multiple digital islands. In one embodiment, a first digital island includes a first power collapsible circuit and a first retention circuit, and a second digital island includes a second power collapsible circuit and a second retention circuit. In a normal mode of operation, the first digital island is provided a first supply voltage and a second digital island is provided a second supply voltage higher than the first supply voltage. In a transition mode the second power collapsible circuit is powered down and the second supply voltage is lowered and provided to the second retention circuit. When the second supply voltage falls below the first supply voltage, the first power collapsible circuit is powered down. The second supply voltage is now provided only to the retention circuits, and is furthered lowered in a retention mode to a final retention voltage.
摘要翻译：用于为多个数字岛供电的可切换供电网络。在一个实施例中，第一数字岛包括第一电源可折叠电路和第一保持电路，第二数字岛包括第二电源可折叠电路和第二保持电路。在正常操作模式中，第一数字岛被提供第一电源电压，并且第二数字岛被提供有高于第一电源电压的第二电源电压。在转换模式中，第二功率可折叠电路断电并且第二电源电压降低并提供给第二保持电路。当第二电源电压低于第一电源电压时，第一电源可折叠电路断电。现在仅向保持电路提供第二电源电压，并且在保持模式下进一步降低到最终的保持电压。

7. 发明申请

WO2018031167A1 ELECTRONIC DEVICES EMPLOYING ADIABATIC LOGIC CIRCUITS WITH WIRELESS CHARGING 审中-公开
标题翻译：利用绝对逻辑电路进行无线充电的电子设备
公开(公告)号：WO2018031167A1
公开(公告)日：2018-02-15
申请号：PCT/US2017/041629
申请日：2017-07-12
申请人： QUALCOMM INCORPORATED
发明人： PU, Yu , SAMSON, Giby
IPC分类号： H03K19/00 , H02J7/02 , H03K19/017
摘要： Electronic devices employing adiabatic logic circuits with wireless charging are disclosed. In one aspect, an electronic device is provided. The electronic device includes a power circuit employing an alternating current (AC) coupler circuit configured to receive a wireless AC signal and generate a wired AC signal based on the wireless AC signal. The power circuit includes a power output configured to provide an AC power signal based on the wired AC signal generated by the AC coupler circuit. The AC power signal is generated based on the wireless charging capability of the AC coupler circuit. The electronic device employs a digital logic system that includes a power rail electrically coupled to an adiabatic logic circuit. The AC power signal is provided to the power rail to provide power to the adiabatic logic circuit. Wirelessly charging the adiabatic logic circuit consumes less power than conventional non-wireless charging circuitry.
摘要翻译：公开了采用具有无线充电的绝热逻辑电路的电子设备。在一个方面中，提供了一种电子设备。该电子设备包括采用交流（AC）耦合器电路的电源电路，该交流（AC）耦合器电路被配置为接收无线AC信号并且基于该无线AC信号生成有线AC信号。功率电路包括功率输出端，该功率输出端被配置成基于由AC耦合器电路产生的有线AC信号来提供AC功率信号。交流电源信号是基于交流耦合器电路的无线充电能力产生的。电子设备采用数字逻辑系统，其包括电耦合到绝热逻辑电路的电力轨。交流电源信号被提供给电源轨以向绝热逻辑电路提供电力。无线充电绝热逻辑电路比传统的非无线充电电路消耗更少的功率。

8. 发明申请

WO2016144625A1 CLOCK DISTRIBUTION SCHEMES WITH WIDE OPERATING VOLTAGE RANGES 审中-公开
标题翻译：具有宽操作电压范围的时钟分配方案
公开(公告)号：WO2016144625A1
公开(公告)日：2016-09-15
申请号：PCT/US2016/020330
申请日：2016-03-02
申请人： QUALCOMM INCORPORATED
发明人： SAMSON, Giby , PU, Yu , YUEN, Kendrick, Hoy Leong
IPC分类号： G06F1/10
CPC分类号： H03K5/135 , G06F1/10 , H03K19/0016 , H03K2005/00052
摘要： Clock distribution schemes with wide operating voltage ranges are disclosed. In one aspect, an operating voltage level or condition within a computing device is sensed. In a first voltage condition, delay elements are used within a clock tree to minimize clock skew. In a second voltage condition, one or more delay and/or clocked elements are bypassed to minimize clock skew at the second voltage condition. In addition to controlling clock skew, power may be conserved by depowering the bypassed elements. Controlling clock skew in this fashion improves operation of a computing device that includes the clock tree and may improve battery life.
摘要翻译：公开了具有宽工作电压范围的时钟分配方案。在一个方面，感测计算设备内的工作电压电平或状况。在第一电压条件下，在时钟树中使用延迟元件以最小化时钟偏移。在第二电压条件下，绕过一个或多个延迟和/或时钟元件以使在第二电压条件下的时钟偏移最小化。除了控制时钟偏移之外，通过削弱旁路元件可以节省功率。以这种方式控制时钟偏移改善了包括时钟树的计算设备的操作并且可以提高电池寿命。

9. 发明申请

WO2019139701A1 DIGITAL DESIGN WITH BUNDLED DATA ASYNCHRONOUS LOGIC AND BODY-BIASING TUNING 审中-公开
公开(公告)号：WO2019139701A1
公开(公告)日：2019-07-18
申请号：PCT/US2018/064395
申请日：2018-12-07
申请人： QUALCOMM INCORPORATED
发明人： LIN, Mark , PU, Yu , SAMSON, Giby
IPC分类号： H03K19/00 , G06F17/50
摘要： Aspects of the disclosure are directed to a digital design with bundled data asynchronous logic and body-biasing tuning. In one aspect, implementation includes establishing a control path between a first controller and a second controller using a handshaking protocol; establishing a data path between a first latch and a second latch using a bundled data technique; executing a first dynamic body biasing tuning by applying a first body bias signal to the control path; executing a second dynamic body biasing tuning by applying a second body bias signal to the data path. The digital design includes a first controller with a control path to connect to a second controller, wherein a first body bias tuning signal tunes body bias in the control path, a first latch with a data path to connect to a second latch, wherein a second body bias tuning signal tunes body bias in the data path.

10. 发明申请

WO2019046835A1 ULTRA-LOW POWER NEUROMORPHIC ARTIFICIAL INTELLIGENCE COMPUTING ACCELERATOR 审中-公开
公开(公告)号：WO2019046835A1
公开(公告)日：2019-03-07
申请号：PCT/US2018/049287
申请日：2018-09-01
申请人： QUALCOMM INCORPORATED
发明人： PU, Yu , DU, Yang
IPC分类号： G06N3/063 , G06F1/32 , G06N3/04 , G06N3/08 , G11C11/00 , G11C11/16 , G11C11/54 , G11C13/00 , H01L25/18 , H01L25/00
摘要： A three-dimensional (3D) ultra-low power neuromorphic accelerator is described. The 3D ultra-low power neuromorphic accelerator includes a power manager as well as multiple tiers. The 3D ultra-low power neuromorphic accelerator also includes multiple cores defined on each tier and coupled to the power manager. Each core includes at least a processing element, a non-volatile memory, and a communications module.

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