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1. 发明申请

WO2012167239A2 APPARATUS AND SYSTEMS DIGITAL PHASE INTERPOLATOR WITH IMPROVED LINEARITY 审中-公开
标题翻译：具有改进线性的装置和系统数字相位插值器
公开(公告)号：WO2012167239A2
公开(公告)日：2012-12-06
申请号：PCT/US2012/040718
申请日：2012-06-04
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED , ERDOGAN, Mustafa, Ulvi
发明人： ERDOGAN, Mustafa, Ulvi
CPC分类号： H03K5/133 , H03K5/131 , H03K2005/00052 , H03L7/0812 , H03L7/16
摘要： An apparatus comprising: a first control switch (111) driven by a first bit value; a first weighted switch (141) driven by a first clock signal; a first intermediate node (112) coupled between the first control switch and the first weighted switch; a first pre-charge transistor (131) coupled to the first intermediate node, wherein the pre-charge transistor is driven by an inverse of the clock signal; a second control switch (121) driven by an inverse of the bit; a second weighted switch (151) driven by a second clock signal; a second intermediate node (122) coupled between the second control switch and the second weighted switch; a second pre-charge transistor (135) coupled to the second intermediate node, wherein the second pre-charge transistor (135) is driven by an inverse of the second clock signal; and a capacitor (159) coupled to the first control switch, the second control switch, the first weighted switch and the second weighted switch.
摘要翻译：一种装置，包括：由第一位值驱动的第一控制开关（111）由第一时钟信号驱动的第一加权开关（141）耦合在所述第一控制开关和所述第一加权开关之间的第一中间节点（112）耦合到所述第一中间节点的第一预充电晶体管（131），其中所述预充电晶体管由所述时钟信号的反相驱动; 由比特的倒数驱动的第二控制开关（121）由第二时钟信号驱动的第二加权开关（151）; 耦合在所述第二控制开关和所述第二加权开关之间的第二中间节点（122）耦合到所述第二中间节点的第二预充电晶体管（135），其中所述第二预充电晶体管（135）由所述第二时钟信号的反相驱动; 以及耦合到第一控制开关，第二控制开关，第一加权开关和第二加权开关的电容器（159）。

2. 发明申请

WO2020046741A1 EMBEDDED UNIVERSAL SERIAL BUS 2 REPEATER 审中-公开
公开(公告)号：WO2020046741A1
公开(公告)日：2020-03-05
申请号：PCT/US2019/047877
申请日：2019-08-23
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： MAUNG, Win, Naing , WENTE, Douglas, Edward , ERDOGAN, Mustafa, Ulvi , HUANG, Huanzhang , GOYAL, Saurabh , SHARMA, Bhupendra
IPC分类号： G06F3/00 , G06F13/42
摘要： This description provides a circuit (200) including a squelch detector (225) having a first input coupled to a first node (260) and configured to receive a positive component of a differential signal with a floating center tap, a second input coupled to a second node (262) and configured to receive a negative component of the differential signal, and an output coupled to a logic circuit (230), a first resistor (235) coupled between the first node and a third node (268), a second resistor (240) coupled between the third node and the second node, a third resistor (245) coupled between the first node and a fourth node (270), a fourth resistor (250) coupled between the fourth node and the second node, a capacitor (255) coupled between the fourth node and a ground terminal (272), a comparator (220) having a first input coupled to the third node, a second input coupled to a fifth node (274), and an output coupled to the logic circuit.

3. 发明申请

WO2020033421A1 EMBEDDED UNIVERSAL SERIAL BUS 2 REPEATER 审中-公开
公开(公告)号：WO2020033421A1
公开(公告)日：2020-02-13
申请号：PCT/US2019/045326
申请日：2019-08-06
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： MAUNG, Win Naing , GOYAL, Saurabh , SHARMA, Bhupendra , HUANG, Huanzhang , WENTE, Douglas Edward , VINING, Suzanne Mary , ERDOGAN, Mustafa, Ulvi
IPC分类号： G06F13/40
摘要： In some examples, a method (800) includes receiving, at a circuit, data via a differential input signal (805), detecting a rising edge in the data received via the differential input signal (810), and precharging a common mode voltage (Vcm) node of the differential input signal responsive to detecting the rising edge in the data received via the differential input signal (815). The Vcm node is a floating node.

4. 发明申请

WO2020046499A3 EMBEDDED UNIVERSAL SERIAL BUS 2 REPEATER 审中-公开
公开(公告)号：WO2020046499A3
公开(公告)日：2020-03-05
申请号：PCT/US2019/043334
申请日：2019-07-25
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： MAUNG, Win, Naing , SHARMA, Bhupendra , HUANG, Huanzhang , WENTE, Douglas, Edward , VINING, Suzanne, Mary , ERDOGAN, Mustafa, Ulvi
IPC分类号： G06F13/40
摘要： Aspects of the disclosure provide for a method (500). In some examples, the method includes receiving, at a circuit, data via a differential input signal (505). The method further includes detecting a falling edge in the data received via the differential input signal (515). The method further includes holding an output of the circuit at a final logical value of the data (520). The method further includes disabling a transmitter of the circuit while holding the output of the circuit at the final logical value of the data (525). The method further includes releasing the output of the circuit from the final logical value of the data (525).

5. 发明申请

WO2020046499A2 EMBEDDED UNIVERSAL SERIAL BUS 2 REPEATER 审中-公开
公开(公告)号：WO2020046499A2
公开(公告)日：2020-03-05
申请号：PCT/US2019/043334
申请日：2019-07-25
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： MAUNG, Win, Naing , SHARMA, Bhupendra , HUANG, Huanzhang , WENTE, Douglas, Edward , VINING, Suzanne, Mary , ERDOGAN, Mustafa, Ulvi
IPC分类号： G06F13/40
摘要： Aspects of the disclosure provide for a method (500). In some examples, the method includes receiving, at a circuit, data via a differential input signal (505). The method further includes detecting a falling edge in the data received via the differential input signal (515). The method further includes holding an output of the circuit at a final logical value of the data (520). The method further includes disabling a transmitter of the circuit while holding the output of the circuit at the final logical value of the data (525). The method further includes releasing the output of the circuit from the final logical value of the data (525).

6. 发明申请

WO2022103998A1 A REDRIVER CAPABLE OF SWITCHING BETWEEN LINEAR AND LIMITED MODES 审中-公开
公开(公告)号：WO2022103998A1
公开(公告)日：2022-05-19
申请号：PCT/US2021/059045
申请日：2021-11-12
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： CAMPBELL, Charles, Michael , ERDOGAN, Mustafa, Ulvi , WENTE, Douglas, Edward , RAMASWAMY, Sridhar
IPC分类号： H04B3/36 , G06F13/38
摘要： A redriver system (130) adapted for coupling to a first device and to a second device includes first and second transmitter drivers and a snoop circuit (148). The first transmitter driver has a first enable input. The second transmitter driver has a second enable input. The snoop circuit (148) is coupled to the first and second enable inputs. The snoop circuit (148) is configured to determine whether the first device and the second device are to operate according to a first protocol. Responsive to the snoop circuit (148) determining that the first and second devices are to operate according to the first protocol, the snoop circuit (148) enables the first transmitter driver and disables the second transmitter driver. Responsive to the snoop circuit determining that the first and second devices are not to operate according to the first protocol, the snoop circuit disables the first transmitter driver and enables the second transmitter driver.

7. 发明申请

WO2022150733A1 METHODS AND SYSTEMS FOR ADAPTIVE EQUALIZATION WITH WIDE RANGE OF SIGNAL AMPLITUDES 审中-公开
公开(公告)号：WO2022150733A1
公开(公告)日：2022-07-14
申请号：PCT/US2022/011891
申请日：2022-01-11
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： GUO, Shita , FAN, Yanli , ERDOGAN, Mustafa, Ulvi , WENTE, Douglas, Edward
IPC分类号： H04L25/03
摘要： Methods and systems of adaptive equalization to compensate channel loss are described. A method includes detecting a peak amplitude (504) of an equalizer output signal and selecting (508) a set of reference voltage levels from M sets based on the peak amplitude of the equalizer output signal, each of the M sets having N reference voltage levels. The method includes continuing to increase (528) an equalization level in predetermined steps to a next higher equalization level if the applied equalization level does not correspond to the over-equalization level and evaluating the distribution of the resulting hit counts for each increase to the next higher equalization level until the applied equalization level corresponds to the over-equalization level. The method includes decreasing (524) to the previously applied lower equalization level if the applied equalization level corresponds to the over-equalization level.

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