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1. 发明申请

WO2016049598A1 SIX-TRANSISTOR SRAM SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATION 审中-公开
标题翻译：六极晶体管SRAM半导体结构和制造方法
公开(公告)号：WO2016049598A1
公开(公告)日：2016-03-31
申请号：PCT/US2015/052493
申请日：2015-09-25
申请人： KILOPASS TECHNOLOGY, INC.
发明人： LUAN, Harry , BATEMAN, Bruce , AXELRAD, Valery , CHENG, Charlie , CHEVALLIER, Christophe
IPC分类号： G11C7/00
CPC分类号： H01L27/1025 , G11C11/39 , G11C11/41 , G11C11/411 , G11C11/412 , G11C11/419 , H01L21/76229 , H01L21/768 , H01L21/8229 , H01L21/8249 , H01L23/528 , H01L27/0623 , H01L27/0821 , H01L27/0826 , H01L27/1027 , H01L27/11 , H01L27/1104 , H01L29/0642 , H01L29/0649 , H01L29/0804 , H01L29/0821 , H01L29/083 , H01L29/1004 , H01L29/1012 , H01L29/1095 , H01L29/42304 , H01L29/6625 , H01L29/66272 , H01L29/735 , H01L29/737 , H01L29/7436 , H01L2924/0002 , H01L2924/00
摘要： A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricatingit. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.
摘要翻译：基于用于SRAM集成电路的晶闸管的双晶体管存储单元与制造工艺一起被描述。存储器单元可以在具有浅沟槽隔离的半导体衬底中的晶闸管的MOS和双极选择晶体管的不同组合中实现，或者不具有选择晶体管。标准CMOS工艺技术可用于制造SRAM。

2. 发明申请

WO2016049590A1 CROSS-COUPLED THYRISTOR SRAM SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATION 审中-公开
标题翻译：交叉耦合二极管SRAM半导体结构和制造方法
公开(公告)号：WO2016049590A1
公开(公告)日：2016-03-31
申请号：PCT/US2015/052480
申请日：2015-09-25
申请人： KILOPASS TECHNOLOGY, INC.
发明人： LUAN, Harry , BATEMAN, Bruce , AXELRAD, Valery , CHENG, Charlie , CHEVALLIER, Christophe
IPC分类号： G11C11/00 , G11C11/411 , G11C11/419 , G11C11/34 , G11C7/12
CPC分类号： H01L27/0623 , G11C11/39 , G11C11/4113 , G11C11/4116 , G11C11/416 , G11C11/419 , H01L21/8249 , H01L27/1025 , H01L27/1027 , H01L27/11 , H01L29/7404 , H01L29/7436
摘要： A memory cell based upon thyristors for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM. Special circuitry provides lowered power consumption during standby.
摘要翻译：基于用于SRAM集成电路的晶闸管的存储单元与其制造方法一起被描述。存储器单元可以在具有浅沟槽隔离的半导体衬底中的晶闸管的MOS和双极选择晶体管的不同组合中实现，或者不具有选择晶体管。标准CMOS工艺技术可用于制造SRAM。特殊电路在待机期间提供降低的功耗。

3. 发明申请

WO2016049581A1 CROSS-COUPLED THYRISTOR SRAM CIRCUITS AND METHODS OF OPERATION 审中-公开
标题翻译：交叉耦合晶体管电路和操作方法
公开(公告)号：WO2016049581A1
公开(公告)日：2016-03-31
申请号：PCT/US2015/052468
申请日：2015-09-25
申请人： KILOPASS TECHNOLOGY, INC.
发明人： LUAN, Harry , BATEMAN, Bruce , AXELRAD, Valery , CHENG, Charlie , CHEVALLIER, Christophe
IPC分类号： G11C11/00 , G11C11/411 , G11C7/12 , G11C11/34 , G11C11/419
CPC分类号： H01L27/0623 , G11C11/39 , G11C11/4113 , G11C11/4116 , G11C11/416 , G11C11/419 , H01L21/8249 , H01L27/1025 , H01L27/1027 , H01L27/11 , H01L29/7404 , H01L29/7436
摘要： A memory cell based upon thyristors for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM. Special circuitry provides lowered power consumption during standby.
摘要翻译：基于用于SRAM集成电路的晶闸管的存储单元与其制造方法一起被描述。存储器单元可以以具有浅沟槽隔离的半导体衬底中的晶闸管与MOS和双极选择晶体管的不同组合或不具有选择晶体管来实现。标准CMOS工艺技术可用于制造SRAM。特殊电路在待机期间提供降低的功耗。

4. 发明申请

WO2010092555A3 FOUR-TRANSISTOR AND FIVE-TRANSISTOR BJT-CMOS ASYMMETRIC SRAM CELLS 审中-公开
标题翻译：四晶体和五晶体BJT-CMOS不对称SRAM电池
公开(公告)号：WO2010092555A3
公开(公告)日：2016-05-26
申请号：PCT/IB2010050668
申请日：2010-02-15
申请人： ASA GIL
发明人： ASA GIL
IPC分类号： G11C11/00
CPC分类号： H01L21/8249 , G11C11/411 , G11C11/412 , H01L27/0623 , H01L27/0688 , H01L27/1025 , H01L27/11 , H03K3/288
摘要： A memory cell comprises asymmetric retention elements formed of bipolar junction transistors integrated with a CMOS transistor. The BJT transistors of the retention element may be vertically stacked. In one embodiment, the N region of two adjacent NPN BJT transistors may be connected to ground and may form a common emitter of the NPN BJT transistors while the P region of two adjacent PNP BJT transistors may be connected to high voltage and may form a common emitter of the PNP BJT transistors. For further compactness in one embodiment a base of one transistor doubles as a collector of another transistor. The retention element may have only a single bit line and a single write line, with no negative bit line. In some embodiments, a single inverter and only three transistors may form the retention element. Memory space may be cut approximately in half.
摘要翻译：存储单元包括由与CMOS晶体管集成的双极结型晶体管形成的不对称保留元件。保持元件的BJT晶体管可以是垂直堆叠的。在一个实施例中，两个相邻NPN BJT晶体管的N区可以连接到地，并且可以形成NPN BJT晶体管的公共发射极，而两个相邻的PNP BJT晶体管的P区可以连接到高电压并且可以形成公共 PNP BJT晶体管的发射极。为了在一个实施例中进一步的紧凑性，一个晶体管的基极可兼作另一个晶体管的集电极。保持元件可以仅具有单个位线和单个写入线，没有负位线。在一些实施例中，单个逆变器和仅三个晶体管可以形成保持元件。内存空间大约可以削减一半。

5. 发明申请

WO2012017746A1 半導体装置およびその製造方法ならびに不揮発性半導体記憶装置审中-公开
标题翻译：半导体器件，其制造方法和非易失性半导体存储器件
公开(公告)号：WO2012017746A1
公开(公告)日：2012-02-09
申请号：PCT/JP2011/064060
申请日：2011-06-20
申请人：株式会社日立製作所 , 久本大 , 斎藤慎一 , 島明生 , 吉元広行
发明人：久本　大 , 斎藤　慎一 , 島　明生 , 吉元　広行
IPC分类号： H01L21/8249 , H01L21/331 , H01L21/8234 , H01L21/8238 , H01L21/8244 , H01L21/8247 , H01L27/06 , H01L27/088 , H01L27/092 , H01L27/11 , H01L27/115 , H01L29/66 , H01L29/732 , H01L29/78 , H01L29/786 , H01L29/788 , H01L29/792
CPC分类号： H01L27/1203 , G11C11/412 , G11C16/0408 , H01L21/8249 , H01L21/84 , H01L23/535 , H01L27/0623 , H01L27/0705 , H01L27/092 , H01L27/1025 , H01L27/1026 , H01L27/11 , H01L27/11521 , H01L27/11568 , H01L29/0649 , H01L29/0804 , H01L29/0821 , H01L29/0847 , H01L29/0895 , H01L29/1004 , H01L29/1033 , H01L29/66825 , H01L29/66833 , H01L29/7311 , H01L29/788 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要：　これまでのＭＯＳＦＥＴと同等の集積性を維持しながら、ＭＯＳＦＥＴに比べて優れたスイッチング特性をもつ、すなわち、室温においてＳ値が６０ｍＶ／桁より小さな値をもつ半導体素子を提供する。ＭＯＳＦＥＴと、トンネル接合を有するトンネルバイポーラトランジスタを組み合わせることにより、低電圧であっても、ゲート電位変化に対してドレイン電流が急峻な変化（Ｓ値が６０ｍＶ／桁よりも小さい）を示す半導体素子を構成する。
摘要翻译：提供了与MOSFET相比，具有与常规MOSFET相同的可集成性的半导体元件，即在室温下S值小于60mV /次的优异的开关特性。通过组合MOSFET和具有隧道结的隧道双极型晶体管，配置了相对于栅极电压的变化（S值小于60mV /次）显示出漏电流的突然变化的半导体元件，即使在低电压。

6. 发明申请

WO2019050848A1 BI-STABLE STATIC RANDOM ACCESS MEMORY (SRAM) BIT CELLS FORMED FROM III-V COMPOUNDS AND CONFIGURED TO ACHIEVE HIGHER OPERATING SPEEDS 审中-公开
公开(公告)号：WO2019050848A1
公开(公告)日：2019-03-14
申请号：PCT/US2018/049371
申请日：2018-09-04
申请人： QUALCOMM INCORPORATED
发明人： TAO, Gengming , LI, Xia , YANG, Bin
IPC分类号： H01L27/108 , H01L27/102 , G11C11/411 , H01L27/11 , H01L29/78
CPC分类号： H01L27/1104 , G11C11/4113 , G11C11/412 , G11C11/419 , H01L21/02543 , H01L21/02546 , H01L21/02634 , H01L27/0605 , H01L27/0705 , H01L27/1025 , H01L27/10802 , H01L27/11 , H01L29/0817 , H01L29/0821 , H01L29/0847 , H01L29/1004 , H01L29/1033 , H01L29/1095 , H01L29/20 , H01L29/205 , H01L29/41708 , H01L29/66318 , H01L29/66462 , H01L29/66522 , H01L29/7371 , H01L29/7841
摘要： Bi-stable static random access memory (SRAM) bit cells formed from III- V compounds and configured to achieve higher operating speeds are disclosed. In one aspect, a bi-stable SRAM bit cell includes substrate (202), a first well layer (204) formed over substrate from a III- V compound doped with a first type material, and a second well layer (206) formed over the first well layer (204) from a lll-V compound doped with a second type material. A channel layer (208) is formed over the second well layer (206) from a lll-V compound doped with the first type material. Source and drain regions (210, 214) are formed over the channel layer (208) from a lll-V compound doped with the first type material, and a gate region (224) is formed over the channel layer (208). Bipolar junction transistors (BJTs, 228(1) and 228(2)) are formed such that a data value can be stored in second well layer (206). A collector tap electrode (CL) is configured to provide access to collector of each BJT for reading or writing data.

7. 发明申请

WO2016049594A1 TWO-TRANSISTOR SRAM SEMICONDUCTOR STRUCTURE AND METHODS OF FABRICATION 审中-公开
标题翻译：双晶体SRAM半导体结构和制造方法
公开(公告)号：WO2016049594A1
公开(公告)日：2016-03-31
申请号：PCT/US2015/052488
申请日：2015-09-25
申请人： KILOPASS TECHNOLOGY, INC.
发明人： LUAN, Harry , BATEMAN, Bruce , AXELRAD, Valery , CHENG, Charlie , CHEVALLIER, Christophe
IPC分类号： G11C11/00 , G11C11/411 , G11C11/419 , G11C11/34 , G11C7/12
CPC分类号： H01L27/1104 , G11C11/39 , G11C11/41 , G11C11/411 , H01L21/8229 , H01L21/8249 , H01L27/0623 , H01L27/0821 , H01L27/0826 , H01L27/1025 , H01L27/1027 , H01L27/11 , H01L27/1116 , H01L29/0649 , H01L29/0804 , H01L29/083 , H01L29/0847 , H01L29/1004 , H01L29/1012 , H01L29/1095 , H01L29/66272 , H01L29/66386 , H01L29/732 , H01L29/742 , H01L29/7455
摘要： A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.
摘要翻译：基于用于SRAM集成电路的晶闸管的双晶体管存储单元及其制造方法一起被描述。存储器单元可以以具有浅沟槽隔离的半导体衬底中的晶闸管与MOS和双极选择晶体管的不同组合或不具有选择晶体管来实现。标准CMOS工艺技术可用于制造SRAM。

8. 发明申请

WO2010092555A2 FOUR-TRANSISTOR AND FIVE-TRANSISTOR BJT-CMOS ASYMMETRIC SRAM CELLS 审中-公开
标题翻译：四晶体和五晶体BJT-CMOS不对称SRAM电池
公开(公告)号：WO2010092555A2
公开(公告)日：2010-08-19
申请号：PCT/IB2010/050668
申请日：2010-02-15
申请人： ASA, Gil
发明人： ASA, Gil
CPC分类号： H01L21/8249 , G11C11/411 , G11C11/412 , H01L27/0623 , H01L27/0688 , H01L27/1025 , H01L27/11 , H03K3/288
摘要： A memory cell comprises asymmetric retention elements formed of bipolar junction transistors integrated with a CMOS transistor. The BJT transistors of the retention element may be vertically stacked. In one embodiment, the N region of two adjacent NPN BJT transistors may be connected to ground and may form a common emitter of the NPN BJT transistors while the P region of two adjacent PNP BJT transistors may be connected to high voltage and may form a common emitter of the PNP BJT transistors. For further compactness in one embodiment a base of one transistor doubles as a collector of another transistor. The retention element may have only a single bit line and a single write line, with no negative bit line. In some embodiments, a single inverter and only three transistors may form the retention element. Memory space may be cut approximately in half.
摘要翻译：存储单元包括由与CMOS晶体管集成的双极结型晶体管形成的不对称保留元件。保持元件的BJT晶体管可以是垂直堆叠的。在一个实施例中，两个相邻NPN BJT晶体管的N区可以连接到地，并且可以形成NPN BJT晶体管的公共发射极，而两个相邻的PNP BJT晶体管的P区可以连接到高电压并且可以形成公共 PNP BJT晶体管的发射极。为了在一个实施例中进一步的紧凑性，一个晶体管的基极可兼作另一个晶体管的集电极。保持元件可以仅具有单个位线和单个写入线，没有负位线。在一些实施例中，单个逆变器和仅三个晶体管可以形成保持元件。内存空间大约可以削减一半。

9. 发明申请

WO1993003486A1 BIPOLAR MEMORY CELL WITH ISOLATED PNP LOAD 审中-公开
标题翻译：具有隔离PNP负载的双极存储器单元
公开(公告)号：WO1993003486A1
公开(公告)日：1993-02-18
申请号：PCT/US1991009293
申请日：1991-12-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： INTERNATIONAL BUSINESS MACHINES CORPORATION , WONG, Robert, Chi-Foon
IPC分类号： G11C11/40
CPC分类号： H01L27/1025 , G11C11/4113 , G11C11/4116
摘要： A bipolar memory array and memory cell. The memory cell has a pair of cross coupled NPN storage transistors and a pair of PNP load transistors. The collector of each of the load transistors is connected to one of the storage transistors. A base, common to both load transistors, and the emitters of the storage transistors are connected to a drain line. The word line is connected to an emitter common to both of the load transistors. The cell is connected to a bit line pair through Schottky Barrier Diodes (SBD's) or, alternatively, through emitters of transistors which share a common base and common collector with the cross coupled storage transistors.

10. 发明申请

WO1985003168A1 NON-LINEAR LOAD ELEMENT FOR MEMORY CELL 审中-公开
标题翻译：用于存储单元的非线性负载元件
公开(公告)号：WO1985003168A1
公开(公告)日：1985-07-18
申请号：PCT/US1984002124
申请日：1984-12-20
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , WONG, Thomas, S., W.
IPC分类号： H01L29/56
CPC分类号： H01L27/0766 , G11C11/4116 , H01L27/1025 , H01L29/872
摘要： A bistable circuit element for integration into a static memory cell constructed of two transistors with cross-coupled base and collector regions and having a nonlinear load element (111) wherein the load element is a nonlinear surface load device. In particular, the nonlinear surface load device is a structure comprising a metallized contact segment (124) in semiconductor junction contact with a lightly doped monocrystalline silicon implant (119). The manufacturing technique approximates that of a Schottky diode with implant doping modified to increase the non-ideality factor m relative to the ideal of m = 1. The non-ideality factor m is limited so that the nonlinear surface load device does not degenerate into a linear ohmic.
摘要翻译：一种双稳态电路元件，用于集成到具有交叉耦合基极和集电极区域的两个晶体管构成的静态存储单元中，并具有非线性负载元件（111），其中负载元件是非线性表面负载装置。特别地，非线性表面负载装置是包括与轻掺杂的单晶硅植入物（119）的半导体结接触中的金属化接触段（124）的结构。制造技术近似于掺杂掺杂修正的肖特基二极管，其相对于m = 1的理想增加非理想因子m。非理想因子m受到限制，使得非线性表面负载器件不退化为线性欧姆

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