专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2019050848A1 BI-STABLE STATIC RANDOM ACCESS MEMORY (SRAM) BIT CELLS FORMED FROM III-V COMPOUNDS AND CONFIGURED TO ACHIEVE HIGHER OPERATING SPEEDS 审中-公开
公开(公告)号：WO2019050848A1
公开(公告)日：2019-03-14
申请号：PCT/US2018/049371
申请日：2018-09-04
申请人： QUALCOMM INCORPORATED
发明人： TAO, Gengming , LI, Xia , YANG, Bin
IPC分类号： H01L27/108 , H01L27/102 , G11C11/411 , H01L27/11 , H01L29/78
CPC分类号： H01L27/1104 , G11C11/4113 , G11C11/412 , G11C11/419 , H01L21/02543 , H01L21/02546 , H01L21/02634 , H01L27/0605 , H01L27/0705 , H01L27/1025 , H01L27/10802 , H01L27/11 , H01L29/0817 , H01L29/0821 , H01L29/0847 , H01L29/1004 , H01L29/1033 , H01L29/1095 , H01L29/20 , H01L29/205 , H01L29/41708 , H01L29/66318 , H01L29/66462 , H01L29/66522 , H01L29/7371 , H01L29/7841
摘要： Bi-stable static random access memory (SRAM) bit cells formed from III- V compounds and configured to achieve higher operating speeds are disclosed. In one aspect, a bi-stable SRAM bit cell includes substrate (202), a first well layer (204) formed over substrate from a III- V compound doped with a first type material, and a second well layer (206) formed over the first well layer (204) from a lll-V compound doped with a second type material. A channel layer (208) is formed over the second well layer (206) from a lll-V compound doped with the first type material. Source and drain regions (210, 214) are formed over the channel layer (208) from a lll-V compound doped with the first type material, and a gate region (224) is formed over the channel layer (208). Bipolar junction transistors (BJTs, 228(1) and 228(2)) are formed such that a data value can be stored in second well layer (206). A collector tap electrode (CL) is configured to provide access to collector of each BJT for reading or writing data.

2. 发明申请

WO2013058640A2 METHOD FOR THE EXTRACTION, VERIFICATION AND COUNTING OF DIALYZED LEUKOCYTE EXTRACT ORIGINATING FROM SHARK SPLEEN IN ORDER TO OBTAIN POTENTIALIZED TRANSFER FACTOR, SPECIFICALLY DESIGNED FOR USE AS TREATMENT AGAINST THE DISEASE KNOWN AS ASTHMA 审中-公开
标题翻译：用于从鲨鱼脾脏中提取，鉴定和计算由鲨鱼脾脏产生的沉淀的白血球提取物以便获得潜在的转移因子的方法，特别设计用于治疗被称为哮喘的疾病
公开(公告)号：WO2013058640A2
公开(公告)日：2013-04-25
申请号：PCT/MX2012000091
申请日：2012-09-20
申请人： ZEPEDA LOPEZ HECTOR MANUEL
发明人： ZEPEDA LOPEZ HECTOR MANUEL
CPC分类号： H01L29/41708 , H01L29/0817 , H01L29/201 , H01L29/205 , H01L29/207 , H01L29/42304 , H01L29/66318 , H01L29/7371
摘要： A leukocyte extract containing polypeptides equal to or less than 10,000 Daltons originating from shark spleen and the use thereof as a drug in the treatment of the disease known as asthma comprises, furthermore, a method for the extraction and processing of dialyzable leukocyte extract from sharks, in order to obtain a drug based on leukocyte-cell extract for treating symptoms of the disease known by the name "asthma".
摘要翻译：此外，含有来自鲨鱼脾的等于或小于10,000道尔顿的多肽的白细胞提取物及其作为用于治疗称为哮喘的疾病的药物的用途还包括从鲨鱼中提取和处理可透析白细胞提取物的方法，以获得基于白细胞提取物的药物，用于治疗以“哮喘”命名的疾病症状。

3. 发明申请

WO2005022580A1 HETEROJUNCTION BIPOLAR TRANSISTOR WITH TUNNELLING MIS EMITTER JUNCTION 审中-公开
标题翻译：异质结双极性晶体管，带有隧道MIS发射极接线
公开(公告)号：WO2005022580A1
公开(公告)日：2005-03-10
申请号：PCT/AU2004/001184
申请日：2004-09-02
申请人： EPITACTIX PTY LTD , CUNNINGHAM, Shaun, Joseph
发明人： CUNNINGHAM, Shaun, Joseph
IPC分类号： H01L29/737
CPC分类号： H01L29/7311 , H01L29/0817 , H01L29/0895 , H01L29/66318 , H01L29/7371
摘要： A method and structure are provided for a high performance heterojunction bipolar transistor which is suited to compound semiconductor systems such as gallium arsenide (GaAs) and which utilises an emitter junction formed from a plurality of metal layers and a plurality of ultra-thin insulating layers. The metal layers chosen have work functions which form a tunnelling Metal-Insulator-Semiconductor Junction when deposited on top of an ultra-thin insulating layer. The insulating layer may be made from a rare-earth oxide such as gadolinium oxide (Gd 2 O 3 ) which is epitaxially grown on a compound semiconductor substrate and possibly covered with a second ultra-thin insulating layer.
摘要翻译：提供了一种用于高性能异质结双极晶体管的方法和结构，该晶体管适用于诸如砷化镓（GaAs）的化合物半导体系统，并且其利用由多个金属层形成的发射极结和多个超薄绝缘层。所选择的金属层具有功函数，当沉积在超薄绝缘层上时，形成隧道式金属 - 绝缘体 - 半导体结。绝缘层可以由在化合物半导体衬底上外延生长并且可能被覆盖有氧化钆（Gd 2 O 3）的稀土氧化物（Gd 2 O 3：第二层超薄绝缘层。

4. 发明申请

WO2007128075A3 METHOD AND APPARATUS FOR MANUFACTURE OF SEMICONDUCTORS AND RESULTING STRUCTURES, DEVICES, CIRCUITS, AND COMPONENTS 审中-公开
标题翻译：用于制造半导体和结构的方法和装置，器件，电路和组件
公开(公告)号：WO2007128075A3
公开(公告)日：2007-12-27
申请号：PCT/AU2007000613
申请日：2007-05-08
申请人： EPITACTIX PTY LTD , CUNNINGHAM SHAUN JOSEPH
发明人： CUNNINGHAM SHAUN JOSEPH
IPC分类号： H01L27/00 , H01L29/32 , H01L29/735
CPC分类号： H01L29/7371 , H01L27/0605 , H01L29/0817 , H01L29/1029 , H01L29/20 , H01L29/6631 , H01L29/66318 , H01L29/735 , H01L29/737 , H01L29/812
摘要： The present invention relates to semiconductor structures, devices, circuits and components and the manufacture or fabrication of same. In one form, the invention is suitable for use in structures, devices, integrated circuits, components and manufacturing processes relating to compound semiconductor materials such as gallium arsenide (GaAs) and may equally apply to other semiconductor materials such as, for instance, indium phosphide (InP), gallium nitride (GaN), silicon carbide (SiC) and also silicon (Si). A first embodiment relates, in particular, to improved means of fabrication of bipolar transistor devices such as for example, npn and pnp bipolar transistors in a single process. A second preferred embodiment is related in general to control mechanisms for use in relation to HBT's, for example those used in power amplifiers. A third preferred embodiment provides a manufacturing method and structure for a compound semiconductor heterojunction bipolar transistor (HBT) which provides scalable device feature size, reduced manufacturing complexity and increased operating voltage. Fourth and fifth preferred embodiment relates to integrated HBT/FET fabrication technologies.
摘要翻译：本发明涉及半导体结构，器件，电路和元件及其制造或制造。在一种形式中，本发明适用于与诸如砷化镓（GaAs）的化合物半导体材料相关的结构，器件，集成电路，部件和制造工艺，并且可以同样适用于其它半导体材料，例如磷化铟（InP），氮化镓（GaN），碳化硅（SiC）以及硅（Si）。第一实施例特别涉及在单个工艺中制造双极晶体管器件，例如npn和pnp双极晶体管的改进方法。第二优选实施例通常涉及用于关于HBT的控制机构，例如用于功率放大器中的那些。第三优选实施例提供了一种化合物半导体异质结双极晶体管（HBT）的制造方法和结构，其提供可扩展的器件特征尺寸，降低的制造复杂性和增加的工作电压。第四和第五优选实施例涉及集成的HBT / FET制造技术。

5. 发明申请

WO2007128075A2 METHOD AND APPARATUS FOR MANUFACTURE OF SEMICONDUCTORS AND RESULTING STRUCTURES, DEVICES, CIRCUITS, AND COMPONENTS 审中-公开
标题翻译：用于制造半导体和结构的方法和装置，器件，电路和组件
公开(公告)号：WO2007128075A2
公开(公告)日：2007-11-15
申请号：PCT/AU2007/000613
申请日：2007-05-08
申请人： EPITACTIX PTY LTD , CUNNINGHAM, Shaun, Joseph
发明人： CUNNINGHAM, Shaun, Joseph
CPC分类号： H01L29/7371 , H01L27/0605 , H01L29/0817 , H01L29/1029 , H01L29/20 , H01L29/6631 , H01L29/66318 , H01L29/735 , H01L29/737 , H01L29/812
摘要： The present invention relates to semiconductor structures, devices, circuits and components and the manufacture or fabrication of same. In one form, the invention is suitable for use in structures, devices, integrated circuits, components and manufacturing processes relating to compound semiconductor materials such as gallium arsenide (GaAs) and may equally apply to other semiconductor materials such as, for instance, indium phosphide (InP), gallium nitride (GaN), silicon carbide (SiC) and also silicon (Si). A first embodiment relates, in particular, to improved means of fabrication of bipolar transistor devices such as for example, npn and pnp bipolar transistors in a single process. A second preferred embodiment is related in general to control mechanisms for use in relation to HBT's, for example those used in power amplifiers. A third preferred embodiment provides a manufacturing method and structure for a compound semiconductor heterojunction bipolar transistor (HBT) which provides scalable device feature size, reduced manufacturing complexity and increased operating voltage. Fourth and fifth preferred embodiment relates to integrated HBT/FET fabrication technologies
摘要翻译：本发明涉及半导体结构，器件，电路和元件及其制造或制造。在一种形式中，本发明适用于与诸如砷化镓（GaAs）的化合物半导体材料相关的结构，器件，集成电路，部件和制造工艺，并且可以同样适用于其它半导体材料，例如磷化铟（InP），氮化镓（GaN），碳化硅（SiC）以及硅（Si）。第一实施例特别涉及在单个工艺中制造双极晶体管器件，例如npn和pnp双极晶体管的改进方法。第二优选实施例通常涉及用于关于HBT的控制机构，例如用于功率放大器中的那些。第三优选实施例提供了一种化合物半导体异质结双极晶体管（HBT）的制造方法和结构，其提供可扩展的器件特征尺寸，降低的制造复杂性和增加的工作电压。第四和第五优选实施例涉及集成的HBT / FET制造技术

6. 发明申请

WO2007076576A1 METHOD AND STRUCTURE FOR A HIGH PERFORMANCE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：高性能半导体器件的方法和结构
公开(公告)号：WO2007076576A1
公开(公告)日：2007-07-12
申请号：PCT/AU2006/001976
申请日：2006-12-29
申请人： EPITACTIX PTY LTD , CUNNINGHAM, Shaun, Joseph
发明人： CUNNINGHAM, Shaun, Joseph
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L29/7371 , H01L29/0817 , H01L29/66318
摘要： The present invention relates generally to integrated circuit devices. In one form, the invention provides a manufacturing method and resulting structure for a compound semiconductor heterojunction bipolar transistor (HBT) which provides scalable device feature size and reduced manufacturing complexity. A preferred embodiment of the present invention provides for the fabrication of an integrated circuit device comprising: converting at least one portion of a layered arrangement of semiconductor materials to an insulating state to form an isolation region and at least one isolated device bounded by the isolation region; subsequently providing at least one layer of material operatively associated with the isolated device and which extends across an isolation region boundary to form at least one region of overlap within the isolation region. Consequently, embodiments of the present invention provide for improved precision of device alignment, reduced emitter widths for improved performance and enlarged metal interconnects for circuit connectivity and heat dissipation.
摘要翻译：本发明一般涉及集成电路器件。在一种形式中，本发明提供了一种化合物半导体异质结双极晶体管（HBT）的制造方法和结果，其提供可扩展的器件特征尺寸和降低的制造复杂度。本发明的优选实施例提供一种集成电路器件的制造方法，包括：将至少一部分半导体材料的分层布置转换成绝缘状态以形成隔离区域，以及至少一个被隔离区限定的隔离器件 ; 随后提供与所述隔离装置可操作地相关联并且跨越隔离区边界延伸的至少一层材料，以形成所述隔离区域内的至少一个重叠区域。因此，本发明的实施例提供了器件对准的改进的精度，用于改善性能的减小的发射极宽度以及用于电路连接和散热的扩大的金属互连。

7. 发明申请

WO2007056017A2 BANDGAP AND RECOMBINATION ENGINEERED EMITTER LAYERS FOR SI-GE HBT PERFORMANCE OPTIMIZATION 审中-公开
标题翻译：用于SI-GE HBT性能优化的带状和重组工程发射器层
公开(公告)号：WO2007056017A2
公开(公告)日：2007-05-18
申请号：PCT/US2006/042682
申请日：2006-10-31
申请人： ATMEL CORPORATION , ENICKS, Darwin, Gene , CARVER, Damian
发明人： ENICKS, Darwin, Gene , CARVER, Damian
IPC分类号： H01L21/331
CPC分类号： H01L29/7378 , H01L29/0817 , H01L29/1004 , H01L29/66242
摘要： A method for fabricating a heterojunction bipolar transistor (HBT) is provided. The method includes providing a substrate including a collector region; forming a compound base region over the collector region; and forming an emitter region over the compound base region including forming a first emitter layer within the emitter region and doping the first emitter layer with a pre-determined percentage of at least one element associated with the compound base region. In one implementation, an emitter region is formed including multiple emitter layers to enhance a surface recombination surface area within the emitter region.
摘要翻译：提供了一种用于制造异质结双极晶体管（HBT）的方法。该方法包括提供包括集电极区域的衬底; 在集电极区域上形成复合基极区域; 以及在复合基极区域上方形成发射极区域，包括在发射极区域内形成第一发射极层，并用预定百分比的与复合基极区域相关的至少一个元素掺杂第一发射极层。在一个实施方式中，形成包括多个发射极层的发射极区域以增强发射极区域内的表面复合表面区域。

8. 发明申请

WO2006060208A2 LOW TURN-ON VOLTAGE, NON-ELECTRON BLOCKING DOUBLE HBT STRUCTURE 审中-公开
标题翻译：低导通电压，非电子阻塞双HBT结构
公开(公告)号：WO2006060208A2
公开(公告)日：2006-06-08
申请号：PCT/US2005/042062
申请日：2005-11-18
申请人： NORTHROP GRUMMAN CORPORATION , SAWDAI, Donald, J. , GUTIERREZ-AITKEN, Augusto, L. , CHIN, Tsung-pei
发明人： SAWDAI, Donald, J. , GUTIERREZ-AITKEN, Augusto, L. , CHIN, Tsung-pei
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L29/7371 , H01L29/0817 , H01L29/1004
摘要： A double heterojunction bipolar transistor structure having desirable properties of a low base-emitter turn-on voltage and no electron blocking discontinuities in the base-collector junction. These properties are achieved by selecting base, emitter and collector materials to provide a bandgap profile that exhibits abrupt transitions at the heterojunctions, such that both abrupt transitions are due to transitions in the valence band edge of the bandgap, but not in the conductive band edge of the bandgap.
摘要翻译：具有低基极 - 发射极接通电压和基极 - 集电极结中电子阻挡不连续性的所需特性的双异质结双极晶体管结构。这些性质通过选择基极，发射极和集电极材料来实现，以提供在异质结处表现出突变的带隙分布，使得两个突变都是由于带隙的价带边缘中的跃迁，而不是导电带边缘的带隙。

9. 发明申请

WO2005041261A2 BiFET INCLUDING A FET HAVING INCREASED LINEARITY AND MANUFACTURABILITY 审中-公开
标题翻译：包括具有增加的线性和可制造性的FET的BiFET
公开(公告)号：WO2005041261A2
公开(公告)日：2005-05-06
申请号：PCT/US2004/032717
申请日：2004-10-04
申请人： SKYWORKS SOLUTIONS, INC. , ZAMPARDI, Peter, J. , PIERSON, Richard, N.
发明人： ZAMPARDI, Peter, J. , PIERSON, Richard, N.
IPC分类号： H01L
CPC分类号： H01L27/0623 , H01L27/0605 , H01L29/0817 , H01L29/7371 , H01L29/812
摘要： According to one exemplary embodiment, a BiFET situated on a substrate comprises an emitter layer segment situated over the substrate, where the emitter layer segment comprises a semiconductor of a first type. The HBT further comprises a first segment of an etch stop layer, where the first segment of the etch stop layer comprises InGaP. The BiFET further comprises a FET situated over the substrate, where the FET comprises source and drain regions, where a second segment of the etch stop layer is situated under the source and drain regions, and where the second segment of the etch stop layer comprises InGaP. The FET further comprises a semiconductor layer of a second type situated under the second segment of the etch stop layer. The etch stop layer increases linearity of the FET and does not degrade electron current flow in the HBT.
摘要翻译：根据一个示例性实施例，位于衬底上的BiFET包括位于衬底上的发射极层段，其中发射极层段包括第一类型的半导体。 HBT还包括蚀刻停止层的第一段，其中蚀刻停止层的第一段包括InGaP。 BiFET还包括位于衬底上方的FET，其中FET包括源区和漏区，其中蚀刻停止层的第二段位于源极和漏极区之下，并且其中蚀刻停止层的第二段包括InGaP 。 FET还包括位于蚀刻停止层的第二段下方的第二类型的半导体层。蚀刻停止层增加了FET的线性度，并且不会降低HBT中的电子流量。

10. 发明申请

WO2014089813A1 一种晶体管及其制造方法审中-公开
公开(公告)号：WO2014089813A1
公开(公告)日：2014-06-19
申请号：PCT/CN2012/086610
申请日：2012-12-14
申请人：复旦大学
发明人：吴东平 , 付超超 , 张卫 , 张世理
IPC分类号： H01L29/417 , H01L29/43 , H01L21/28
CPC分类号： H01L29/7378 , H01L21/02532 , H01L21/0257 , H01L21/02598 , H01L21/0262 , H01L21/28518 , H01L21/2855 , H01L29/0817 , H01L29/0821 , H01L29/1004 , H01L29/165 , H01L29/167 , H01L29/41708 , H01L29/456 , H01L29/66242 , H01L29/7371
摘要：提供一种晶体管（100）及其制造方法。晶体管（100）具有倒置异质结结构，其中，在形成基极（130）层和集电极（140）层之前形成发射极（120）层。这种倒置的异质结结构，可以采用ALE工艺通过在预先形成的外延单晶金属硅化物（110）上形成发射极（120）层，在发射极（120）层上形成基极（130）层，在基极（130）层上形成集电极（140）层制备得到。通过为关键的基区形貌和掺杂分布控制提供更好的热预算，可以获得更高的截止频率（f T ）；通过最小化集电区和基区的接触面积，可以显著减少寄生电容、提高最高振荡频率（f max ）。这样可以显著提高晶体管的频率特性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式