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1. 发明申请

WO8702487A3 CONTROL SYSTEM FOR CHAINED CIRCUIT MODULES 审中-公开
标题翻译：链式电路模块控制系统
公开(公告)号：WO8702487A3
公开(公告)日：1987-06-18
申请号：PCT/GB8600601
申请日：1986-10-06
申请人： ANAMARTIC LTD , MACDONALD NEAL
发明人： MACDONALD NEAL
IPC分类号： G11C29/00 , G06F11/20 , G06F15/60
CPC分类号： G11C29/006
摘要： A wafer-scale integrated circuit comprises a few hundred modules which can be connected into a long chain by commands sent from a terminal (XMIT) to the modules along a transmit path set up by way of module inputs from neighbouring modules and outputs thereto, only one of which is enabled by one of four selection signals. The transmit path normally follows a route through a main chain of modules (M0 to M15), as shown by a full line. However, commands may be sent to nodal modules (M0, M6 and M10) to make alternative direction selections there at, so as to obtain access to modules (M16) etc. in spur chains. Commands are addressed to the modules in accordance with their distances (F) from (XMIT). Spurs may themselves include nodal moduls such as (M17). The normal and alternative direction selections are listed in a stored table which is used by a command unit to access any desired module and then restore the main chain (M0 - M15). In an alternative embodiment, the stored table lists individually for every module the sequence of direction selections needed to obtain access thereto by the shortest route avoiding unusable modules (marked with a cross).
摘要翻译：晶圆级集成电路包括几百个模块，这些模块可以通过从终端（XMIT）沿着通过来自相邻模块的模块输入建立的发送路径向模块发送命令并将其输出到长链中而连接成长链其中之一由四个选择信号之一启用。发送路径通常遵循通过主链模块（M0到M15）的路由，如实线所示。然而，可以将命令发送到节点模块（M0，M6和M10）以在那里进行替代的方向选择，以便获得对短链中的模块（M16）等的访问。根据距离（XMIT）的距离（F）将命令发给模块。马刺本身可能包括节点模块，如（M17）。存储的表格中列出了正常和替代方向选择，命令单元使用该表格存取任何所需的模块，然后恢复主链（M0-M15）。在替代实施例中，所存储的表单独地为每个模块列出需要通过避免不可用模块（用十字标记）的最短路线获得对其的访问所需的方向选择序列。

2. 发明申请

WO1987002487A2 CONTROL SYSTEM FOR CHAINED CIRCUIT MODULES 审中-公开
标题翻译：链路模块控制系统
公开(公告)号：WO1987002487A2
公开(公告)日：1987-04-23
申请号：PCT/GB1986000601
申请日：1986-10-06
申请人： ANAMARTIC LIMITED , MACDONALD, Neal
发明人： ANAMARTIC LIMITED
IPC分类号： G06F11/20
CPC分类号： G11C29/006
摘要： A wafer-scale integrated circuit comprises a few hundred modules which can be connected into a long chain by commands sent from a terminal (XMIT) to the modules along a transmit path set up by way of module inputs from neighbouring modules and outputs thereto, only one of which is enabled by one of four selection signals. The transmit path normally follows a route through a main chain of modules (M0 to M15), as shown by a full line. However, commands may be sent to nodal modules (M0, M6 and M10) to make alternative direction selections there at, so as to obtain access to modules (M16) etc. in spur chains. Commands are addressed to the modules in accordance with their distances (F) from (XMIT). Spurs may themselves include nodal moduls such as (M17). The normal and alternative direction selections are listed in a stored table which is used by a command unit to access any desired module and then restore the main chain (M0 - M15). In an alternative embodiment, the stored table lists individually for every module the sequence of direction selections needed to obtain access thereto by the shortest route avoiding unusable modules (marked with a cross).
摘要翻译：晶圆级集成电路包括几百个模块，可以通过从终端（XMIT）向模块连接到沿着通过相邻模块的模块输入建立的发送路径和仅向其输出的命令连接到长链中其中之一由四个选择信号中的一个启用。传输路径通常遵循通过主链（M0至M15）的路由，如全行所示。然而，可以将命令发送到节点模块（M0，M6和M10）以在其中进行替代方向选择，以便获得对支线链路中的模块（M16）等的访问。根据（XMIT）的距离（F）将命令发送给模块。马刺本身可以包括诸如（M17）的节点模式。正常和替代方向选择列在存储表中，命令单元用于访问任何所需模块，然后恢复主链（M0 - M15）。在替代实施例中，所存储的表单独列出了通过避免不可用模块（用十字标记）的最短路由获得对其的访问所需的方向选择顺序。

3. 发明申请

WO8700674A3 WAFER-SCALE INTEGRATED CIRCUIT MEMORY 审中-公开
标题翻译：超大规模集成电路存储器
公开(公告)号：WO8700674A3
公开(公告)日：1987-03-26
申请号：PCT/GB8600400
申请日：1986-07-11
申请人： ANAMARTIC LTD , BRENT MICHAEL , MACDONALD NEAL
发明人： BRENT MICHAEL , MACDONALD NEAL
IPC分类号： G06F11/20 , G11C7/00 , G11C7/22 , G11C8/00 , G11C8/12 , G11C8/18 , G11C11/406 , G11C29/00
CPC分类号： G11C8/00 , G11C7/00 , G11C7/22 , G11C8/12 , G11C8/18 , G11C11/406 , G11C29/006
摘要： A wafer scale integrated circuit comprises a few hundred modules (10) which can be connected into a long chain by commands sent to the modules along a transmit path set up by way of module inputs (XINN, XINE, XINS, XINW) from neighbouring modules and outputs thereto (XOUTN, XOUTE, XOUTS, XOUTW), only one of which is enabled by one of four selection signals (SELN, SELE, SELS, SELW) acting both on transmit path logic (20) and on receive path logic (21) in a return path. Each module includes configuration logic (22) which decodes commands providing the selection signals (SELN, etc), a READ signal and a WRITE signal. The configuration logic (22) is addressed when a bit is presented thereto by the transmit path simultaneously with assertion of a signal (CMND) which is supplied globally to all modules. The address configuration logic clocks the bit along a shift register and the selected command is determined by the position of the bit at the time that the global signal (CMND) is terminated. Each module includes a memory unit (23) including a free running address counter. When the WRITE command appears a data stream on the transmit path is read into the memory. When READ appears, the contents of the memory are read out onto the return path. Memory refresh occurs conventionally under control of the free-running address counter. In order to avoid heavy current in any of the power distribution conductors on the wafer, the count cycles of the free-running address counters are staggered.

4. 发明申请

WO1990012399A1 CONTROL SYSTEM FOR AN ARRAY OF CIRCUIT MODULES 审中-公开
标题翻译：电路模块阵列控制系统
公开(公告)号：WO1990012399A1
公开(公告)日：1990-10-18
申请号：PCT/GB1990000539
申请日：1990-04-09
申请人： MV LIMITED , MACDONALD, Neal, Hugh
发明人： MV LIMITED
IPC分类号： G11C07/00
CPC分类号： G11C7/22 , G11C8/12 , G11C8/18
摘要： A digital computer can control an array of circuit modules through the use of two sets of pan-array signals, known as R and C. The C lines run vertically and connect to all modules in the same column, and the R lines run horizontally and connect to all chips in the same row of the array. By asserting a particular pair of R and C lines, a specific module can be selected to receive control data from one of these lines. Each module includes a support circuit to latch when R and C are asserted together, and then to route data from one line into a variety of storage registers. A particular example is described that uses the control system as the basis of a data storage and retrieval system.
摘要翻译：数字计算机可以通过使用两组pan-array信号（称为R和C）来控制电路模块阵列.C线垂直运行并连接到同一列中的所有模块，R线水平运行，连接到阵列的同一行中的所有芯片。通过断言特定的一对R和C线，可以选择一个特定的模块来从这些线路之一接收控制数据。每个模块包括一个支持电路，当R和C一起被断言时锁存，然后将数据从一行路由到各种存储寄存器。描述了使用控制系统作为数据存储和检索系统的基础的特定示例。

5. 发明申请

WO1992008193A1 A FAULT TOLERANT DATA STORAGE SYSTEM 审中-公开
标题翻译：一个容错数据存储系统
公开(公告)号：WO1992008193A1
公开(公告)日：1992-05-14
申请号：PCT/GB1991001929
申请日：1991-11-04
申请人： MV LIMITED , MACDONALD, Neal, Hugh
发明人： MV LIMITED
IPC分类号： G06F11/20
CPC分类号： G11C29/76
摘要： A fault tolerant random access data storage system comprises a plurality of rows of memory chips (31) plus a first spare row of chips (32) and a second spare row of chips (33), each chip comprising an array of memory locations. A controller (25) addresses the chips with the logical addresses of the rows within the arrays being skewed relative to their physical addresses but in a different manner for the different rows of chips, and with the logical addresses of the columns within the arrays being skewed relative to their physical addresses but in a different manner for the different rows of chips. The locations of faults within the chips are recorded so that if a selected array row in a selected chip row (31) is faulty, then a replacement row in the first spare row of chips (32) is selected instead, and if a selected array column in a selected chip row (31) is faulty, then a replacement column in the second spare row of chips (33) is selected instead.
摘要翻译：容错随机存取数据存储系统包括多行存储器芯片（31）加上第一备用行芯片（32）和第二备用行芯片（33），每个芯片包括一组存储器位置。控制器（25）以阵列内的行的逻辑地址相对于它们的物理地址进行寻址，但以不同的方式对于不同行的码片进行寻址，并且阵列内的列的逻辑地址偏斜相对于它们的物理地址，但以不同的方式对于不同行的芯片。记录芯片内的故障位置，使得如果选定的芯片行（31）中选定的阵列行有故障，则替代地选择第一备用行芯片（32）中的替换行，并且如果选择的阵列选择的芯片行（31）中的列是故障的，则替代地选择第二备用行芯片（33）中的替换列。

6. 发明申请

WO1991001023A1 A FAULT TOLERANT DATA STORAGE SYSTEM 审中-公开
标题翻译：一个容错数据存储系统
公开(公告)号：WO1991001023A1
公开(公告)日：1991-01-24
申请号：PCT/GB1990001051
申请日：1990-07-06
申请人： MV LIMITED , MACDONALD, Neal, Hugh
发明人： MV LIMITED
IPC分类号： G06F11/20
CPC分类号： G11C29/76
摘要： A fault tolerant data storage system comprises an array of memory chips having a plurality of rows and columns, each row of memory chips CO to CN having a spare chip CS. Each chip comprises an array of memory locations some of which may be faulty. When simultaneously writing or reading data via parallel data lines DO-DN to the respective chips, a map MAP identifies any chip having a fault in the addressed location (e.g. in the addressed column) and connects the data line to a good location in the spare chip. The logical addresses for the chips are skewed differently for each other as compared with their physical addresses, such that there are not coincident faults in the different chips e.g. only a single chip in a row has a fault in the columns being simultaneously addressed in the respective chips of that row.
摘要翻译：容错数据存储系统包括具有多个行和列的存储器芯片阵列，每行存储器芯片CO至CN具有备用芯片CS。每个芯片包括一些存储器位置，其中一些可能是有缺陷的。当通过并行数据线DO-DN将数据同时写入或读取到相应的芯片时，映射MAP识别在寻址位置（例如，寻址列）中具有故障的任何芯片，并将数据线连接到备用的良好位置芯片。与其物理地址相比，芯片的逻辑地址彼此不同，使得不同的芯片中不存在重合故障，例如，只有一行中的单个芯片在该行的各个芯片中同时处理列中的故障。

7. 发明申请

WO1987003716A2 FAULT TOLERANT MEMORY SYSTEM 审中-公开
标题翻译：容错记忆系统
公开(公告)号：WO1987003716A2
公开(公告)日：1987-06-18
申请号：PCT/GB1986000760
申请日：1986-12-12
申请人： ANAMARTIC LIMITED , MACDONALD, Neal
发明人： ANAMARTIC LIMITED
IPC分类号： G06F11/00
CPC分类号： G11C29/70 , G11C29/006 , G11C29/86
摘要： A digital computer (15) can write a block of data to a RAM (10), or read a block therefrom, via a serial/parallel converter (17) which is word serial, bit parallel on the computer side and bit serial on the RAM side. The RAM is addressed by a free-running address counter (18) clocked by clock pulses WCK. A fault masking circuit (19) enables faulty cells in the RAM (10) to be masked out. Data specific to the RAM (10) causes the clock pulses WCK to be selectively gated for providing bit rate clock pulses GCK to the converter (17). These pulses are divided down to produce pulses BCK at word rate. The invention is particularly useful in a wafer scale integrated circuit comprising a large number of RAMs (10) served by a single fault masking circuit (19) with tabulated data defining the memory cells to be masked out on a memory by memory basis.
摘要翻译：数字计算机（15）可以通过串行/并行转换器（17）将数据块写入RAM（10）或从其读取块，该串行/并行转换器（17）是字串行的，位于计算机侧的位并行 RAM侧。 RAM由时钟脉冲WCK时钟的自由运行的地址计数器（18）寻址。故障屏蔽电路（19）使得RAM（10）中的故障单元被屏蔽掉。特定于RAM（10）的数据使得时钟脉冲WCK被选择性地选通，以将比特率时钟脉冲GCK提供给转换器（17）。这些脉冲被分频以产生字速率BCK。本发明在包括由单个故障屏蔽电路（19）服务的大量RAM（10）的晶片级集成电路中特别有用，其中列表数据通过存储器定义在存储器上被屏蔽的存储器单元。

8. 发明申请

WO8703716A3 FAULT TOLERANT MEMORY SYSTEM 审中-公开
标题翻译：容错记忆系统
公开(公告)号：WO8703716A3
公开(公告)日：1987-07-16
申请号：PCT/GB8600760
申请日：1986-12-12
申请人： ANAMARTIC LTD , MACDONALD NEAL
发明人： MACDONALD NEAL
IPC分类号： G06F12/16 , G06F11/00 , G06F11/16 , G11C29/00
CPC分类号： G11C29/70 , G11C29/006 , G11C29/86
摘要： A digital computer (15) can write a block of data to a RAM (10), or read a block therefrom, via a serial/parallel converter (17) which is word serial, bit parallel on the computer side and bit serial on the RAM side. The RAM is addressed by a free-running address counter (18) clocked by clock pulses WCK. A fault masking circuit (19) enables faulty cells in the RAM (10) to be masked out. Data specific to the RAM (10) causes the clock pulses WCK to be selectively gated for providing bit rate clock pulses GCK to the converter (17). These pulses are divided down to produce pulses BCK at word rate. The invention is particularly useful in a wafer scale integrated circuit comprising a large number of RAMs (10) served by a single fault masking circuit (19) with tabulated data defining the memory cells to be masked out on a memory by memory basis.

9. 发明申请

WO1987000674A2 WAFER-SCALE INTEGRATED CIRCUIT MEMORY 审中-公开
标题翻译：超大规模集成电路存储器
公开(公告)号：WO1987000674A2
公开(公告)日：1987-01-29
申请号：PCT/GB1986000400
申请日：1986-07-11
申请人： ANAMARTIC LIMITED , BRENT, Michael , MACDONALD, Neal
发明人： ANAMARTIC LIMITED
IPC分类号： G11C07/00
CPC分类号： G11C8/00 , G11C7/00 , G11C7/22 , G11C8/12 , G11C8/18 , G11C11/406 , G11C29/006
摘要： A wafer scale integrated circuit comprises a few hundred modules (10) which can be connected into a long chain by commands sent to the modules along a transmit path set up by way of module inputs (XINN, XINE, XINS, XINW) from neighbouring modules and outputs thereto (XOUTN, XOUTE, XOUTS, XOUTW), only one of which is enabled by one of four selection signals (SELN, SELE, SELS, SELW) acting both on transmit path logic (20) and on receive path logic (21) in a return path. Each module includes configuration logic (22) which decodes commands providing the selection signals (SELN, etc), a READ signal and a WRITE signal. The configuration logic (22) is addressed when a bit is presented thereto by the transmit path simultaneously with assertion of a signal (CMND) which is supplied globally to all modules. The address configuration logic clocks the bit along a shift register and the selected command is determined by the position of the bit at the time that the global signal (CMND) is terminated. Each module includes a memory unit (23) including a free running address counter. When the WRITE command appears a data stream on the transmit path is read into the memory. When READ appears, the contents of the memory are read out onto the return path. Memory refresh occurs conventionally under control of the free-running address counter. In order to avoid heavy current in any of the power distribution conductors on the wafer, the count cycles of the free-running address counters are staggered.
摘要翻译：晶圆级集成电路包括几百个模块（10），其可以通过沿着通过模块输入（XINN，XINE，XINS，XINW）设置的传输路径从相邻模块发送到模块的命令连接到长链并且向其输出（XOUTN，XOUTE，XOUTS，XOUTW），其中仅一个由在发送路径逻辑（20）和接收路径逻辑（21）上起作用的四个选择信号（SELN，SELE，SELS，SELW）中的一个使能）在返回路径。每个模块包括对提供选择信号（SELN等）的命令，READ信号和WRITE信号进行解码的配置逻辑（22）。当通过发送路径同时向所有模块全局提供的信号（CMND）的断言同时向其发送位时，配置逻辑（22）被寻址。地址配置逻辑沿着移位寄存器对该位进行时钟，并且所选择的命令由全局信号（CMND）终止时的位的位置确定。每个模块包括包括自由运行的地址计数器的存储器单元（23）。当WRITE命令出现时，发送路径上的数据流被读入存储器。当READ出现时，内存的内容被读出到返回路径上。存储器刷新通常在自由运行地址计数器的控制下发生。为了避免晶片上的任何配电导体中的大电流，自由运行的地址计数器的计数周期是交错的。

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