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1. 发明申请

WO2016053533A1 APPARATUS AND METHODS FOR SENSING HARD BIT AND SOFT BITS 审中-公开
标题翻译：用于传感硬头和软件位置的装置和方法
公开(公告)号：WO2016053533A1
公开(公告)日：2016-04-07
申请号：PCT/US2015/047626
申请日：2015-08-30
申请人： SANDISK 3D LLC
发明人： SIAU, Chang , LEE, Jeffrey Koon Yee , YAN, Tianhong , CHEN, Yingchang , BALAKRISHNAN, Gopinath , LIU, Tz-Yi
IPC分类号： G11C11/16 , G11C13/00 , G11C16/28 , G11C16/32
CPC分类号： G11C13/004 , G11C13/0028 , G11C13/0061 , G11C16/28 , G11C16/32 , G11C27/02 , G11C2013/0054
摘要： A method is provided for reading a hard bit and N soft bits of a memory cell of a nonvolatile memory system in response to a single read command in a total time corresponding to a single read latency period and N + 1 data transfer times, the method comprising: generating a sense signal proportional to a current of the memory cell; generating a reference signal that comprises 2N + 1 distinct reference signal values; generating a comparison signal by comparing the sense signal and the reference signal; sampling the comparison signal to generate 2N + 1 data values; and determining the hard bit and the N soft bits based on the 2N + 1 data values.
摘要翻译：提供了一种用于在对应于单个读等待时间周期和N + 1个数据传送时间的总时间内响应于单个读取命令来读取非易失性存储器系统的存储器单元的硬比特和N个软比特的方法，该方法包括：产生与所述存储器单元的电流成比例的感测信号; 生成包括2N + 1个不同参考信号值的参考信号; 通过比较感测信号和参考信号来产生比较信号; 对比较信号进行采样以产生2N + 1个数据值; 以及基于2N + 1个数据值来确定硬比特和N个软比特。

2. 发明申请

WO2014130604A1 SMART READ SCHEME FOR MEMORY ARRAY SENSING 审中-公开
标题翻译：用于记忆阵列感测的SMART阅读方案
公开(公告)号：WO2014130604A1
公开(公告)日：2014-08-28
申请号：PCT/US2014/017252
申请日：2014-02-20
申请人： SANDISK 3D LLC
发明人： CHEN, Yingchang , LEE, Jeffrey Koon Yee
IPC分类号： G11C13/00 , G11C11/56
CPC分类号： G11C7/06 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C16/26 , G11C2013/0054 , G11C2013/0057
摘要： Methods for reducing variability in bias voltages applied to a plurality of memory cells during a sensing operation caused by IR drops along a word line shared by the plurality of memory cells are described. In some embodiments, IR drops along a shared word line may be reduced by reducing sensing currents associated with memory cells whose state has already been determined during a sensing operation. In one example, once a sense amplifier detects that a memory cell being sensed is in a particular state, then the sense amplifier may disable sensing of the memory cell and discharge a corresponding bit line associated with the memory cell. In some cases, a bit line voltage associated with a memory cell whose state has not already been determined during a first phase of a sensing operation may be increased during a second phase of the sensing operation.
摘要翻译：描述了在由多个存储器单元共享的字线的IR下降引起的感测操作期间减小施加到多个存储单元的偏置电压的变化性的方法。在一些实施例中，可以通过减少与在感测操作期间已经确定其状态的存储器单元相关联的感测电流来减小沿着共享字线的IR降级。在一个示例中，一旦读出放大器检测到被感测的存储器单元处于特定状态，则读出放大器可以禁止对存储器单元的感测并放电与存储器单元相关联的相应位线。在一些情况下，在感测操作的第二阶段期间，与在感测操作的第一阶段尚未确定状态的存储器单元相关联的位线电压可能会增加。

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