专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO8707968A3 MULTI-MODE COUNTER NETWORK 审中-公开
标题翻译：多模式计数器网络
公开(公告)号：WO8707968A3
公开(公告)日：1988-01-28
申请号：PCT/US8701240
申请日：1987-05-29
申请人： HUGHES AIRCRAFT CO
发明人： UNDERWOOD GEORGE D
IPC分类号： G01R31/28 , G01R31/3185 , G06F20060101 , G06F11/22 , G06F11/26 , H03K20060101 , H03K21/12 , H03K21/40
CPC分类号： H03K21/12 , G01R31/318527
摘要： A multi-mode counter network and a method of testing the operation of the multi-mode counter network. The multi-mode counter network comprises a counter circuit formed of a plurality of counter registers and a multiplexer circuit formed of a plurality of multiplexers wherein said multiplexers are connected to and associated with one of the registers and are operative to selectively vary the input signal communicated to the associated register such that the registers operate in one of a plurality of operational modes. By controlling the selection of the input signal communicated to the registers the network may be alternately configured to perform traditional counting functions or may be configured to provide a serial signal path for communicating a test pattern through the registers and multiplexers to test the operation of the multiplexers and registers. The test pattern is communicated through the circuit, bypassing counter enabling circuitry, and thus independent of the network counter rate.

2. 发明申请

WO87007968A2 MULTI-MODE COUNTER NETWORK 审中-公开
标题翻译：多模式计数器网络
公开(公告)号：WO87007968A2
公开(公告)日：1987-12-30
申请号：PCT/US1987001240
申请日：1987-12-30
IPC分类号： G01R31/28 , G01R31/3185 , G06F20060101 , G06F11/22 , G06F11/26 , H03K20060101 , H03K21/12 , H03K21/40
CPC分类号： H03K21/12 , G01R31/318527
摘要： A multi-mode counter network and a method of testing the operation of the multi-mode counter network. The multi-mode counter network comprises a counter circuit formed of a plurality of counter registers and a multiplexer circuit formed of a plurality of multiplexers wherein said multiplexers are connected to and associated with one of the registers and are operative to selectively vary the input signal communicated to the associated register such that the registers operate in one of a plurality of operational modes. By controlling the selection of the input signal communicated to the registers the network may be alternately configured to perform traditional counting functions or may be configured to provide a serial signal path for communicating a test pattern through the registers and multiplexers to test the operation of the multiplexers and registers. The test pattern is communicated through the circuit, bypassing counter enabling circuitry, and thus independent of the network counter rate.

3. 发明申请

WO1997014044A1 COUNTER AND A REVOLUTION STOP DETECTION APPARATUS USING THE COUNTER 审中-公开
标题翻译：计数器和使用计数器的变革停止检测装置
公开(公告)号：WO1997014044A1
公开(公告)日：1997-04-17
申请号：PCT/JP1996002229
申请日：1996-08-07
申请人： THE NIPPON SIGNAL CO., LTD. , SAKAI, Masayoshi , FUTSUHARA, Koichi
发明人： THE NIPPON SIGNAL CO., LTD.
IPC分类号： G01R23/10
CPC分类号： G01D5/24461 , G01D3/08 , G01D5/24457 , G01P3/489 , G01P13/00 , G01P21/00 , G01P21/02 , G01R31/318527
摘要： A counting device having an excellent fail-safe function. According to a first invention, a counter (1) counts pulse signals (P1) to be counted and then counts the cycles of a high-frequency signal (P2). When the frequency of the high-frequency signal (P2) is a predetermined value, a frequency judging circuit (30) generates a judgement signal representing that the counter is normal. According to a second invention, a counter (100) is preset by a preset signal, the counter resetting is confirmed based on the output of a self-hold circuit (102), and another self-hold circuit (104) generates a count output. According to a third invention, such a counting device is used as a timer circuit (203, 300, 400) to determine the rate of generation of the revolution detection pulse signal (Ip) generated based on a sensor signal, thereby detecting the stop of revolution of a rotating body.
摘要翻译：具有出色故障保护功能的计数装置。根据第一发明，计数器（1）对要计数的脉冲信号（P1）进行计数，然后对高频信号（P2）的周期进行计数。当高频信号（P2）的频率为预定值时，频率判断电路（30）产生表示计数器正常的判断信号。根据第二发明，通过预设信号预设计数器（100），基于自保持电路（102）的输出来确认计数器复位，另一自保持电路（104）产生计数输出。根据第三发明，这种计数装置用作定时器电路（203,300,400），以确定基于传感器信号产生的转速检测脉冲信号（Ip）的产生速率，从而检测停止旋转体的旋转。

4. 发明申请

WO1993018457A1 TRANSPARENT TESTING OF INTEGRATED CIRCUITS 审中-公开
标题翻译：集成电路的透明测试
公开(公告)号：WO1993018457A1
公开(公告)日：1993-09-16
申请号：PCT/GR1993000005
申请日：1993-03-05
申请人： SOFIA KOLONI LTD. , NICOLAIDIS, Michael
发明人： SOFIA KOLONI LTD.
IPC分类号： G06F11/26
CPC分类号： G01R31/318527 , G01R31/318533 , G01R31/318536 , G06F11/221 , G06F11/2273 , G06F11/27 , G06F11/2733 , G06F2201/83 , G11C29/32 , G11C29/40
摘要： A technique for transparent testing of integrated circuits has been described. It allows to test the integrated circuits without losing the applications' execution context. The technique considers two kinds of blocks, combinational and sequential blocks on the one hand and RAMs and register files on the other hand. For the first kind of blocks we propose a save, test and restore technique. It takes advantage from a circular scan path implementation and consists on shifting (via the scan path) the contents of various registers until the data inputs of a RAM, it saves the registers' contents in the RAM, performs the test session, loads back the saved data to the scan path and shifts them until the corresponding registers. For the second kind of blocks we propose a transparent test technique allowing to test the RAMs without destroying their initial contents. To do that we propose a technique allowing to derive RAM transparent test processes. These thest processes can be implemented by means of BIST techniques, or by means of scan path techniques. The transparent test processes are composed by a signature prediction or a signature initialisation process and a basic transparent test process. The signature prediction test process is obtained from the basic transparent test process by removing all the write operations. The read operations such that the read data are not injected to the output compaction scheme can also be removed. This technique avoids fault masking due to errors produced during both the signature prediction test process and the basic transparent test process. The basic transparent test process can be obtained from any standard (i.e. non transparent) test process by using several transformation steps. These transformation steps are such that for all the RAM fault models verifying some symmetric property, the basic transparent test process offers the same fault coverage as the standard test process. This property is verified by nearly all the RAM fault models. The signature initialisation process is derived from the signature prediction process by reversing its ordering. When this process is used it is coupled with some new data compactors named Up/Down data compactors. These compactors allow for the whole process (i.e. signature initialisation process plus basic transparent test process) to give a predicted signature.
摘要翻译：已经描述了用于集成电路的透明测试的技术。它允许测试集成电路，而不会丢失应用程序的执行上下文。该技术一方面考虑两种块，组合和顺序块，另一方面考虑RAM和寄存器文件。对于第一类块，我们提出了一种保存，测试和恢复技术。它采用循环扫描路径实现，并且包括通过移动（通过扫描路径）各种寄存器的内容，直到RAM的数据输入，它将寄存器的内容保存在RAM中，执行测试会话，加载回将数据保存到扫描路径，并将其移动到相应的寄存器。对于第二种类型的块，我们提出了一种透明的测试技术，允许测试RAM而不会破坏它们的初始内容。为此，我们提出一种允许导出RAM透明测试过程的技术。这些第一个过程可以通过BIST技术或通过扫描路径技术来实现。透明测试过程由签名预测或签名初始化过程和基本的透明测试过程组成。通过删除所有写入操作，从基本透明测试过程获得签名预测测试过程。读取操作使得读取的数据不被注入到输出压缩方案中也可以被去除。该技术避免了在签名预测测试过程和基本透明测试过程期间产生的错误导致的故障屏蔽。可以通过使用几个变换步骤从任何标准（即非透明）测试过程获得基本的透明测试过程。这些转换步骤对于验证某些对称属性的所有RAM故障模型，基本的透明测试过程提供与标准测试过程相同的故障覆盖。该属性几乎全部由RAM故障模型进行验证。签名初始化过程通过反转其排序从签名预测过程中导出。当使用此过程时，它与一些名为Up / Down数据压缩机的新型数据压缩机相结合。这些压实机允许整个过程（即签名初始化过程加上基本的透明测试过程）来给出预测的签名。

5. 发明申请

WO87007992A1 LOOK AHEAD TERMINAL COUNTER 审中-公开
标题翻译：看起来终端计数器
公开(公告)号：WO87007992A1
公开(公告)日：1987-12-30
申请号：PCT/US1987001238
申请日：1987-12-30
IPC分类号： H03K21/40 , G01R31/3185 , G06F20060101 , G06F11/00 , H03K20060101 , H03K21/38
CPC分类号： G01R31/318527 , H03K21/38
摘要： A look ahead terminal counter and a method for generating a terminal count output signal. The counter comprises a plurality of counter registers connected to counter enable circuitry for sequencing the registers at a predetermined counter rate. Terminal count enable circuitry is connected to the counter circuitry, e.g. at the input ports of the counter registers, and is operative to generate a terminal count enable signal when those input ports are at a predetermined state. The terminal count enable signal and clock signal are communicated to an output register operative to generate a terminal count output signal when a clock signal is received during the simultaneous presence of the terminal count enable signal.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式