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1. 发明申请

WO2015120491A1 COMPUTER PROCESSOR EMPLOYING PHASES OF OPERATIONS CONTAINED IN WIDE INSTRUCTIONS 审中-公开
标题翻译：计算机处理器使用宽泛指令中包含的操作阶段
公开(公告)号：WO2015120491A1
公开(公告)日：2015-08-13
申请号：PCT/US2015/023826
申请日：2015-04-01
申请人： MILL COMPUTING, INC.
发明人： GODARD, Roger Rawson , KAHLICH, Arthur David , YOST, David Arthur , MIROLO, Sebastien Paul Maurice
IPC分类号： G06F7/53 , G06F9/38
CPC分类号： G06F9/3822 , G06F9/30167 , G06F9/3836 , G06F9/3853 , G06F9/3855 , G06F9/3861 , G06F9/3885
摘要： A computer processor employs an instruction processing pipeline that processes a sequence of wide instructions each having an encoding that represents a plurality of different operations. The plurality of different operations of the given wide instruction are logically organized into a number of phases having a predefined ordering such that at least one operation of the given wide instruction produces data that is consumed by at least one other operation of the given wide instruction. In certain circumstances where stalling is absent, the plurality of different operations of the phases of the given wide instruction can be issued for execution by the instruction processing pipeline over a plurality of consecutive machine cycles.
摘要翻译：计算机处理器采用指令处理流水线，其处理每个具有表示多个不同操作的编码的宽指令序列。给定宽指令的多个不同操作被逻辑地组织成具有预定义排序的多个阶段，使得给定宽指令的至少一个操作产生由给定宽指令的至少一个其他操作消耗的数据。在不存在停止的某些情况下，可以通过指令处理流水线在多个连续的机器周期上发出给定的宽指令的相位的多个不同的操作来执行。

2. 发明申请

WO2015057819A1 COMPUTER PROCESSOR WITH DEFERRED OPERATIONS 审中-公开
标题翻译：具有延期操作的计算机处理器
公开(公告)号：WO2015057819A1
公开(公告)日：2015-04-23
申请号：PCT/US2014/060661
申请日：2014-10-15
申请人： MILL COMPUTING, INC.
发明人： GODARD, Roger, Rawson , KAHLICH, Arthur, David , KANOVSKY, Nachum
IPC分类号： G06F9/38 , G06F9/318
CPC分类号： G06F9/30032 , G06F9/30145 , G06F9/3826 , G06F9/3828 , G06F12/0292 , G06F12/0811 , G06F12/0864 , G06F12/0893 , G06F12/0897 , G06F12/1009 , G06F12/1027 , G06F12/1045 , G06F17/30286 , G06F2212/1024 , G06F2212/1028 , G06F2212/283 , G06F2212/6032 , G06F2212/608 , G06F2212/684 , Y02D10/13
摘要： A computer processor and corresponding method of operation employs execution logic that includes at least one functional unit and operand storage that stores data that is produced and consumed by the at least one functional unit. The at least one functional unit is configured to execute a deferred operation whose execution produces result data. The execution logic further includes a retire station that is configured to store and retire the result data of the deferred operation in order to store such result data in the operand storage, wherein the retire of such result data occurs at a machine cycle following issue of the deferred operation as controlled by statically-assigned parameter data included in the encoding of the deferred operation.
摘要翻译：计算机处理器和相应的操作方法使用包括至少一个功能单元和存储由至少一个功能单元产生和消耗的数据的操作数存储器的执行逻辑。所述至少一个功能单元被配置为执行其执行产生结果数据的延迟操作。所述执行逻辑还包括退休站，其被配置为存储和退出所述延迟操作的结果数据，以便将所述结果数据存储在所述操作数存储器中，其中，所述结果数据的退出在发布延迟操作由延迟操作编码中包含的静态分配参数数据控制。

3. 发明申请

WO2016154115A1 CPU SECURITY MECHANISMS EMPLOYING THREAD-SPECIFIC PROTECTION DOMAINS 审中-公开
标题翻译： CPU安全机制采用特定保护域
公开(公告)号：WO2016154115A1
公开(公告)日：2016-09-29
申请号：PCT/US2016/023420
申请日：2016-03-21
申请人： MILL COMPUTING, INC.
发明人： GODARD, Roger, Rawson , KAHLICH, Arthur, David , SCHUKAT, Jan , EDWARDS, William
IPC分类号： G06F9/38
CPC分类号： G06F12/1466 , G06F9/46 , G06F12/1441
摘要： A computer processor includes an instruction processing pipeline that interfaces to a hierarchical memory system employing an address space. The instruction processing pipeline includes execution logic that executes at least one thread in different protection domains over time, wherein the different protection domains are defined by descriptors each including first data specifying a memory region of the address space employed by the hierarchical memory system and second data specifying permissions for accessing the associated memory region. The address space can be a virtual address space or a physical address space. The protection domains can be associated with different turfs each representing a collection of descriptors. A given thread can execute in a particular protection domain(turf), one protection domain (turf) at a time with the particular protection domain (turf) selectively configured to change over time.
摘要翻译：计算机处理器包括与采用地址空间的分层存储器系统接口的指令处理流水线。指令处理流水线包括执行逻辑，该执行逻辑在时间上执行不同保护域中的至少一个线程，其中不同的保护域由描述符定义，每个描述符包括指定分层存储器系统采用的地址空间的存储器区域的第一数据和第二数据指定访问关联内存区域的权限。地址空间可以是虚拟地址空间或物理地址空间。保护域可以与不同的turfs相关联，每个turfs表示描述符的集合。给定的线程可以在特定保护域（草皮）中执行，一个保护域（草坪），特定保护域（草皮）选择性地配置为随时间改变。

4. 发明申请

WO2016028410A1 EXECUTION AND SCHEDULING OF SOFTWARE PIPELINED LOOPS 审中-公开
标题翻译：软件管道的执行和调度
公开(公告)号：WO2016028410A1
公开(公告)日：2016-02-25
申请号：PCT/US2015/040096
申请日：2015-07-13
申请人： MILL COMPUTING, INC.
发明人： GODARD, Roger, Rawson , KAHLICH, Arthur, David , YOST, David, Arthur
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3857 , G06F8/452 , G06F9/30036 , G06F9/3016
摘要： A computer processor includes execution logic (having a number of functional units) configured to perform operations that access operand data values stored in a plurality of operand storage elements. Such operand data values include a predefined None operand data value indicative of a missing operand value. The operations include a RETIRE operation specifying a number of operand data values that is intended to be retired in a predefined machine cycle. During execution of the RETIRE operation, zero or more at None operand data values are selectively retired in the predefined machine cycle based on the number of operand data values specified by the RETIRE operation and the number of operand data values to be retired as a result of execution of other operations by the execution logic in the predefined machine cycle. Other aspects and software tools are also described and claimed.
摘要翻译：计算机处理器包括执行逻辑（具有多个功能单元），其被配置为执行存储在多个操作数存储元件中的操作数数据值的操作。这样的操作数数据值包括指示缺少操作数值的预定义的无操作数数据值。这些操作包括一个RETIRE操作，指定在预定义的机器周期中要退休的操作数数据值的数量。在RETIRE操作的执行期间，基于由RETIRE操作指定的操作数数据值的数量和由于RETIRE操作而退出的操作数数据值的数目，在预定义的机器周期中选择性地退出零个或多个无操作数数据值在预定义的机器周期中由执行逻辑执行其他操作。还描述和要求保护其他方面和软件工具。

5. 发明申请

WO2015089314A1 COMPUTER PROCESSOR EMPLOYING OPERAND DATA WITH ASSOCIATED META-DATA 审中-公开
标题翻译：计算机处理器使用相关的元数据操作数据
公开(公告)号：WO2015089314A1
公开(公告)日：2015-06-18
申请号：PCT/US2014/069811
申请日：2014-12-11
申请人： MILL COMPUTING, INC.
发明人： GODARD, Roger, Rawson , KAHLICH, Arthur, David , YOST, David, Arthur , MIROLO, Sebastien Paul, Maurice
IPC分类号： G06F9/38
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30072 , G06F9/30094 , G06F9/3016 , G06F9/30163 , G06F9/30192 , G06F9/3859 , G06F9/3865 , G06F11/0721 , G06F11/0772 , G06F12/14
摘要： A computer processor is provided that employs a plurality of operand storage elements that store operand data values and associated meta-data as unitary operand data elements as well as at least one functional unit that performs operations that produce and access the unitary operand data elements stored in the plurality of operand storage elements. The meta-data associated with a given operand data value as part of a unitary operand data element can specify type of the unitary operand data element (e.g., vector or scalar), elemental width and floating-point error flags. The meta-data can also be used to define special operand data values (e.g., Not-a-Result and None). The meta-data is useful in optimizing execution, such as in speculation and vectorized SIMD operations. The computer processor can also support a number of particular vector operations that are useful in optimizing execution of vectorized SIMD operations.
摘要翻译：提供了一种计算机处理器，其采用将操作数数据值和相关联的元数据存储为单一操作数数据元素的多个操作数存储元件以及执行产生和访问存储在其中的单一操作数数据元素的操作的至少一个功能单元多个操作数存储元件。与作为单一操作数数据元素的一部分的给定操作数数据值相关联的元数据可以指定单一操作数数据元素（例如，向量或标量），元素宽度和浮点错误标志的类型。元数据也可用于定义特殊的操作数数据值（例如非结果和无）。元数据在优化执行中非常有用，例如在推测和矢量化SIMD操作中。计算机处理器还可以支持用于优化矢量化SIMD操作的执行的许多特定向量操作。

6. 发明申请

WO2015057828A1 COMPUTER PROCESSOR EMPLOYING CACHE MEMORY STORING BACKLESS CACHE LINES 审中-公开
标题翻译：计算机处理器使用高速缓存存储器的无背后缓存线
公开(公告)号：WO2015057828A1
公开(公告)日：2015-04-23
申请号：PCT/US2014/060676
申请日：2014-10-15
申请人： MILL COMPUTING, INC.
发明人： GODARD, Roger, Rawson , KAHLICH, Arthur, David
IPC分类号： G06F12/08
CPC分类号： G06F9/30032 , G06F9/30145 , G06F9/3826 , G06F9/3828 , G06F12/0292 , G06F12/0811 , G06F12/0864 , G06F12/0893 , G06F12/0897 , G06F12/1009 , G06F12/1027 , G06F12/1045 , G06F17/30286 , G06F2212/1024 , G06F2212/1028 , G06F2212/283 , G06F2212/6032 , G06F2212/608 , G06F2212/684 , Y02D10/13
摘要： A computer processing system with a hierarchical memory system having at least one cache and physical memory, and a processor having execution logic that generates memory requests that are supplied to the hierarchical memory system. The at least one cache stores a plurality of cache lines including at least one backless cache line.
摘要翻译：具有分层存储器系统的计算机处理系统具有至少一个缓存和物理存储器，以及具有执行逻辑的处理器，所述执行逻辑生成提供给所述分层存储器系统的存储器请求。所述至少一个高速缓冲存储器存储包括至少一个后端高速缓存行的多条高速缓存行。

7. 发明申请

WO2015057857A1 COMPUTER PROCESSOR EMPLOYING DEDICATED HARDWARE MECHANISM CONTROLLING THE INITIALIZATION AND INVALIDATION OF CACHE LINES 审中-公开
标题翻译：计算机处理器采用专用硬件机制控制缓存线路的初始化和无效化
公开(公告)号：WO2015057857A1
公开(公告)日：2015-04-23
申请号：PCT/US2014/060721
申请日：2014-10-15
申请人： MILL COMPUTING, INC.
发明人： GODARD, Roger, Rawson , KAHLICH, Arthur, David , HARDY, Norman , BAUM, Allen, J.
IPC分类号： G06F12/08
CPC分类号： G06F9/30032 , G06F9/30145 , G06F9/3826 , G06F9/3828 , G06F12/0292 , G06F12/0811 , G06F12/0864 , G06F12/0893 , G06F12/0897 , G06F12/1009 , G06F12/1027 , G06F12/1045 , G06F17/30286 , G06F2212/1024 , G06F2212/1028 , G06F2212/283 , G06F2212/6032 , G06F2212/608 , G06F2212/684 , Y02D10/13
摘要： A computer processing system includes execution logic that generates memory requests that are supplied to a hierarchical memory system. The computer processing system includes a hardware map storing a number of entries associated with corresponding cache lines, where each given entry of the hardware map indicates whether a corresponding cache line i) currently stores valid data in the hierarchical memory system, or ii) does not currently store valid data in hierarchical memory system and should be interpreted as being implicitly zero throughout.
摘要翻译：计算机处理系统包括产生提供给分层存储器系统的存储器请求的执行逻辑。计算机处理系统包括存储与对应的高速缓存行相关联的多个条目的硬件映射，其中硬件映射的每个给定条目指示对应的高速缓存行i）当前是否在分层存储器系统中存储有效数据，或者ii）不目前在分层存储系统中存储有效数据，并且应该被解释为整体为零。

8. 发明申请

WO2015057846A1 COMPUTER PROCESSOR EMPLOYING CACHE MEMORY WITH PRE-BYTE VALID BITS 审中-公开
标题翻译：计算机处理器使用带前缀有效位的缓存存储器
公开(公告)号：WO2015057846A1
公开(公告)日：2015-04-23
申请号：PCT/US2014/060707
申请日：2014-10-15
申请人： MILL COMPUTING, INC.
发明人： GODARD, Roger, Rawson , KAHLICH, Arthur, David
IPC分类号： G06F12/08
CPC分类号： G06F9/30032 , G06F9/30145 , G06F9/3826 , G06F9/3828 , G06F12/0292 , G06F12/0811 , G06F12/0864 , G06F12/0893 , G06F12/0897 , G06F12/1009 , G06F12/1027 , G06F12/1045 , G06F17/30286 , G06F2212/1024 , G06F2212/1028 , G06F2212/283 , G06F2212/6032 , G06F2212/608 , G06F2212/684 , Y02D10/13
摘要： A computer processing system with a hierarchical memory system that associates a number of valid bits for each cache line of the hierarchical memory system. The valid bits are provided for each cache line stored in a respective cache and make explicit which bytes are semantically defined and which are not for the associated given cache line. Memory requests to the cache(s) of the hierarchical memory system can include an address specifying a requested cache line as well as a mask that includes a number of bits each corresponding to a different byte of the requested cache line.
摘要翻译：一种具有分层存储器系统的计算机处理系统，其将分层存储器系统的每个高速缓存行的多个有效位相关联。为存储在相应高速缓存中的每个高速缓存线提供有效位，并显式显示哪些字节在语义上定义，哪些字节不适用于相关联的给定高速缓存行。对分级存储器系统的缓存的存储器请求可以包括指定所请求的高速缓存行的地址以及包括每个对应于所请求的高速缓存行的不同字节的位数的掩码。

9. 发明申请

WO2015120491A4 COMPUTER PROCESSOR EMPLOYING PHASES OF OPERATIONS CONTAINED IN WIDE INSTRUCTIONS 审中-公开
标题翻译：计算机处理器使用宽操作指令中的操作阶段
公开(公告)号：WO2015120491A4
公开(公告)日：2015-10-29
申请号：PCT/US2015023826
申请日：2015-04-01
申请人： MILL COMPUTING INC
发明人： GODARD ROGER RAWSON , KAHLICH ARTHUR DAVID , YOST DAVID ARTHUR , MIROLO SEBASTIEN PAUL MAURICE
IPC分类号： G06F7/53 , G06F9/38
CPC分类号： G06F9/3822 , G06F9/30167 , G06F9/3836 , G06F9/3853 , G06F9/3855 , G06F9/3861 , G06F9/3885
摘要： A computer processor employs an instruction processing pipeline that processes a sequence of wide instructions each having an encoding that represents a plurality of different operations. The plurality of different operations of the given wide instruction are logically organized into a number of phases having a predefined ordering such that at least one operation of the given wide instruction produces data that is consumed by at least one other operation of the given wide instruction. In certain circumstances where stalling is absent, the plurality of different operations of the phases of the given wide instruction can be issued for execution by the instruction processing pipeline over a plurality of consecutive machine cycles.
摘要翻译：计算机处理器采用指令处理流水线，处理一系列宽指令，每条指令具有表示多个不同操作的编码。给定宽指令的多个不同操作在逻辑上组织成具有预定义顺序的多个阶段，使得给定宽指令的至少一个操作产生由给定宽指令的至少一个其他操作消耗的数据。在某些情况下，如果不存在拖延，则给定的宽指令的相位的多个不同操作可以在多个连续的机器周期中被指令处理流水线发布以供执行。

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