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1. 发明申请

WO1989001263A1 VARIABLE FREQUENCY SYSTEM HAVING LINEAR COMBINATION OF CHARGE PUMP AND VOLTAGE CONTROLLED OSCILLATOR 审中-公开
标题翻译：具有充电泵和电压控制振荡器的线性组合的可变频率系统
公开(公告)号：WO1989001263A1
公开(公告)日：1989-02-09
申请号：PCT/US1988002624
申请日：1988-08-01
申请人： WESTERN DIGITAL CORPORATION
发明人： WESTERN DIGITAL CORPORATION , SHEARER, Gerald , LOFGREN, Karl, M. , OUYANG, Kenneth, W.
IPC分类号： H03L07/08
CPC分类号： H03L7/0898 , H04L7/033
摘要： A phase locked loop system having a non-linear voltage controlled oscillator (VCO) is provided with a variable gain charge pump. The charge pump supplies a pump current to an integrating network which transforms the pump current into a frequency-modulating input voltage. The frequency-modulating input voltage is applied to an input of the VCO. The frequency-modulating input voltage is also coupled to a gain control input of the variable gain charge pump so that the magnitude of the pump current will be a function of the absolute value of the frequency-modulating voltage. A substantially constant loop gain may be obtained in the phase locked loop system by arranging the gain function of the variable gain charge pump in counterposed relation to the slope of a VCO transfer function defining the nonlinear relation between the frequency-modulating input voltage of the VCO and the output frequency of the VCO.

2. 发明申请

WO1988007317A1 SOLDER PASTE REPLACEMENT METHOD AND ARTICLE 审中-公开
标题翻译：焊膏替代方法和文章
公开(公告)号：WO1988007317A1
公开(公告)日：1988-09-22
申请号：PCT/US1988000619
申请日：1988-03-01
申请人： WESTERN DIGITAL CORPORATION
发明人： WESTERN DIGITAL CORPORATION , ELLIOTT, James
IPC分类号： H05K03/34
CPC分类号： B23K1/20 , B23K1/085 , B23K2101/40 , H05K3/26 , H05K3/3421 , H05K3/3468 , H05K3/3489 , H05K2201/10689 , H05K2203/044 , H05K2203/0485 , Y02P70/613
摘要： A method for soldering surface mountable electronic components (40) to a printed circuit board (10) is described. The method involves the use of a wave soldering machine (22) to coat the pads (12) of the printed circuit board (10) with solder (26). After the pads (12) are coated with solder (26), the entire surface of the board (10) is covered with flux paste (38). Then, surface mountable electronic components (40) are positioned on the board (10). The viscous flux (38) coating holds the leads of each electronic component (40) to the pads (12) until the board (10) is placed in a furnace. The heat from the furnace first melts the flux (38) which chemically cleans the surface of the solder coated pads (12). Further increases in temperature melt the solder coating (44) to solder the component leads (42) to the pads (12). When the board (10) is subsequently removed from the furnace, the solder cools and resolidifies to electrically and mechanically connect the leads (42) to the pads (12).
摘要翻译：描述了将表面可安装的电子部件（40）焊接到印刷电路板（10）的方法。该方法包括使用波峰焊机（22）用焊料（26）涂覆印刷电路板（10）的焊盘（12）。在焊盘（12）涂覆有焊料（26）之后，板（10）的整个表面被焊剂膏（38）覆盖。然后，表面安装电子元件（40）位于板（10）上。粘性通量（38）涂层将每个电子部件（40）的引线保持到焊盘（12），直到板（10）放置在炉中。来自炉子的热量首先熔化焊剂（38），其通过化学清洁焊料涂覆的焊盘（12）的表面。熔化焊料涂层（44）的温度进一步升高以将部件引线（42）焊接到焊盘（12）。当板（10）随后从炉中取出时，焊料冷却并重新固化以将引线（42）电连接和机械地连接到焊盘（12）。

3. 发明申请

WO1989000789A2 CMOS SCHMITT TRIGGER WITH INDEPENDENTLY BIASED HIGH/LOW THRESHOLD CIRCUITS 审中-公开
标题翻译：具有独立偏置高/低阈值电路的CMOS SCHMITT触发器
公开(公告)号：WO1989000789A2
公开(公告)日：1989-01-26
申请号：PCT/US1988002386
申请日：1988-07-14
申请人： WESTERN DIGITAL CORPORATION
发明人： WESTERN DIGITAL CORPORATION , O'SHAUGHNESSY, Timothy , HULL, Richard, W.
IPC分类号： H03K03/295
CPC分类号： H03K3/0377 , H03K3/3565
摘要： A Schmitt trigger circuit with independently biased threshold sections includes a drive disabling switch for blocking one of the threshold sections from driving a logic node toward a predetermined logic state. The drive disabling switch is selectively operated so that unidirectional sensitivity to the crossing of a threshold level belonging to its corresponding one threshold section is obtained.
摘要翻译：具有独立偏置的阈值部分的施密特触发器电路包括用于防止阈值部分中的一个将逻辑节点设置为预定逻辑状态的控制禁用开关。控制禁止开关被选择性地致动，以在属于与其相关联的相关联的阈值部分的阈值水平交叉处提供单向灵敏度。

4. 发明申请

WO1988010061A1 MOUNTING OF PRINTED CIRCUIT BOARDS IN COMPUTERS 审中-公开
标题翻译：印刷电路板在计算机中的安装
公开(公告)号：WO1988010061A1
公开(公告)日：1988-12-15
申请号：PCT/US1988000628
申请日：1988-03-02
申请人： WESTERN DIGITAL CORPORATION
发明人： WESTERN DIGITAL CORPORATION , PATTON, Charles, Royston
IPC分类号： H05K07/12
CPC分类号： G06F1/185 , G06F1/184 , G06F1/186 , H05K7/1429
摘要： A mounting system for mounting an expansion card (38) inside a computer chassis includes a mounting bracket (62) having a combination board mounting clip (64) and chassis mounting tab (66) formed as an integral unit in which the bracket releasably fastens to a corner of the expansion card. The expansion card has a bottom edge connector (40) for plugging into an expansion card socket (26) at the base of the computer chassis inside the expansion slot. The computer chassis also has a removable cover plate (20) on a panel of the chassis for shielding the expansion slot. The board mounting clip releasably fastens to the expansion card (38) by engaging the opposite faces of the board (38) in a continuous frictional means of attachment without the use of external fastening means. The chassis mounting tab (66) is arranged so that when the expansion card is plugged into the expansion card socket (26), a portion (90) of the chassis mounting tab (66) automatically registers with the fastener (36) for the cover plate (20) so that the fastener (36) is usable to fasten the tab (66) to a portion of the chassis (24) adjacent the cover plate (30), with the cover plate (20) providing a separate means of shielding the expansion slot, independently of the bracket (62) on the expansion card (38).

5. 发明申请

WO1989001283A1 APPARATUS AND METHOD FOR ALIGNING SURFACE MOUNTABLE ELECTRONIC COMPONENTS ON PRINTED CIRCUIT BOARD PADS 审中-公开
标题翻译：印刷电路板贴面上表面安装电子元件的装置和方法
公开(公告)号：WO1989001283A1
公开(公告)日：1989-02-09
申请号：PCT/US1988002234
申请日：1988-06-30
申请人： WESTERN DIGITAL CORPORATION
发明人： WESTERN DIGITAL CORPORATION , ELLIOTT, James, N.
IPC分类号： H05K13/04
CPC分类号： B23K1/06 , H05K3/3421 , H05K3/3494 , H05K13/0465 , H05K2201/10689 , H05K2203/0292 , H05K2203/048 , H05K2203/1509 , Y02P70/613 , Y10T29/49144 , Y10T29/53183
摘要： A method and apparatus are described for precisely centering the leads of surface mountable electronic components on the pads of a printed circuit board. The method includes coating the pads with solder, placing the leads of the components on the solder coated pads, melting the solder and vibrating the leads relative to the pads while the solder is molten, so that the surface tension of the molten solder centers the leads on the pads. The molten solder is then cooled until it resolidifies.

6. 发明申请

WO1988008229A1 TRANSIENT NOISE REDUCTION BY PREMAGNETIZATION OF PARASITIC INDUCTANCE 审中-公开
标题翻译：通过预处理电磁场电流降低瞬态噪声
公开(公告)号：WO1988008229A1
公开(公告)日：1988-10-20
申请号：PCT/US1988001149
申请日：1988-04-06
申请人： WESTERN DIGITAL CORPORATION
发明人： WESTERN DIGITAL CORPORATION , OUYANG, Kenneth, Wisheng , O'SHAUGHNESSY, Timothy, Glen
IPC分类号： H03K17/16
CPC分类号： H03K17/163 , H03K17/162 , H03K19/00361
摘要： The present invention provides an apparatus and method for allowing an electronic device to drive large values of load capacitance without generating high levels of transient noise. Means (37, 44) are provided for passing a first current (12) through the parasitic inductance (32) of the integrated circuit prior to the activation of the output driver (36), presoaking the parasitic inductance. Thereafter, when the output driver (36) is activated and the load capacitance (38) discharges through the inductance (32) of the integrated circuit, the first current (12) is removed from as the current (13) from the load capacitor (38) replaces it. Since an initial level of current existed through the inductance, the rate of change of current passing through the inductance during activation of the output driver is maintained approximately constant, thereby reducing the level of transient noise generated by the electronic device.

7. 发明申请

WO1988008228A2 METHOD AND APPARATUS FOR REDUCING TRANSIENT NOISE IN INTEGRATED CIRCUITS 审中-公开
标题翻译：用于减少集成电路中瞬态噪声的方法和装置
公开(公告)号：WO1988008228A2
公开(公告)日：1988-10-20
申请号：PCT/US1988001051
申请日：1988-04-01
申请人： WESTERN DIGITAL CORPORATION
发明人： WESTERN DIGITAL CORPORATION , O'SHAUGHNESSY, Timothy, Glen , CHUNG, David, Kyong-Sik , HULL, Richard, William , OUYANG, Kenneth, W. , PIEROTTI, Victor, G. , SOUZA, Joseph, Arthur
IPC分类号： H03K17/16
CPC分类号： H03K17/166 , H03K17/163 , H03K19/00361
摘要： The transient noise generated at the output drivers of an integrated circuit chip is reduced by maintaining an increasing ramp shaped current through each output driver during the entire transition interval between binary states of a capacitive load. A capacitor fed by a fixed current source is connected across the input of each output driver stage. The fixed current source and capacitor are so selected as to generate across the input of each output driver stage a linear ramp shaped control voltage that regulates the charging/discharging current through the output driver stage and package inductance in the described manner. A specially designed bias circuit reduces the sensitivity of the resulting transient noise to process variations and operating conditions. A feedback connection from the package inductance to the bias control circuit for the fixed current source adjusts the fixed current inversely with the transient noise. A dynamic clamp suppresses voltage spikes extending outside the voltage supply operating range. A bias circuit arrangement compensates for sheet resistivity of the integrated circuit chip. If the resistance value of the sheet drops below a prescribed value, the fixed current is limited so it cannot exceed its designed value.
摘要翻译：在集成电路芯片的输出驱动器处产生的瞬态噪声通过在容性负载的二进制状态之间的整个转换间隔期间保持通过每个输出驱动器的斜坡形状电流而减小。由固定电流源馈送的电容器连接在每个输出驱动级的输入端。固定电流源和电容器被选择为在每个输出驱动级的输入端产生线性斜坡形控制电压，其以所述方式调节通过输出驱动级和封装电感的充电/放电电流。专门设计的偏置电路降低了所产生的瞬态噪声对工艺变化和工作条件的敏感性。从封装电感到用于固定电流源的偏置控制电路的反馈连接将与固定电流反向地调整固定电流与瞬态噪声。动态钳位电压可以抑制电压工作范围以外的电压尖峰。偏置电路布置补偿集成电路芯片的薄层电阻率。如果纸张的电阻值低于规定值，则固定电流受到限制，因此不能超过设计值。

8. 发明申请

WO1988006382A1 CMOS CIRCUIT WITH RACEFREE SINGLE CLOCK DYNAMIC LOGIC 审中-公开
标题翻译： CMOS电路与RACEFREE单时钟动态逻辑
公开(公告)号：WO1988006382A1
公开(公告)日：1988-08-25
申请号：PCT/US1988000430
申请日：1988-02-11
申请人： WESTERN DIGITAL CORPORATION
发明人： WESTERN DIGITAL CORPORATION , CHUNG, Randall, M. , MASTERS, Bradley, S.
IPC分类号： H03K19/177
CPC分类号： H03K19/0963 , H03K19/00323 , H03K19/1772
摘要： Improved logic circuit employing dynamic CMOS logic and having alternating logic employing first and second conductivity type transistors (24, 26), respectively, separated by clocked inverters (20). The circuit employs a single clock signal (CK) to synchronize the dynamic logic operations of said logic gates and, along with a second, complement clock signal (CK), said clocked inverters (20). Precharge transistors (28, 30, 32, 34) of each conductivity type are slowed slightly with respect to logic transistors (24, 26), and the complement clock signal is delayed slightly with respect to the clock signal, thereby providing racefree logic operations. An inplementation in a PLA is disclosed employing two logic planes (10, 12) for implementing arbitrary logic equations on input logic signals (14). The first logic plane (10) and second logic plane (12) are evaluated on separate phases of a complement clock signal (CK) and are separated by a clocked latch/inverter (20) for providing correct logic evaluation between the logic planes.
摘要翻译：采用动态CMOS逻辑的改进的逻辑电路和分别由时钟反相器（20）分开的具有第一和第二导电类型晶体管（24,26）的交替逻辑。所述电路采用单个时钟信号（CK）来同步所述逻辑门的动态逻辑运算，以及与第二补码时钟信号（CK），所述时钟反相器（20）同步。每个导电类型的预充电晶体管（28,30,32,34）相对于逻辑晶体管（24,26）略微减慢，并且互补时钟信号相对于时钟信号稍微延迟，由此提供无竞争逻辑运算。公开了一种在PLA中的实现，其采用用于在输入逻辑信号（14）上实现任意逻辑方程的两个逻辑平面（10,12）。第一逻辑平面（10）和第二逻辑平面（12）在补码时钟信号（CK）的单独相位上进行评估，并由时钟锁存/反相器（20）分离，以在逻辑平面之间提供正确的逻辑评估。

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