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1. 发明申请

WO2007102141A3 MULTI-BIT-PER-CELL FLASH MEMORY DEVICE WITH NON-BIJECTIVE MAPPING 审中-公开
标题翻译：具有非定向映射的多位单元闪速存储器件
公开(公告)号：WO2007102141A3
公开(公告)日：2009-04-09
申请号：PCT/IL2006001251
申请日：2006-10-30
申请人： UNIV RAMOT , LITSYN SIMON , SHARON ERAN , ALROD IDAN
发明人： LITSYN SIMON , SHARON ERAN , ALROD IDAN
IPC分类号： G06F12/00
CPC分类号： G11C16/10 , G06F11/1072 , G11C7/1006 , G11C11/56 , G11C11/5628 , G11C16/0483 , G11C16/34 , G11C29/42 , G11C2211/5641
摘要： To store a plurality of input bits, the bits are mapped to a corresponding programmed state of one or more memory cells and the cell(s) is/are programmed to that corresponding programmed state. The mapping may be many-to one or may be an "into" generalized Gray mapping. The cell(s) is/are read to provide a read state value that is transformed into a plurality of output bits, for example by maximum likelihood decoding or by mapping the read state value into a plurality of soft bits and then decoding the soft bits.
摘要翻译：为了存储多个输入位，这些位被映射到一个或多个存储器单元的相应的编程状态，并且单元被编程为相应的编程状态。映射可以是多对一的，或者可以是“到”广义灰色映射。读取单元以提供被转换成多个输出位的读取状态值，例如通过最大似然解码或通过将读取状态值映射到多个软比特中，然后解码软比特。

2. 发明申请

WO2007043042A3 METHOD OF ERROR CORRECTION IN MBC FLASH MEMORY 审中-公开
标题翻译： MBC闪存中错误校正方法
公开(公告)号：WO2007043042A3
公开(公告)日：2008-12-31
申请号：PCT/IL2006001159
申请日：2006-10-04
申请人： UNIV RAMOT , LITSYN SIMON , ALROD IDAN , SHARON ERAN , MURIN MARK , LASSER MENACHEM
发明人： LITSYN SIMON , ALROD IDAN , SHARON ERAN , MURIN MARK , LASSER MENACHEM
IPC分类号： G11C29/00
CPC分类号： G06F11/1072
摘要： A plurality of logical pages is stored in a MBC flash memory (42) along with corresponding ECC bits, with at least one of the MBC cells storing bits from more than one logical page, and with at least one of the ECC bits applying to two or more of the logical pages. When the pages are read from the memory (42), the data bits as read are corrected using the ECC bits as read. Alternatively, a joint, systematic or non-systematic ECC codeword is computed for two or more of the logical pages and is stored instead of those logical pages. When the joint codeword is read, the logical bits are recovered from the codeword as read. The scope of the invention also includes corresponding memory devices (54, 56, 5S), the controllers of such memory devices (54, 56, 58), and also computer-readable storage media bearing computer-readable code for implementing the methods.
摘要翻译：多个逻辑页面与相应的ECC位一起存储在MBC闪速存储器（42）中，其中至少一个MBC单元存储来自多于一个逻辑页面的位，并且至少一个ECC位应用于两个或更多的逻辑页面。当从存储器（42）读取页面时，读取的数据位使用被读取的ECC位进行校正。或者，针对两个或多个逻辑页面计算联合的，系统的或非系统的ECC码字，并且存储该代码字而不是那些逻辑页面。当读取联合码字时，从读取的码字中恢复逻辑比特。本发明的范围还包括对应的存储设备（54,56,5S），这些存储设备（54,56,58）的控制器，以及用于实现该方法的具有计算机可读代码的计算机可读存储介质。

3. 发明申请

WO2011010286A3 COMPACT DECODING OF PUNCTURED CODES 审中-公开
标题翻译：伪码的紧凑解码
公开(公告)号：WO2011010286A3
公开(公告)日：2011-11-24
申请号：PCT/IB2010053317
申请日：2010-07-21
申请人： UNIV RAMOT , SHARON ERAN , ALROD IDAN , LITSYN SIMON
发明人： SHARON ERAN , ALROD IDAN , LITSYN SIMON
IPC分类号： H03M13/00 , H03M13/25 , H04L1/00
CPC分类号： H03M13/1185 , H03M13/1111 , H03M13/616 , H03M13/6362 , H03M13/6393 , H04L1/0013 , H04L1/0052 , H04L1/0057 , H04L1/0069
摘要： k input bits are encoded according to a code with which is associated a m x n=m+k parity check matrix H. The resulting codeword is punctured, with n' bits. The punctured codeword is exported to a corrupting medium such as a communication channel or a memory. A representation of the punctured codeword is imported from the corrupting medium and is decoded using a matrix H' that is smaller than H. For example, H' is m'=m~(n-n ') x n' and is derived by merging selected rows of H. Alternatively, H has at most m rows and fewer than n columns but more than n' columns. Alternatively, H has fewer than m'=m-(n-n') rows and fewer than n' columns.
摘要翻译： k个输入比特根据与m×n = m + k个奇偶校验矩阵H相关联的代码进行编码。所产生的码字用n'比特打孔。删截的码字被导出到诸如通信信道或存储器之类的破坏媒体。删截码字的表示从破坏介质导入并使用小于H的矩阵H'解码。例如，H'是m'= m〜（nn'）×n'并且通过合并选择的行的H.或者，H具有至多m行，少于n列但多于n'列。或者，H具有少于m'= m-（n-n'）行且少于n'列。

4. 发明申请

WO2009156935A1 USING DAMPING FACTORS TO OVERCOME LDPC TRAPPING SETS 审中-公开
标题翻译：使用阻尼因子来覆盖LDPC陷波器组
公开(公告)号：WO2009156935A1
公开(公告)日：2009-12-30
申请号：PCT/IB2009052662
申请日：2009-06-22
申请人： UNIV RAMOT , SHARON ERAN , LITSYN SIMON , ALROD IDAN
发明人： SHARON ERAN , LITSYN SIMON , ALROD IDAN
IPC分类号： H03M13/11
CPC分类号： H03M13/1137 , H03M13/1114 , H03M13/114 , H03M13/3753 , H03M13/618 , H03M13/6362 , H03M13/658
摘要： To decode a representation, imported from a channel, of a codeword that encodes K information bits as N>K codeword bits, estimates of the codeword bits are updated by exchanging messages between JV bit nodes and N-K check nodes of a graph in a plurality of iterations. In each of one or more of the iterations, some or all values associated with the bit nodes, and/or some or all values associated with check nodes, and/or some or all messages are modified in a manner that depends explicitly on the ordinality of the iteration and is independent of any other iteration. Alternatively, the modifications are according to respective locally heteromorphic rules.
摘要翻译：为了将从信道导入的表示解码为将K个信息比特编码为N> K个码字比特的码字，通过在图中的JV比特节点和NK校验节点之间交换消息来更新码字比特的估计，迭代。在一个或多个迭代中的每一个中，与位节点相关联的一些或所有值，和/或与校验节点相关联的一些或所有值和/或某些或所有消息以明确依赖于序数的方式被修改的迭代，并且独立于任何其他迭代。或者，修改根据各自的本地异形规则。

5. 发明申请

WO2008142683A3 MEMORY-EFFICIENT LDPC DECODING 审中-公开
标题翻译：存储器高效的LDPC解码
公开(公告)号：WO2008142683A3
公开(公告)日：2009-02-12
申请号：PCT/IL2008000685
申请日：2008-05-20
申请人： UNIV RAMOT , SHARON ERAN , LITSYN SIMON , ALROD IDAN
发明人： SHARON ERAN , LITSYN SIMON , ALROD IDAN
IPC分类号： H03M13/11
CPC分类号： H03M13/114 , H03M13/6505
摘要： To decode a representation of a codeword that encodes K information bits as N>K codeword bits, messages are exchanged between N bit nodes and N-K check nodes of a graph in which E edges connect the bit nodes and the check nodes. While messages are exchanged, fewer than E of the messages are stored, and/or fewer than N soft estimates of the codeword bits are stored. In some embodiments, the messages are exchanged only within sub-graphs and between the sub-graphs and one or more external check nodes. While messages are exchanged, the largest number of stored messages is the number of edges in the sub-graph with the most edges plus the number of edges that connect the sub-graphs to the external check node(s), and/or the largest number of stored soft estimates is the number of bit nodes in the sub-graph with the most bit nodes.
摘要翻译：为了将编码K个信息比特的码字的表示解码为N个K个码字比特，消息在其中E个边缘连接比特节点和校验节点的图的N个比特节点和N-K个校验节点之间进行交换。当消息被交换时，存储少于E个消息，和/或存储少于N个码字比特的软估计。在一些实施例中，消息仅在子图中以及子图和一个或多个外部校验节点之间交换。当消息被交换时，最大数量的存储消息是具有最多边缘的子图中的边数加上将子图连接到外部校验节点的边数，和/或最大存储的软估计数是具有最多位节点的子图中的比特节点的数量。

6. 发明申请

WO2008081426B1 AVOIDING ERRORS IN A FLASH MEMORY BY USING SUBSTITUTION TRANSFORMATIONS 审中-公开
标题翻译：通过使用替代变换避免闪存中的错误
公开(公告)号：WO2008081426B1
公开(公告)日：2008-08-14
申请号：PCT/IL2007001567
申请日：2007-12-19
申请人： UNIV RAMOT , ALROD IDAN , SHARON ERAN , LITSYN SIMON
发明人： ALROD IDAN , SHARON ERAN , LITSYN SIMON
IPC分类号： G06F11/10 , G11C7/10 , G11C11/56
CPC分类号： G11C11/5628 , G06F11/1072 , G11C7/1006 , G11C29/00
摘要： Memory circuitry, or a memory device controller, or a host of a memory device, store an input string of M N-tuples of bits by selecting a substitution transformation in accordance with the input string and by applying the transformation to the input string to provide a transformed string of M N-tuples of bits. M or more memory cells are programmed to represent the transformed string and preferably also to represent a key of the transformation. Alternatively, the circuitry selectively programs each of M or more cells to a respective one of 2N states. The circuitry or the controller selects a mapping that maps the binary numbers in [0,2N-1] into respective states in accordance with the input string and the circuitry uses the mapping to program M cells to represent the input string. Preferably, a key of the mapping is stored in the memory in association with the M cells.
摘要翻译：存储器电路或存储器件控制器或存储器件的主机通过根据输入字符串选择替换变换并通过将变换应用于输入字符串来存储M个N元组的输入串，以提供一个M位元组的变换字符串。 M个或更多个存储器单元被编程以表示变换的字符串，并且优选地也表示转换的关键字。或者，电路选择性地将M个或更多个单元中的每一个编程为2N个状态中的相应的一个。电路或控制器根据输入字符串选择将[0,2N-1]中的二进制数映射到各自状态的映射，并且电路使用映射来编程M个单元来表示输入字符串。优选地，映射的密钥与M个单元相关联地存储在存储器中。

7. 发明申请

WO2011010286A2 COMPACT DECODING OF PUNCTURED CODES 审中-公开
标题翻译：拼接代码的紧凑解码
公开(公告)号：WO2011010286A2
公开(公告)日：2011-01-27
申请号：PCT/IB2010053317
申请日：2010-07-21
申请人： UNIV RAMOT , SHARON ERAN , ALROD IDAN , LITSYN SIMON
发明人： SHARON ERAN , ALROD IDAN , LITSYN SIMON
CPC分类号： H03M13/1185 , H03M13/1111 , H03M13/616 , H03M13/6362 , H03M13/6393 , H04L1/0013 , H04L1/0052 , H04L1/0057 , H04L1/0069
摘要： k input bits are encoded according to a code with which is associated a m x n=m+k parity check matrix H. The resulting codeword is punctured, with n' bits. The punctured codeword is exported to a corrupting medium such as a communication channel or a memory. A representation of the punctured codeword is imported from the corrupting medium and is decoded using a matrix H' that is smaller than H. For example, H' is m'=m~(n-n ') x n' and is derived by merging selected rows of H. Alternatively, H has at most m rows and fewer than n columns but more than n' columns. Alternatively, H has fewer than m'=m-(n-n') rows and fewer than n' columns.
摘要翻译： k个输入比特根据与m×n = m + k个奇偶校验矩阵H相关联的代码进行编码。所得到的码字以n'比特被打孔。穿孔码字被导出到诸如通信信道或存储器的破坏介质。穿孔码字的表示是从破坏介质中导入的，并且使用小于H的矩阵H'进行解码。例如，H'是m'= m〜（nn'）xn'，并且通过合并所选择的行而导出或者，H具有至多m行且少于n列但大于n'列。或者，H具有少于m'= m-（n-n'）行且小于n'列。

8. 发明申请

WO2007057885A3 METHOD AND DEVICE FOR MULTI PHASE ERROR-CORRECTION 审中-公开
标题翻译：用于多相位错误校正的方法和装置
公开(公告)号：WO2007057885A3
公开(公告)日：2009-09-03
申请号：PCT/IL2006001305
申请日：2006-11-13
申请人： UNIV RAMOT , LITSYN SIMON , SHARON ERAN , ALROD IDAN , LASSER MENACHEM
发明人： LITSYN SIMON , SHARON ERAN , ALROD IDAN , LASSER MENACHEM
IPC分类号： H03M7/00
CPC分类号： H03M13/2927 , G06F11/1068 , H03M13/1111 , H03M13/152 , H03M13/1545 , H03M13/2903 , H03M13/2906 , H03M13/3715 , H03M13/6362
摘要： Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. If one of the decodings fails, the remaining subset whose decoding failed is decoded at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits.
摘要翻译：要编码的数据位被分割成多个子组。每个子组被分别编码以产生相应的码字。所选择的子集从相应的码字中移除，留下缩短的码字，并且被多对一地转换成浓缩比特。最终码字是缩短的码字和浓缩比特的组合。最终码字的表示被分割成选定的子集和多个剩余子集。每个剩余子集被单独解码。如果解码失败之一，则解码失败的剩余子集至少部分地根据所选子集进行解码。如果编码和解码是系统的，则所选择的子集是奇偶校验位。

9. 发明申请

WO2007135657A3 ERROR CORRECTION DECODING BY TRIAL AND ERROR 审中-公开
标题翻译：错误修正通过尝试和错误解码
公开(公告)号：WO2007135657A3
公开(公告)日：2009-04-09
申请号：PCT/IL2006001248
申请日：2006-10-30
申请人： UNIV RAMOT , SHARON ERAN , ALROD IDAN , LITSYN SIMON
发明人： SHARON ERAN , ALROD IDAN , LITSYN SIMON
IPC分类号： H03M13/00
CPC分类号： H03M13/3738 , H03M13/3707 , H03M13/6502 , H03M13/6511
摘要： A representation of a codeword is decoded by applying a first decoder of the codeword to the representation of the codeword. If applying the first decoder fails to decode the representation of the codeword then a second decoder of the codeword is applied to the representation of the codeword. Preferably, applying the first decoder consumes less power and is faster than applying the second decoder. Data are ported by encoding the data as a codeword, exporting the codeword to a corrupting medium, importing a representation of the codeword, and applying a first decoder to the representation of the codeword. If applying the first decoder fails to decode the representation of the codeword then a second decoder of the codeword is applied to the representation of the codeword.
摘要翻译：通过将码字的第一解码器应用于码字的表示来解码码字的表示。如果应用第一解码器不能解码码字的表示，则码字的第二解码器被应用于码字的表示。优选地，应用第一解码器消耗较少的功率并且比应用第二解码器更快。数据通过将数据编码为码字来移植，将码字导出到破坏性介质，导入码字的表示，以及将第一解码器应用于码字的表示。如果应用第一解码器不能解码码字的表示，则码字的第二解码器被应用于码字的表示。

10. 发明申请

WO2008075351A2 SOFT DECODING OF HARD AND SOFT BITS READ FROM A FLASH MEMORY 审中-公开
标题翻译：从闪存中读取硬软位的软解码
公开(公告)号：WO2008075351A2
公开(公告)日：2008-06-26
申请号：PCT/IL2007001565
申请日：2007-12-19
申请人： UNIV RAMOT , ALROD IDAN , SHARON ERAN , LITSYN SIMON , LASSER MENAHEM
发明人： ALROD IDAN , SHARON ERAN , LITSYN SIMON , LASSER MENAHEM
IPC分类号： G11C16/26
CPC分类号： G11C11/5642 , G06F11/1068 , G06F11/1072 , G11C16/26 , G11C2211/5634
摘要： To read one or more flash memory cells, the threshold voltage of each cell is compared to at least one integral reference voltage and to at least one fractional reference voltage. Based on the comparisons, a respective estimate probability measure of each bit of an original bit pattern of each cell is calculated. This provides a plurality of estimated probability measures. Based at least in part on at least two of the estimated probability measures, respective original bit patterns of the cells are estimated. Preferably, the estimated probability measures are initial probability measures that are transformed to final probability measures under the constraint that the bit pattern(s) (collectively) is/are a member of a candidate set, e.g. a set of codewords.
摘要翻译：为了读取一个或多个闪存单元，将每个单元的阈值电压与至少一个积分参考电压和至少一个分数参考电压进行比较。基于比较，计算每个单元的原始位模式的每个位的相应估计概率度量。这提供了多个估计的概率测量。至少部分地基于估计的概率度量中的至少两个，估计单元的各个原始位模式。优选地，所估计的概率测量值是初始概率测量值，其在约束下（一个或多个）位模式（总称）是候选集的成员，例如，一组码字。

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