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1. 发明申请

WO2007043042A3 METHOD OF ERROR CORRECTION IN MBC FLASH MEMORY 审中-公开
标题翻译： MBC闪存中错误校正方法
公开(公告)号：WO2007043042A3
公开(公告)日：2008-12-31
申请号：PCT/IL2006001159
申请日：2006-10-04
申请人： UNIV RAMOT , LITSYN SIMON , ALROD IDAN , SHARON ERAN , MURIN MARK , LASSER MENACHEM
发明人： LITSYN SIMON , ALROD IDAN , SHARON ERAN , MURIN MARK , LASSER MENACHEM
IPC分类号： G11C29/00
CPC分类号： G06F11/1072
摘要： A plurality of logical pages is stored in a MBC flash memory (42) along with corresponding ECC bits, with at least one of the MBC cells storing bits from more than one logical page, and with at least one of the ECC bits applying to two or more of the logical pages. When the pages are read from the memory (42), the data bits as read are corrected using the ECC bits as read. Alternatively, a joint, systematic or non-systematic ECC codeword is computed for two or more of the logical pages and is stored instead of those logical pages. When the joint codeword is read, the logical bits are recovered from the codeword as read. The scope of the invention also includes corresponding memory devices (54, 56, 5S), the controllers of such memory devices (54, 56, 58), and also computer-readable storage media bearing computer-readable code for implementing the methods.
摘要翻译：多个逻辑页面与相应的ECC位一起存储在MBC闪速存储器（42）中，其中至少一个MBC单元存储来自多于一个逻辑页面的位，并且至少一个ECC位应用于两个或更多的逻辑页面。当从存储器（42）读取页面时，读取的数据位使用被读取的ECC位进行校正。或者，针对两个或多个逻辑页面计算联合的，系统的或非系统的ECC码字，并且存储该代码字而不是那些逻辑页面。当读取联合码字时，从读取的码字中恢复逻辑比特。本发明的范围还包括对应的存储设备（54,56,5S），这些存储设备（54,56,58）的控制器，以及用于实现该方法的具有计算机可读代码的计算机可读存储介质。

2. 发明申请

WO2007046084A2 PROBABILISTIC ERROR CORRECTION IN MULTI-BIT-PER-CELL FLASH MEMORY 审中-公开
标题翻译：多比特单元闪存中的概率误差校正
公开(公告)号：WO2007046084A2
公开(公告)日：2007-04-26
申请号：PCT/IL2006001175
申请日：2006-10-15
申请人： UNIV RAMOT , LITSYN SIMON , ALROD IDAN , SHARON ERAN , MURIN MARK , LASSER MENACHEM
发明人： LITSYN SIMON , ALROD IDAN , SHARON ERAN , MURIN MARK , LASSER MENACHEM
IPC分类号： G06F19/00
CPC分类号： G06F11/1068 , G06F11/1072 , G11C11/5642 , G11C2029/0409
摘要： Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.
摘要翻译：根据系统或非系统ECC存储在多比特单元存储器的单元中的数据根据估计的概率被读取和校正（系统ECC）或恢复（非系统ECC）更多的读取位是错误的。在本发明的一种方法中，估计是先验的。在本发明的另一种方法中，估计仅基于包括读位的重要性或位页的读位的方面。在本发明的第三种方法中，估计仅基于读位的值。并不是所有的估计是相等的。

3. 发明申请

WO2006064497A3 A METHOD OF HANDLING LIMITATIONS ON THE ORDER OF WRITING TO A NON-VOLATILE MEMORY 审中-公开
标题翻译：处理非易失性存储器订单限制的方法
公开(公告)号：WO2006064497A3
公开(公告)日：2006-12-07
申请号：PCT/IL2005001341
申请日：2005-12-13
申请人： MILSYS LTD , MURIN MARK , LASSER MENACHEM
发明人： MURIN MARK , LASSER MENACHEM
IPC分类号： G11C11/34
CPC分类号： G11C16/102 , G06F3/0626 , G06F3/0656 , G06F3/0659 , G06F3/0679 , G11C11/5628
摘要： Sectors of data are stored in a non-volatile memory (12) by writing all the sectors in a first order and subsequently writing all the sectors in a different, second order that is determined prior to the second writing. Sectors are stored in a non-volatile memory (12) by writing the sectors using a first set of write operations and again writing the sectors using a second set of write operations that write one or more of the sectors twice. The first set writes each sector only once and the second set writes the sectors from outside the memory (12). The first set writes in a mode that couples the cells of the memory (12) less than the second set. The first set writes less reliably than the second set.
摘要翻译：数据的扇区通过以第一顺序写入所有扇区并随后以在第二次写入之前确定的不同的第二阶段写入所有扇区来存储在非易失性存储器（12）中。扇区通过使用第一组写入操作写入扇区来存储在非易失性存储器（12）中，并且再次使用写入一个或多个扇区两次的第二写入操作来写入扇区。第一组写入每个扇区一次，第二组从存储器（12）外部写入扇区。第一组以一种将存储器（12）的单元小于第二组的模式写入。第一组写入的可靠性低于第二组。

4. 发明申请

WO2007029259A3 FRONT MEMORY STORAGE SYSTEM AND METHOD 审中-公开
标题翻译：前端存储系统和方法
公开(公告)号：WO2007029259A3
公开(公告)日：2007-11-15
申请号：PCT/IL2006001049
申请日：2006-09-07
申请人： SANDISK IL LTD , LASSER MENACHEM , MURIN MARK , EYAL ARIK
发明人： LASSER MENACHEM , MURIN MARK , EYAL ARIK
IPC分类号： G06F12/00
CPC分类号： G11C11/5621 , G06F12/0246 , G06F12/0866 , G06F2212/2022 , G06F2212/7211 , G11C16/349 , G11C16/3495 , G11C2211/5641
摘要： A flash memory storage system (10) includes a memory array (12) containing a plurality of memory cells (14) and a controller (16) for controlling the flash memory array (12). The controller (16) dedicates a first group of memory cells to operate with a first number of bits per cell and a second, separate group of memory cells (14) to operate with a second number of bits per cell. A mechanism is provided to apply wear leveling techniques separately to the two groups of cells to evenly wear out the memory cells (14).
摘要翻译：闪速存储器存储系统（10）包括包含多个存储器单元（14）的存储器阵列（12）和用于控制闪存阵列（12）的控制器（16）。控制器（16）专用于第一组存储器单元以每个单元的第一位数和第二单独的存储单元组（14）以每单元的第二位数来操作。提供了一种机制来将磨损均衡技术分别应用于两组细胞以均匀地磨损存储单元（14）。

5. 发明申请

WO2007049272A3 A METHOD FOR RECOVERING FROM ERRORS IN FLASH MEMORY 审中-公开
标题翻译：一种用于从闪速存储器中的错误中恢复的方法
公开(公告)号：WO2007049272A3
公开(公告)日：2009-04-09
申请号：PCT/IL2006001220
申请日：2006-10-24
申请人： SANDISK IL LTD , LASSER MENACHEM , MURIN MARK
发明人： LASSER MENACHEM , MURIN MARK
IPC分类号： G11C11/34
CPC分类号： G06F11/1072 , G06F11/1068 , G11C11/5642 , G11C16/28
摘要： Methods, devices and computer readable code for reading data from one or more flash memory cells, and for recovering from read errors are disclosed In some embodiments, in the event of an error correction failure by an error detection and correction module, the flash memory cells are re-read at least once using one or more modified reference voltages, for example, until a successful error correction may be earned out In some embodiments, after successful error correction a subsequent read request is handled without re- writing data (for example, reliable values of the read data) to the flash memory cells in the interim. In some embodiments, reference voltages associated with a reading where errors are corrected may be stored in memory, and retrieved when responding to a subsequent read request
摘要翻译：公开了用于从一个或多个闪速存储器单元读取数据以及从读取错误中恢复的方法，装置和计算机可读代码。在一些实施例中，在由错误检测和校正模块进行纠错故障的情况下，闪存单元使用一个或多个修改的参考电压至少重新读取一次，例如，直到可以获得成功的纠错。在一些实施例中，在成功的纠错之后，处理随后的读取请求而不重写数据（例如，读取数据的可靠值）到中间的闪存单元。在一些实施例中，与校正错误相关联的读数的参考电压可以存储在存储器中，并在响应随后的读取请求时被检索

6. 发明申请

WO2006072945A3 METHOD OF MANAGING A MULTI-BIT CELL FLASH MEMORY WITH IMPROVED RELIABILITY AND PERFORMANCE 审中-公开
标题翻译：管理具有改进的可靠性和性能的多位单元闪速存储器的方法
公开(公告)号：WO2006072945A3
公开(公告)日：2007-01-25
申请号：PCT/IL2006000012
申请日：2006-01-03
申请人： MILSYS LTD , LASSER MENACHEM , MURIN MARK
发明人： LASSER MENACHEM , MURIN MARK
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5621 , G11C16/0483 , G11C2211/5641
摘要： A method of storing data by providing a flash memory device (209) including a plurality of memory cells; each of the memory cells is capable of storing data bits. First data bits are stored into memory cells used for storing M bits per cell (212), the memory cells are allocated to a page of the memory (113). Second data bits are stored into other memory cells, the other memory cells used for storing N bits per cell (210) are allocated to the page and upon storing of the first data bits and upon storing the second data bits, the page uses at the same time at least one of the memory cells with M bits per cell and at least one of the other memory cells with N bits per cell with N less than M.
摘要翻译：一种通过提供包括多个存储器单元的闪速存储器件（209）来存储数据的方法; 每个存储单元能够存储数据位。第一数据位被存储到用于存储每个单元的M位（212）的存储器单元中，存储器单元被分配给存储器（113）的页面。第二数据位被存储到其他存储单元中，用于存储每个单元（210）的N位的其他存储单元被分配给页面，并且在存储第一数据位时，并且在存储第二数据位时，页面在同时每个单元具有M位的至少一个存储器单元以及具有N个小于M的每个单元的N位的其它存储单元中的至少一个存储单元。

7. 发明申请

WO2006048861A3 STATES ENCLODING IN MULTI-BIT FLASH CELLS FOR OPTIMIZING ERRROR RATE 审中-公开
标题翻译：用于优化误码率的多点闪存中的状态
公开(公告)号：WO2006048861A3
公开(公告)日：2008-01-10
申请号：PCT/IL2005001116
申请日：2005-10-26
申请人： MILSYS LTD , MURIN MARK
发明人： MURIN MARK
IPC分类号： G06F12/00
CPC分类号： G11C11/5628
摘要： To store N bits of M=2 logical pages, the bits are interleaved and the interleaved bits are programmed to [N/M] memory cells, M bits per cell. Preferably, the interleaving puts the same number of bits from each logical page into each bit-page of the [N/M] cells. When the bits are read from the cells, the bits are de-interleaved. The interleaving may be deterministic or random, and may be effected by software or by dedicated hardware.
摘要翻译：为了存储M = 2个逻辑页的N位，这些位被交织，并且交织位被编程到[N / M]个存储单元，每个单元M位。优选地，交织将来自每个逻辑页的相同数量的比特放入[N / M]个小区的每个比特页。当从单元读取这些位时，这些位被解交织。交织可以是确定性的或随机的，并且可以由软件或专用硬件实现。

8. 发明申请

WO2008004216A3 MULTI-BIT-PER-CELL FLASH MEMORY DEVICE WITH AN EXTENDED SET OF COMMANDS 审中-公开
标题翻译：具有扩展的命令集的多位单元闪存存储器件
公开(公告)号：WO2008004216A3
公开(公告)日：2009-04-30
申请号：PCT/IL2007000814
申请日：2007-07-01
申请人： SANDISK IL LTD , MURIN MARK
发明人： MURIN MARK
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C8/10 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C2211/5621 , G11C2211/5634
摘要： A multi-bit-per-cell flash memory device supports a command such that each invocation of the command by the device's host changes respective values of one or more types of reference voltage (e.g., all read reference voltages and/or all program verify reference voltages) of the device to respective new values.
摘要翻译：多单元闪存设备支持命令，使得设备主机对命令的每次调用改变一种或多种类型的参考电压的相应值（例如，所有读取的参考电压和/或所有程序验证参考电压）到相应的新值。

9. 发明申请

WO2007083303A2 A METHOD OF ARRANGING DATA IN A MULTI-LEVEL CELL MEMORY DEVICE 审中-公开
标题翻译：一种在多级存储器件中安排数据的方法
公开(公告)号：WO2007083303A2
公开(公告)日：2007-07-26
申请号：PCT/IL2007000061
申请日：2007-01-17
申请人： SANDISK IL LTD , MURIN MARK
发明人： MURIN MARK
IPC分类号： H03M13/00
CPC分类号： G11C11/5621 , G06F11/1068 , G06F11/1072 , G11C11/5628 , G11C16/0483 , G11C29/00
摘要： A method of storing data includes storing a first portion of data in bit positions of a non-volatile memory having a first probability of error; storing a second portion of the data in bit positions of the non-volatile memory having a second probability of error, wherein the second probability of error is lower than the first probability of error; storing error correction parity bits with the data; and applying an error correction scheme to read data using the error correction parity bits, wherein at least one bit of the first portion is checked for correction before any bit of the second portion is checked for correction. The error correction scheme is stopped before checking for correcting of all the data.
摘要翻译：存储数据的方法包括：将具有第一误差概率的非易失性存储器的位位置中的数据的第一部分存储; 将所述数据的第二部分存储在具有第二误差概率的所述非易失性存储器的比特位置中，其中所述第二误差概率低于所述第一误差概率; 存储纠错奇偶校验位与数据; 以及使用纠错奇偶校验位来应用纠错方案来读取数据，其中在检查所述第二部分的任何位之前检查所述第一部分的至少一位以进行校正。在检查所有数据的校正之前，停止纠错方案。

10. 发明申请

WO2007052259A3 A METHOD, SYSTEM AND COMPUTER-READABLE CODE FOR TESTING OF FLASH MEMORY 审中-公开
标题翻译：用于测试闪存的方法，系统和计算机可读代码
公开(公告)号：WO2007052259A3
公开(公告)日：2009-04-16
申请号：PCT/IL2006001247
申请日：2006-10-30
申请人： SANDISK IL LTD , MURIN MARK , LASSER MENAHEM , AVRAHAM MEIR
发明人： MURIN MARK , LASSER MENAHEM , AVRAHAM MEIR
IPC分类号： G11C7/00
CPC分类号： G11C29/16 , G11C11/5621 , G11C16/04 , G11C2029/0401
摘要： Methods, systems and devices for testing flash memory dies are disclosed. According to some embodiments, during the post-wafer sort stage of device manufacture, a plurality of flash memory devices, each of which includes a flash controller die and at least one flash memory die associated with a common housing, are subjected to a testing process, for examples, a batch testing process or a mass testing process. During testing, a respective flash controller residing on a respective flash controller die executes at least one test program to test one or more respective flash memory dies of the respective flash device. A testing system including at least 100 of the flash memory devices and a mass-testing board is disclosed. Furthermore, flash memory devices where the flash controller is operative to test one or more of the flash memory dies are disclosed. Exemplary testing includes but is not limited to bad block testing.
摘要翻译：公开了用于测试闪存芯片的方法，系统和设备。根据一些实施例，在器件制造的后晶片分类阶段期间，多个闪存器件（其中每个闪存器件包括闪存控制器管芯和与公共壳体相关联的至少一个闪存管芯）经受测试过程例如，批量测试过程或批量测试过程。在测试期间，位于相应的闪存控制器芯片上的相应的闪存控制器执行至少一个测试程序来测试相应闪存设备的一个或多个相应的闪存存储器管芯。公开了一种包括至少100个闪存器件和质量检测板的测试系统。此外，公开了闪存控制器用于测试一个或多个闪速存储器管芯的闪存器件。示例性测试包括但不限于坏块测试。

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