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1. 发明申请

WO2018048490A1 BLOCK HEALTH MONITORING USING THRESHOLD VOLTAGE OF DUMMY MEMORY CELLS 审中-公开
标题翻译：基于虚电内存阈值电压的健康监测
公开(公告)号：WO2018048490A1
公开(公告)日：2018-03-15
申请号：PCT/US2017/034891
申请日：2017-05-28
申请人： SANDISK TECHNOLOGIES LLC
发明人： PANG, Liang , YU, Xuehong , DONG, Yingda , YANG, Nian Niles
IPC分类号： G11C16/34 , G11C7/14 , G11C16/04 , G11C11/56
摘要： Techniques are provided for measuring the endurance of a set of data memory cells by evaluating the threshold voltage (Vth) of associated dummy memory cells. A cell has a high endurance or good data retention if it is able to maintain the charges. However, there can be a variation in the endurance of cells even within a single die. By evaluating the dummy memory cells, an early warning can be obtained of a degradation of the data memory cells. Moreover, there is no interference with the operation of the data memory cells. Based on a number of dummy memory cells which have a Vth below a demarcation voltage, a corrective action is taken such as adjusting read voltages, an initial program voltage and/or an initial erase voltage, or marking the block as being bad and recovering the data.
摘要翻译：通过评估关联的虚存储单元的阈值电压（Vth）来提供用于测量一组数据存储单元的耐久性的技术。如果电池能够维持充电，则电池具有高耐久性或良好的数据保留。但是，即使在一个模具内，电池的耐久性也可能有所不同。通过评估伪存储单元，可以获得数据存储单元退化的预警。而且，不会干扰数据存储单元的操作。基于具有低于分界电压Vth的虚拟存储器单元的数量，采取诸如调整读取电压，初始编程电压和/或初始擦除电压的校正动作，或者将块标记为坏并且恢复数据

2. 发明申请

WO2018022184A1 NON-VOLATILE MEMORY WITH REDUCED PROGRAM SPEED VARIATION 审中-公开
标题翻译：非易失性存储器，程序速度变化较小
公开(公告)号：WO2018022184A1
公开(公告)日：2018-02-01
申请号：PCT/US2017/034888
申请日：2017-05-28
申请人： SANDISK TECHNOLOGIES LLC
发明人： BARASKAR, Ashish , PANG, Liang , ZHANG, Yanli , MAKALA, Raghuveer , DONG, Yingda
IPC分类号： H01L27/11556 , H01L27/11582 , H01L29/788 , H01L29/792
摘要： A three-dimensional non-volatile memory is provided with reduced programming variation across word lines. The gate lengths of word lines decrease from the top to the bottom of the memory hole. Increased programming speeds due to a narrow memory hole are offset by a smaller gate length at corresponding positions. A blocking dielectric thickness may also be varied, independently or in combination with a variable word line thickness. The blocking dielectric is formed with a horizontal thickness that is larger at regions adjacent to the lower word line layers and smaller at regions adjacent to the upper word line layers. The larger thickness at the lower word line layers reduces the programming speed in the memory hole for the lower word lines relative to the upper word lines. A variance in programming speed resulting from differences in memory hole diameter may be offset by a corresponding variance in blocking dielectric thickness.
摘要翻译：三维非易失性存储器具有跨越字线的减少的编程变化。字线的栅极长度从记忆孔的顶部到底部逐渐减小。由于存储空间狭窄，编程速度的提高被相应位置的较小栅极长度所抵消。阻挡电介质厚度也可以独立地或与可变字线厚度结合地变化。阻挡电介质形成有水平厚度，该水平厚度在与下字线层相邻的区域处更大并且在与上字线层相邻的区域处更小。较低字线层的较大厚度降低了较低字线相对于较高字线的存储空间中的编程速度。由于记忆孔直径的差异导致的编程速度的变化可能被阻挡电介质厚度的相应变化所抵消。

3. 发明申请

WO2017204871A1 WORD LINE-DEPENDENT AND TEMPERATURE-DEPENDENT ERASE DEPTH 审中-公开
标题翻译：字线取决于和温度相关的擦除深度
公开(公告)号：WO2017204871A1
公开(公告)日：2017-11-30
申请号：PCT/US2017/018551
申请日：2017-02-19
申请人： SANDISK TECHNOLOGIES LLC
发明人： PANG, Liang , DIEP, Vinh , LU, Ching-Huang , DONG, Yingda
IPC分类号： G11C7/04 , G11C16/16 , H01L27/06 , G11C11/56
CPC分类号： G11C7/14 , G11C7/04 , G11C7/062 , G11C7/22 , G11C11/5635 , G11C16/0483 , G11C16/16 , H01L27/1157 , H01L27/11582
摘要： Techniques are provided for reducing program disturb and short term data retention loss. Program disturb becomes worse for the drain-side memory cells at higher temperatures, while data retention generally does not become worse at higher temperatures. In one aspect, a deeper erase is provided for drain-side memory cells when the temperature is relatively high, to reduce program disturb. In another aspect, the verify levels of the programmed data states are lowered to reduce data retention loss when the temperature is relatively high. In another aspect, the number of read errors is used to adjust the depth of the depth of the erase operation. In another aspect, a pass voltage of a drain-side cell is lowered during a verify test for another cell to account for the deep erase of the drain-side cell.
摘要翻译：
提供了减少编程干扰和短期数据保留丢失的技术。较高温度下漏极侧存储单元的编程干扰会变得更糟，而在较高温度下数据保持性通常不会变差。在一个方面，当温度相对较高时，为漏极侧存储器单元提供更深的擦除，以减少编程干扰。另一方面，当温度较高时，编程数据状态的验证电平被降低以减少数据保持损失。在另一方面，读取错误的数量被用来调整擦除操作的深度的深度。在另一方面，漏极侧单元的通过电压在另一个单元的验证测试期间降低，以解释漏极侧单元的深度擦除。

4. 发明申请

WO2017184248A1 WORD LINE-DEPENDENT AND TEMPERATURE-DEPENDENT PASS VOLTAGE DURING PROGRAMMING 审中-公开
标题翻译：字编程中与字线有关且与温度相关的通过电压
公开(公告)号：WO2017184248A1
公开(公告)日：2017-10-26
申请号：PCT/US2017/018545
申请日：2017-02-19
申请人： SANDISK TECHNOLOGIES LLC
发明人： PANG, Liang , DONG, Yingda , YUAN, Jiahui , REN, Jingjian
IPC分类号： G11C16/34 , G11C7/04 , G11C16/10 , G11C16/04 , G11C11/56
CPC分类号： G11C16/10 , G11C7/04 , G11C11/5628 , G11C11/5671 , G11C16/0483 , G11C16/3427 , G11C16/3486
摘要： Techniques are provided for avoiding over-programming can occur on memory cells connected to a data word line at a source-side of a block of word lines. A gradient in the channel potential is created during a program voltage between the data word line and an adjacent dummy word line. This gradient generates electron-hole pairs which can contribute to over programming, where the over programming is worse at higher temperatures. In one aspect, pass voltages of unselected word lines are set to be relatively lower when the temperature is relatively higher, and when the selected word line is among a set of one or more source-side word lines. On the other hand, the pass voltages are set to be relatively higher when the temperature is relatively higher, and when the selected word line is not among the one or more source-side word lines.
摘要翻译：提供了用于避免在连接到字线块的源侧的数据字线的存储单元上发生过度编程的技术。在数据字线和相邻虚拟字线之间的编程电压期间，产生沟道电位的梯度。这种梯度会产生电子空穴对，这可能导致编程过度，在较高的温度下编程过度会变得更糟。在一个方面，当温度相对较高时，以及当所选字线位于一组一个或多个源侧字线中时，未选字线的通过电压被设置为相对较低。另一方面，当温度相对较高并且所选字线不在一个或多个源侧字线中时，通过电压被设置为相对较高。

5. 发明申请

WO2018080644A1 DYNAMIC READ FOR A NAND MEMORY 审中-公开
标题翻译：动态读取NAND内存
公开(公告)号：WO2018080644A1
公开(公告)日：2018-05-03
申请号：PCT/US2017/050568
申请日：2017-09-07
申请人： SANDISK TECHNOLOGIES LLC
发明人： ALROD, Idan , SHARON, Eran , EYAL, Alon , PANG, Liang , MEKHANIK, Evgeny
IPC分类号： G11C11/56 , G11C16/26 , G11C16/32 , G06F11/10
摘要： Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.
摘要翻译：提供了用于提高存储器单元的读取操作的准确性的技术，其中存储器单元的阈值电压可以根据读取操作何时发生而移位。通过将感测节点放电到位线中并且在相对于跳闸电压的两个感测时间处检测放电量来感测存储器单元。基于两个传感时间将一些数据存储在第一和第二锁存器中，以提供第一和第二页数据。使用奇偶校验方程来评估页面，并且选择满足最多等式的页面之一。在另一种选择中，字线电压接地，然后浮动以防止字线耦合。弱地下拉可以逐渐释放字线的耦合电压。

6. 发明申请

WO2018017181A1 THREE-DIMENSIONAL MEMORY DEVICE WITH SELECT TRANSISTOR HAVING CHARGE TRAPPING GATE DIELECTRIC LAYER AND METHODS OF MAKING AND OPERATING THEREOF 审中-公开
标题翻译：具有选择晶体管的三维存储器装置，具有电荷捕获闸极介电层及其制造和操作方法
公开(公告)号：WO2018017181A1
公开(公告)日：2018-01-25
申请号：PCT/US2017/032727
申请日：2017-05-15
申请人： SANDISK TECHNOLOGIES LLC
发明人： BARASKAR, Ashish , ZHANG, Yanli , PANG, Liang , LU, Ching-Huang , BAENNINGER, Matthias , DONG, Yingda
IPC分类号： H01L27/1157 , H01L27/11582
CPC分类号： H01L27/11582 , H01L21/02164 , H01L21/02271 , H01L27/1157 , H01L29/40117
摘要： A gate dielectric layer including a tunneling gate dielectric layer, a charge trapping gate dielectric layer, and a cap gate dielectric layer is formed on a horizontal semiconductor channel. An alternating stack of insulating layers and spacer material layers is formed over the gate dielectric layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conducive layers. Memory stack structures are formed through the alternating stack and the gate dielectric layer. Electrical charges can be injected into the charge trapping gate dielectric layer from the horizontal semiconductor channel to program the threshold voltage of a select field effect transistor employing a bottommost electrically conductive layer as a select gate electrode. The programmable threshold voltage can be advantageously employed to provide enhanced electrical isolation among word lines.
摘要翻译：在水平半导体沟道上形成包括隧穿栅极电介质层，电荷俘获栅极电介质层和帽栅极电介质层的栅极电介质层。在栅介质层上形成交替的绝缘层和间隔材料层的叠层。间隔物材料层形成为导电层或随后替换为导电层。存储器堆叠结构通过交替堆叠和栅极电介质层形成。可以将电荷从水平半导体沟道注入到电荷俘获栅极介电层中，以将采用最底部导电层的选择场效应晶体管的阈值电压编程为选择栅电极。可编程的阈值电压可以有利地用于提供字线之间的增强的电隔离。

7. 发明申请

WO2018004753A1 WEAK ERASE PRIOR TO READ 审中-公开
标题翻译：在读取前弱擦除
公开(公告)号：WO2018004753A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/019591
申请日：2017-02-27
申请人： SANDISK TECHNOLOGIES LLC
发明人： PANG, Liang , DONG, Yingda , YU, Xuehong , REN, Jingjian
IPC分类号： G11C16/34 , G11C16/26
CPC分类号： G11C16/26 , G11C7/04 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/24 , G11C16/3459
摘要： Techniques are disclosed for accurately sensing memory cells without having to wait for a voltage that creeps up on word line after a sensing operation to die down. The word line creep up could cause electrons to trap in shallow interface traps of a memory cell, hence impacting its threshold voltage. In one aspect, trapped electrons are removed (e.g., de-trapped) from shallow interface traps of a memory cell using a weak erase operation. Therefore, problems associated with word line voltage creep up are reduced or prevented. Thus, the memory cell can be sensed without waiting, while still providing an accurate result. The weak erase could be part of a sensing operation, but that is not required. For example, the weak erase could be incorporated into the beginning part of a read operation, which provides for a very efficient solution.
摘要翻译：公开了用于精确地感测存储器单元而不必等待在感测操作停止之后在字线上爬升的电压的技术。字线蠕变可能导致电子陷入存储器单元的浅界面陷阱中，从而影响其阈值电压。在一个方面中，使用弱擦除操作从存储器单元的浅界面陷阱移除（例如，解俘获）俘获的电子。因此，减少或防止了与字线电压蠕变相关的问题。因此，可以在不等待的情况下感测存储器单元，同时仍然提供准确的结果。弱擦除可能是感测操作的一部分，但这不是必需的。例如，弱擦除可以包含在读操作的开始部分，这提供了非常有效的解决方案。

8. 发明申请

WO2018004752A1 WORD LINE RAMPING DOWN SCHEME TO PURGE RESIDUAL ELECTRONS 审中-公开
标题翻译： WORD LINE缓降方案来清除残余电子
公开(公告)号：WO2018004752A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/019590
申请日：2017-02-27
申请人： SANDISK TECHNOLOGIES LLC
发明人： DONG, Yingda , YU, Xuehong , PANG, Liang
IPC分类号： G11C16/34 , G11C16/26 , G11C16/32
摘要： Techniques are disclosed for accurately sensing memory cells without having to wait for a voltage that creeps up on word line after a sensing operation to die down. In one aspect, a read pass voltage is discharged in a manner that purges residual electrons from a memory string channel after a sensing operation. A control circuit may begin to discharge the read pass voltage from memory cell control gates at different strategic times in order to provide a path for residual electrons to leave the channel. Because residual electrons have been purged from the channel, no or very few electrons will be trapped in shallow interface traps of the memory cell if the word line voltage does creep up following sensing. Thus, the word line voltage may still creep up after the sensing operation without changing a threshold voltage of the memory cell.
摘要翻译：公开了用于精确地感测存储器单元而不必等待在感测操作停止之后在字线上爬升的电压的技术。在一个方面，读取通过电压以在感测操作之后从存储器串沟道中清除残余电子的方式被放电。控制电路可以开始在不同的战略时间从存储单元控制栅极释放读取通过电压，以便为残余电子离开通道提供路径。因为残余电子已从通道中清除，所以如果字线电压在感测之后蠕变上升，那么在存储器单元的浅界面陷阱中不会或很少电子被俘获。因此，在感测操作之后，字线电压可能仍然蠕变而不改变存储单元的阈值电压。

9. 发明申请

WO2017222605A1 AMORPHOUS SILICON LAYER IN MEMORY DEVICE WHICH REDUCES NEIGHBORING WORD LINE INTERFERENCE 审中-公开
标题翻译：存储设备中减少相邻字词干扰的非晶硅层
公开(公告)号：WO2017222605A1
公开(公告)日：2017-12-28
申请号：PCT/US2017/018759
申请日：2017-02-21
申请人： SANDISK TECHNOLOGIES LLC
发明人： PANG, Liang , PACHAMUTHU, Jayavel , DONG, Yingda
IPC分类号： H01L29/66 , H01L29/788 , H01L29/792 , H01L27/11548 , H01L27/11563 , H01L27/11556 , H01L27/11582
CPC分类号： H01L27/11582 , H01L21/02164 , H01L21/0217 , H01L21/02238 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/02667 , H01L21/31111 , H01L27/11568 , H01L29/40117 , H01L29/42368 , H01L29/66545 , H01L29/66666 , H01L29/66833 , H01L29/7827 , H01L29/7926
摘要： Techniques for fabricating a memory device which has reduced neighboring word line interference, and a corresponding memory device. The memory device comprises a stack of alternating conductive and dielectric layers, where the conductive layers form word lines or control gates of memory cells. In one aspect, rounding off of the control gate layers due to inadvertent oxidation during fabrication is avoided. An amorphous silicon layer is deposited along the sidewall of the memory holes, adjacent to the control gate layers. Si 3 N 4 is deposited along the amorphous silicon layer and oxidized in the memory hole to form SiO 2 . The amorphous silicon layer acts as an oxidation barrier for the sacrificial material of the control gate layers. The amorphous silicon layer is subsequently oxidized to also form SiO 2 . The two SiO 2 layers together form a blocking oxide layer.
摘要翻译：制造具有减小的邻近字线干扰的存储器件的技术以及相应的存储器件。存储器件包括交替的导电层和介电层的堆叠，其中导电层形成存储器单元的字线或控制栅极。在一个方面中，避免了由于在制造期间的意外氧化而使控制栅极层四舍五入。非晶硅层沿存储器孔的侧壁沉积，与控制栅极层相邻。 Si 3 N 4沿非晶硅层沉积并在记忆孔中氧化形成SiO 2。非晶硅层充当用于控制栅极层的牺牲材料的氧化阻挡层。随后将非晶硅层氧化以形成SiO 2 2。两个SiO 2层一起形成阻挡氧化层。

10. 发明申请

WO2018160242A1 FORMING MEMORY CELL FILM IN STACK OPENING 审中-公开
公开(公告)号：WO2018160242A1
公开(公告)日：2018-09-07
申请号：PCT/US2017/063398
申请日：2017-11-28
申请人： SANDISK TECHNOLOGIES LLC
发明人： BARASKAR, Ashish , PANG, Liang , ZHANG, Yanli , LU, Ching-Huang , DONG, Yingda
IPC分类号： H01L27/1158 , H01L27/11524 , H01L27/11553 , H01L27/1157
CPC分类号： H01L27/11519 , H01L21/823412 , H01L27/11524 , H01L27/11526 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11582
摘要： Disclosed herein are methods of forming non-volatile storage. An opening may be etched through a stack of two alternating materials to a semiconductor substrate. A silicon nitride film may be formed on a vertical sidewall of the opening. The semiconductor substrate may be cleaned to remove oxide from the semiconductor substrate. The silicon nitride film protects the materials in the stack while cleaning the semiconductor substrate. The silicon nitride film may be converted to an oxide after cleaning the semiconductor substrate. A semiconductor region may be formed in contact with the cleaned semiconductor substrate. A memory cell film may be formed over the oxide in the opening. Control gates may be formed by replacing one of the materials in the stack with a conductive material. The oxide may serve as a blocking layer between the control gates and charge storage regions in the memory cell film.

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