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1. 发明申请

WO2018080644A1 DYNAMIC READ FOR A NAND MEMORY 审中-公开
标题翻译：动态读取NAND内存
公开(公告)号：WO2018080644A1
公开(公告)日：2018-05-03
申请号：PCT/US2017/050568
申请日：2017-09-07
申请人： SANDISK TECHNOLOGIES LLC
发明人： ALROD, Idan , SHARON, Eran , EYAL, Alon , PANG, Liang , MEKHANIK, Evgeny
IPC分类号： G11C11/56 , G11C16/26 , G11C16/32 , G06F11/10
摘要： Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.
摘要翻译：提供了用于提高存储器单元的读取操作的准确性的技术，其中存储器单元的阈值电压可以根据读取操作何时发生而移位。通过将感测节点放电到位线中并且在相对于跳闸电压的两个感测时间处检测放电量来感测存储器单元。基于两个传感时间将一些数据存储在第一和第二锁存器中，以提供第一和第二页数据。使用奇偶校验方程来评估页面，并且选择满足最多等式的页面之一。在另一种选择中，字线电压接地，然后浮动以防止字线耦合。弱地下拉可以逐渐释放字线的耦合电压。

2. 发明申请

WO2017151474A1 TEMPERATURE VARIATION COMPENSATION OF A MEMORY 审中-公开
标题翻译：记忆的温度变化补偿
公开(公告)号：WO2017151474A1
公开(公告)日：2017-09-08
申请号：PCT/US2017/019612
申请日：2017-02-27
申请人： SANDISK TECHNOLOGIES LLC
发明人： SHARON, Eran , YANG, Nian Niles , ALROD, Idan , MEKHANIK, Evgeny , SHLICK, Mark , LAI, Joanna
IPC分类号： G11C7/04 , G11C11/56 , G11C16/10 , G11C16/26 , G11C16/34
摘要： A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.
摘要翻译：数据存储设备被配置为响应于确定与向存储器写入数据相关联的第一测量温度超过第一阈值而标记用于刷新的数据。数据存储设备进一步被配置为响应于确定与存储器相关联的第二测量温度低于第二阈值而刷新标记数据。

3. 发明申请

WO2017074589A1 SYSTEMS AND METHODS TO COMPENSATE FOR THRESHOLD VOLTAGE SHIFTS 审中-公开
标题翻译：用于补偿阈值电压偏移的系统和方法
公开(公告)号：WO2017074589A1
公开(公告)日：2017-05-04
申请号：PCT/US2016/051810
申请日：2016-09-15
申请人： SANDISK TECHNOLOGIES LLC
发明人： SHARON, Eran , ALROD, Idan , DUTTA, Deepanshu
IPC分类号： G11C7/04 , G11C16/26 , G11C16/34 , G11C11/56
CPC分类号： G11C16/3404 , G06F11/1068 , G11C7/04 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C16/3418 , G11C16/3436 , G11C16/3459 , G11C16/349 , G11C29/52
摘要： A data storage device includes a memory including multiple storage elements. The data storage device also includes circuitry configured to determine, for a particular storage element of the multiple storage elements, an indicator associated with a threshold voltage temperature dependence (TVTD) of the particular storage element.
摘要翻译：数据存储设备包括包含多个存储元件的存储器。数据存储设备还包括被配置为针对多个存储元件中的特定存储元件确定与特定存储元件的阈值电压温度依赖性（TVTD）相关联的指示符的电路。

4. 发明申请

WO2017062148A1 DATA ENCODING TECHNIQUES FOR A DEVICE 审中-公开
标题翻译：用于设备的数据编码技术
公开(公告)号：WO2017062148A1
公开(公告)日：2017-04-13
申请号：PCT/US2016/051849
申请日：2016-09-15
申请人： SANDISK TECHNOLOGIES LLC
发明人： HU, Xinde , PETTI, Christopher John , SHARON, Eran , ALROD, Idan , NAVON, Ariel
IPC分类号： G11C7/10 , G11C13/00 , G06F11/10
CPC分类号： G06F11/1068 , G06F11/1048 , G11C7/1006 , G11C13/0059 , G11C13/0069 , G11C29/52 , H03M13/2906
摘要： A data storage device includes a controller and a non-volatile memory coupled to the controller. The controller is configured to generate first parity information based on first data and to generate second parity information based on second data. The non-volatile memory is configured to store the first data and the second data. The data storage device also includes a buffer configured to store the first parity information. The controller is further configured to generate joint parity information associated with the first data and the second data in response to a combined data size of the first data and the second data satisfying a threshold.
摘要翻译：数据存储设备包括耦合到控制器的控制器和非易失性存储器。控制器被配置为基于第一数据生成第一奇偶校验信息，并且基于第二数据生成第二奇偶校验信息。非易失性存储器被配置为存储第一数据和第二数据。数据存储装置还包括被配置为存储第一奇偶校验信息的缓冲器。所述控制器还被配置为响应于所述第一数据和所述第二数据的组合数据大小满足阈值，生成与所述第一数据和所述第二数据相关联的联合奇偶校验信息。

5. 发明申请

WO2018164744A1 WORD LINE VOLTAGE DETECTION FOR SELECTION OF READ VOLTAGES IN NON-VOLATILE MEMORY 审中-公开
公开(公告)号：WO2018164744A1
公开(公告)日：2018-09-13
申请号：PCT/US2017/063670
申请日：2017-11-29
申请人： SANDISK TECHNOLOGIES LLC
发明人： DUTTA, Deepanshu , ALROD, Idan , TSENG, Huai-Yuan , DESAI, Amul , WAN, Jun , CHEAH, Ken , PUTHENTHERMADAM, Sarath
IPC分类号： G11C8/08 , G11C16/08 , G11C29/02
摘要： Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected based on an evaluation of the detected word line voltage. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.

6. 发明申请

WO2016153560A1 UPDATING RESISTIVE MEMORY 审中-公开
标题翻译：更新电阻记忆
公开(公告)号：WO2016153560A1
公开(公告)日：2016-09-29
申请号：PCT/US2015/061276
申请日：2015-11-18
申请人： SANDISK TECHNOLOGIES LLC
发明人： NAVON, Ariel , ALROD, Idan , SHARON, Eran , GOLDENBERG, Idan , GUR, Didi
IPC分类号： G11C13/00 , G06F11/10
CPC分类号： G11C13/0069 , G06F11/1048 , G06F11/1056 , G06F11/1068 , G11C13/0033 , G11C13/004 , G11C13/0097 , G11C29/52 , G11C2013/0076 , G11C2013/0085
摘要： Data is initially programmed in a portion of ReRAM in parallel. Subsequently, one or more ReRAM cells in the portion are determined to contain first data that is to be modified while remaining ReRAM cells in the portion contain second data that is not to be modified. First conditions are applied to the one or more ReRAM cells thereby modifying the first data, while second conditions are applied to the remaining ReRAM cells, the second conditions maintaining the second data in the remaining ReRAM cells without significant change.
摘要翻译：数据最初在ReRAM的一部分并行编程。随后，该部分中的一个或多个ReRAM单元被确定为包含待修改的第一数据，而该部分中的剩余ReRAM单元包含不被修改的第二数据。第一条件被应用于一个或多个ReRAM单元，从而修改第一数据，而第二条件被应用于剩余的ReRAM单元，第二条件保持剩余的ReRAM单元中的第二数据而没有显着变化。

7. 发明申请

WO2017160488A1 ERROR CORRECTION CODE PROCESSING AND DATA SHAPING 审中-公开
标题翻译：错误纠正码处理和数据整形
公开(公告)号：WO2017160488A1
公开(公告)日：2017-09-21
申请号：PCT/US2017/019456
申请日：2017-02-24
申请人： SANDISK TECHNOLOGIES LLC
发明人： ALROD, Idan , SHARON, Eran , NAVON, Ariel
IPC分类号： G06F11/10
CPC分类号： G06F3/0604 , G06F3/064 , G06F3/0679 , G06F11/1012 , G06F11/1068 , G06F2212/40 , G06F2212/401 , G06F2212/403 , G11C16/34 , G11C16/3418 , G11C16/349 , G11C16/3495 , G11C29/52 , G11C2211/5647
摘要： A device includes a memory and a controller including a data shaping engine. The data shaping engine is configured to apply a mapping to input data that includes one or more m-tuples of bits to generate transformed data. The transformed data includes one or more n-tuples of bits, and n is greater than m. A relationship of a gray coding of m-tuples to a gray coding of n-tuples is indicated by the mapping. The input data includes a first number of bit values that represent a particular logical state, and the transformed data includes a second number of bit values that represent the particular logical state, the second number of bit values being less than the first number of bit values.
摘要翻译：一种设备包括存储器和包括数据整形引擎的控制器。数据整形引擎被配置为将映射应用于包括一个或多个m位元组的元素的输入数据以生成变换后的数据。经变换的数据包括一个或多个比特的n元组，并且n大于m。通过映射指示m元组的灰度编码与n元组的灰度编码之间的关系。输入数据包括表示特定逻辑状态的第一数量的比特值，并且变换后的数据包括表示特定逻辑状态的第二数量的比特值，比特值的第二数量小于第一比特值数量

8. 发明申请

WO2017058523A1 DATA STORAGE DEVICE WITH A MEMORY DIE THAT INCLUDES AN INTERLEAVER 审中-公开
标题翻译：具有包含交互器的存储器的数据存储设备
公开(公告)号：WO2017058523A1
公开(公告)日：2017-04-06
申请号：PCT/US2016/051807
申请日：2016-09-15
申请人： SANDISK TECHNOLOGIES LLC
发明人： SHARON, Eran , NAVON, Ariel , CHU, Alexander Tsang-nam , TSAI, Wanfang , ALROD, Idan
IPC分类号： G06F3/06 , G06F11/10
CPC分类号： G06F11/1072 , G06F3/0611 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F3/0688 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/26 , G11C29/52 , H03M13/2792
摘要： A data storage device includes a set of latches, read/write circuitry, a memory, and an interleaver. The set of latches is configured to receive data. The read/write circuitry is coupled to the set of latches. The memory is coupled to the read/write circuitry. The interleaver is configured to interleave the data and to cause the read/write circuitry to program the interleaved data to the memory. The set of latches, the read/write circuitry, the memory, and the interleaver are integrated within a common die.
摘要翻译：数据存储设备包括一组锁存器，读/写电路，存储器和交织器。锁存器组被配置为接收数据。读/写电路耦合到该组锁存器。存储器耦合到读/写电路。交织器被配置为交织数据并使得读/写电路将交织的数据编程到存储器。锁存器组，读/写电路，存储器和交织器集成在公共管芯内。

9. 发明申请

WO2017027094A1 SOFT BIT TECHNIQUES FOR READING A DATA STORAGE DEVICE 审中-公开
标题翻译：用于读取数据存储设备的软比特技术
公开(公告)号：WO2017027094A1
公开(公告)日：2017-02-16
申请号：PCT/US2016/036912
申请日：2016-06-10
申请人： SANDISK TECHNOLOGIES LLC
发明人： SHARON, Eran , NAVON, Ariel , ALROD, Idan , BAZARSKY, Alexander
IPC分类号： G11C11/56 , G11C16/28
CPC分类号： G06F11/1048 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1068 , G11C11/5642 , G11C16/28 , G11C29/52
摘要： A data storage device includes a memory, a first module, and a second module. The first module is configured to sense data stored at the memory to generate a first set of soft bits having a first number of bits. The second module is configured to perform an operation using the first set of soft bits to generate a second set of soft bits having a second number of bits that is less than the first number of bits. In an illustrative implementation, the second set of soft bits is used in connection with a three-stage decoding process to decode a set of hard bits that represents the data.
摘要翻译：数据存储装置包括存储器，第一模块和第二模块。第一模块被配置为感测存储在存储器中的数据，以产生具有第一位数的第一组软比特。第二模块被配置为使用第一组软比特来执行操作，以产生具有小于第一比特数的第二比特数的第二组软比特。在说明性实现中，第二组软比特与三级解码过程结合使用，以对表示数据的一组硬比特进行解码。

10. 发明申请

WO2016209639A1 MEMORY HEALTH MONITORING 审中-公开
标题翻译：记忆健康监测
公开(公告)号：WO2016209639A1
公开(公告)日：2016-12-29
申请号：PCT/US2016/036847
申请日：2016-06-10
申请人： SANDISK TECHNOLOGIES LLC
发明人： YANG, Nian Niles , ALROD, Idan
IPC分类号： G11C7/10 , G11C16/34
CPC分类号： G06F3/0653 , G06F3/0616 , G06F3/0679 , G11C7/1006 , G11C16/3495 , G11C2211/5647
摘要： A data storage device may be configured to write first data to a first set of storage elements of a non-volatile memory and to write second data to a second set of storage elements of the non-volatile memory. The first data may be processed by a data shaping operation, and the second data may not be processed by the data shaping operation. The data storage device may be further configured to read a representation of the second data from the second set of storage cells and to determine a block health metric of a portion of the non-volatile memory based on the representation of the second data. The portion may include the first set of storage elements and the second set of storage elements. As an illustrative, non-limiting example, the first portion may be a first block of the non-volatile memory.
摘要翻译：数据存储设备可以被配置为将第一数据写入非易失性存储器的第一组存储元件，并将第二数据写入非易失性存储器的第二组存储元件。可以通过数据整形操作来处理第一数据，并且可以不通过数据整形操作来处理第二数据。数据存储设备还可以被配置为从第二组存储单元读取第二数据的表示，并且基于第二数据的表示来确定非易失性存储器的一部分的块健康度量。该部分可以包括第一组存储元件和第二组存储元件。作为说明性的非限制性示例，第一部分可以是非易失性存储器的第一块。

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