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1. 发明申请

WO2013016401A1 SIMULTANEOUS SENSING OF MULTIPLE WORDLINES AND DETECTION OF NAND FAILURES 审中-公开
标题翻译：多字词的同时感知与NAND故障检测
公开(公告)号：WO2013016401A1
公开(公告)日：2013-01-31
申请号：PCT/US2012/048094
申请日：2012-07-25
申请人： SANDISK TECHNOLOGIES INC. , SHARON, Eran , LI, Yan , LEE, Dana , ALROD, Idan
发明人： SHARON, Eran , LI, Yan , LEE, Dana , ALROD, Idan
IPC分类号： G11C11/56 , G11C16/34
CPC分类号： G11C29/04 , G11C11/5642 , G11C16/3459 , G11C29/50004 , G11C2211/5641
摘要： Techniques for a post-write read are presented. In an exemplary embodiment, a combined simultaneous sensing of multiple word lines is used in order to identify a problem in one or more of these word lines. That is, sensing voltages are concurrently applied to the control gates of more than one memory cell whose resultant conductance is measured on the same bit line. The combined sensing result is use for measuring certain statistics of the cell voltage distribution (CVD) of multiple word lines and comparing it to the expected value. In case the measured statistics are different than expected, this may indicate that one or more of the sensed word lines may exhibit a failure and more thorough examination of the group of word lines can be performed.
摘要翻译：介绍了写后读取的技巧。在示例性实施例中，使用多个字线的组合同时感测以便识别这些字线中的一个或多个中的问题。也就是说，感测电压被同时施加到多于一个存储单元的控制栅极，其存储电导在相同的位线上被测量。组合的传感结果用于测量多条字线的单元电压分布（CVD）的某些统计数据并将其与期望值进行比较。如果测量的统计数据与预期不同，则这可能表明一个或多个感测到的字线可能表现出故障，并且可以对该组字线进行更彻底的检查。

2. 发明申请

WO2014039459A1 NON-VOLATILE STORAGE WITH JOINT HARD BIT AND SOFT BIT READING 审中-公开
标题翻译：非挥发性储存与联合硬头和软位阅读
公开(公告)号：WO2014039459A1
公开(公告)日：2014-03-13
申请号：PCT/US2013/057894
申请日：2013-09-03
申请人： SANDISK TECHNOLOGIES, INC. , SHARON, Eran , ALROD, Idan , LI, Yan , KOH, Yee, Lih , KUO, Tien-chien
发明人： SHARON, Eran , ALROD, Idan , LI, Yan , KOH, Yee, Lih , KUO, Tien-chien
IPC分类号： G11C11/56 , G06F11/10
CPC分类号： G11C16/26 , G06F11/1012 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C2211/5624 , G11C2211/5631 , G11C2211/5632
摘要： A system is disclosed for reading hard bit information (650, 654) and soft bit information (670, 672, 674, 676) from non-volatile storage. Some of the hard bit information and/or soft bit information is read concurrently by using different bit line voltages, different integration times, different sense levels within the sense amplifiers, or other techniques. A method is disclosed for determining the hard bits and soft bits in real time based on sensed hard bit information and soft bit information.
摘要翻译：公开了一种用于从非易失性存储器读取硬比特信息（650,654）和软比特信息（670,672,674,676）的系统。一些硬比特信息和/或软比特信息通过使用不同的位线电压，不同的积分时间，读出放大器内的不同感测电平或其他技术同时读取。公开了一种基于感测的硬比特信息和软比特信息来实时确定硬比特和软比特的方法。

3. 发明申请

WO2013016393A1 DATA RECOVERY FOR DEFECTIVE WORD LINES DURING PROGRAMMING OF NON-VOLATILE MEMORY ARRAYS 审中-公开
标题翻译：在非易失性存储器阵列的编程过程中，针对有缺陷的字线的数据恢复
公开(公告)号：WO2013016393A1
公开(公告)日：2013-01-31
申请号：PCT/US2012/048080
申请日：2012-07-25
申请人： SANDISK TECHNOLOGIES INC. , SHARON, Eran , ALROD, Idan
发明人： SHARON, Eran , ALROD, Idan
IPC分类号： G06F11/10
CPC分类号： G11C29/04 , G06F11/1048 , G06F11/1072 , G11C29/82
摘要： The recovery of data during programming, such as in the case of a broken word-line, is considered. The arrangement described assumes that k pages may be corrupted when the system finishes programming a block. Then these corrupted pages can be recovered using an erasure code. In order to recover any k pages, the system will compute and temporarily store k parity pages in the controller. These k parity pages may be computed on-the-fly as the data pages are received from the host. Once programming of the block is finished, a post-write read may be done in order to validate that the data is stored reliably. If no problem is detected during EPWR, then the parity pages in the controller may be discarded. In case a problem is detected, and data in up to k pages is corrupt on some bad word-lines, then the missing data is recovered using the k parity pages that are stored in the controller and using the other non-corrupted pages that are read from the block of the memory array and decoded. Once the recovery is complete the block can be reprogrammed and the temporary parity pages in the controller may be discarded upon successfully reprogramming.
摘要翻译：考虑在编程期间恢复数据，例如在字线断开的情况下。所描述的布置假设当系统完成对块的编程时，k页可能被破坏。然后可以使用擦除代码恢复这些损坏的页面。为了恢复任何k页，系统将在控制器中计算和临时存储k个奇偶校验页面。当从主机接收到数据页时，这些k个奇偶校验页可以在运行中计算。一旦块的编程完成，可以进行写入后读取，以便验证数据是否被可靠地存储。如果在EPWR期间没有检测到问题，则可能会丢弃控制器中的奇偶校验页。如果检测到问题，并且在一些不良字线上，最多k页的数据已损坏，则使用存储在控制器中的k个奇偶校验页和使用其他未损坏的页面来恢复丢失的数据从存储器阵列中读取并解码。恢复完成后，可以重新编程块，并且在成功重新编程后，可能会丢弃控制器中的临时奇偶校验页。

4. 发明申请

WO2013032892A1 SYSTEM AND METHOD OF COPYING DATA 审中-公开
标题翻译：复制数据的系统和方法
公开(公告)号：WO2013032892A1
公开(公告)日：2013-03-07
申请号：PCT/US2012/052231
申请日：2012-08-24
申请人： SANDISK TECHNOLOGIES INC. , SHARON, Eran , ALROD, Idan
发明人： SHARON, Eran , ALROD, Idan
IPC分类号： G06F11/10
CPC分类号： G06F11/1068 , G11C29/52
摘要： A method of copying data includes receiving a command instructing copying of data from a source location in the memory die to a destination location in the memory die. The method includes determining if a criterion is met, including comparing a predefined parameter to a dynamic threshold. In response to determining that the criterion is met, the method includes executing the copying by moving the data from the source location in the memory die to the controller die and, after moving the data to the controller die, moving an error-corrected version of the data from the controller die to the destination location in the memory die. In response to determining that the criterion is not met, the method includes executing the copying by moving the data inside the memory die source location to the destination location without moving the data to the controller die.
摘要翻译：复制数据的方法包括：接收指令从存储器管芯中的源位置复制数据到存储管芯中的目标位置的命令。该方法包括确定是否满足标准，包括将预定义参数与动态阈值进行比较。响应于确定满足标准，该方法包括通过将数据从存储器管芯中的源位置移动到控制器管芯来执行复制，并且在将数据移动到控制器管芯之后，移动错误校正版本来自控制器的数据死亡到存储器管芯中的目的位置。响应于确定不符合标准，该方法包括通过将存储器管芯源位置内的数据移动到目标位置来执行复制，而不将数据移动到控制器管芯。

5. 发明申请

WO2013018080A1 ERROR-CORRECTION DECODING WITH REDUCED MEMORY AND POWER REQUIREMENTS 审中-公开
标题翻译：具有减少内存和电源要求的错误修正解码
公开(公告)号：WO2013018080A1
公开(公告)日：2013-02-07
申请号：PCT/IL2011/000617
申请日：2011-07-31
申请人： SANDISK TECHNOLOGIES, INC., A TEXAS CORPORATION , SHARON, Eran , ALROD, Idan , FAINZILBER, Omer , LITSYN, Simon
发明人： SHARON, Eran , ALROD, Idan , FAINZILBER, Omer , LITSYN, Simon
IPC分类号： H03M13/00
CPC分类号： H03M13/1105 , H03M13/1117 , H03M13/3715 , H03M13/6502
摘要： An example method is provided that includes receiving a representation of a codeword that includes a plurality of bits, and associating the bits with a respective plurality of one-bit hard-bit values representing the bits and multiple-bit soft-bit values representing measures of reliability of respective hard-bit values. The method includes for each of a plurality of iterations, updating a hard-bit/soft-bit value of one or more bits of a respective subset of the bits as a function of current hard-bit values of the subset's bits, and the current hard-bit and soft-bit values of the respective bit. For two iterations in which the current hard-bit and soft-bit values for each bit of a subset for both iterations is the same, the hard-bit/soft-bit value updated for any bit of the subset during one of the two iterations is the same as that computed for the respective bit during the other of the two iterations.
摘要翻译：提供了一种示例性方法，其包括接收包括多个比特的码字的表示，并且将比特与表示比特的相应多个一比特硬比特值和表示多个比特的度量的多比特软比特值相关联各个硬比特值的可靠性。该方法包括用于多个迭代中的每一个，作为该子集的比特的当前硬比特值的函数来更新比特的相应子集的一个或多个比特的硬比特/软比特值，以及当前相应位的硬比特和软比特值。对于两次迭代，其中对于两次迭代的子集的每个位的当前硬比特和软比特值是相同的，则在两次迭代之一期间为子集的任何比特更新的硬比特/软比特值与在两次迭代中的另一个中相应位计算的相同。

6. 发明申请

WO2013019560A2 CHECKSUM USING SUMS OF PERMUTATION SUB-MATRICES 审中-公开
标题翻译：校验和使用排序子矩阵
公开(公告)号：WO2013019560A2
公开(公告)日：2013-02-07
申请号：PCT/US2012/048364
申请日：2012-07-26
申请人： SANDISK TECHNOLOGIES INC. , SHARON, Eran , ALROD, Idan
发明人： SHARON, Eran , ALROD, Idan
IPC分类号： H03M13/09 , H03M13/05 , G06F11/10
CPC分类号： H03M13/09 , G06F11/1012 , H03M13/1128 , H03M13/116 , H03M13/2906 , H03M13/2927
摘要： A method for encoding data bits includes computing checksum parity bits based on the data bits. A set of equations satisfied by the data bits and the checksum parity bits corresponds to a dense parity-check matrix. The dense parity-check matrix comprises sums of permutation sub-matrices.
摘要翻译：用于编码数据比特的方法包括基于数据比特计算校验和奇偶校验比特。数据位和校验和奇偶校验位满足的一组等式对应于密集奇偶校验矩阵。密集奇偶校验矩阵包含置换子矩阵的和。

7. 发明申请

WO2013016397A2 POST-WRITE READ IN NON-VOLATILE MEMORIES USING COMPARISON OF DATA AS WRITTEN IN BINARY AND MULTI-STATE FORMATS 审中-公开
标题翻译：在非易失性存储器中使用双向和多态格式中的数据进行比较读写
公开(公告)号：WO2013016397A2
公开(公告)日：2013-01-31
申请号：PCT/US2012/048087
申请日：2012-07-25
申请人： SANDISK TECHNOLOGIES INC. , SHARON, Eran , ALROD, Idan
发明人： SHARON, Eran , ALROD, Idan
IPC分类号： G11C16/34 , G11C11/56 , G06F11/10
CPC分类号： G11C16/3459 , G06F11/1072 , G11C11/5628 , G11C16/3481 , G11C2211/5641
摘要： Techniques for a post-write read are presented. In an exemplary embodiment, host data is initially written into the non-volatile memory in binary form, such as a non-volatile binary cache. It is then subsequently written from the binary section into a multi-state non-volatile section of the memory. After being written in multi-state format, pages of data from a multi-state block can then be checked against there source pages in the binary section to verify the quality of the multi-state write. This process can be performed on the memory device itself, without transferring the pages out to the controller.
摘要翻译：介绍了写入后读取技术。在示例性实施例中，主数据最初以二进制形式写入非易失性存储器，例如非易失性二进制高速缓存。随后将其从二进制部分写入存储器的多状态非易失性部分。在以多状态格式写入后，可以在二进制部分的源页面中检查来自多状态块的数据页面，以验证多状态写入的质量。该过程可以在存储器设备本身上执行，而不将页面传送到控制器。

8. 发明申请

WO2013016168A2 SYSTEMS AND METHODS OF STORING DATA 审中-公开
标题翻译：存储数据的系统和方法
公开(公告)号：WO2013016168A2
公开(公告)日：2013-01-31
申请号：PCT/US2012/047545
申请日：2012-07-20
申请人： SANDISK TECHNOLOGIES INC. , SHARON, Eran , ALROD, Idan , LITSYN, Simon , LASSER, Menahem
发明人： SHARON, Eran , ALROD, Idan , LITSYN, Simon , LASSER, Menahem
IPC分类号： G06F11/10
CPC分类号： G11C7/1006 , G06F11/1044 , G06F11/1068 , G06F11/1072 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C29/78 , G11C2211/5641
摘要： Systems and methods of storing data are disclosed.
摘要翻译：公开了存储数据的系统和方法。

9. 发明申请

WO2011080564A1 FLASH MEMORY SYSTEM HAVING CROSS-COUPLING COMPENSATION DURING READ OPERATION 审中-公开
标题翻译：在读取操作期间具有交叉耦合补偿的闪存存储器系统
公开(公告)号：WO2011080564A1
公开(公告)日：2011-07-07
申请号：PCT/IB2010/003338
申请日：2010-12-21
申请人： SANDISK IL LTD. , SHARON, Eran , ALROD, Idan
发明人： SHARON, Eran , ALROD, Idan
IPC分类号： G11C11/56 , G11C16/26
CPC分类号： G11C11/5642 , G11C16/26 , G11C16/3422
摘要： A method for reading an addressed cell of a memory system comprises applying at least two different voltage levels to a control gate of a memory cell in an array of memory cells, wherein the memory cell is adjacent to and in electrical field communication with the addressed memory cell. A threshold voltage of the addressed memory cell is measured at each of the at least two different applied voltage levels. At least two of the measured threshold voltages of the addressed memory cell are converted to one or more bit values stored in the addressed memory cell. The bit values are provided to a host of the memory system. An apparatus implementing the method is also disclosed.
摘要翻译：一种用于读取存储器系统的寻址单元的方法包括将至少两个不同的电压电平施加到存储器单元阵列中的存储器单元的控制栅极，其中存储器单元与寻址存储器相邻并且与电场通信细胞。在所述至少两个不同的施加电压电平中的每一个处测量寻址的存储器单元的阈值电压。所寻址的存储器单元的测量阈值电压中的至少两个被转换为存储在所寻址的存储单元中的一个或多个位值。位值被提供给存储器系统的主机。还公开了一种实现该方法的装置。

10. 发明申请

WO2011073710A1 AUXILIARY PARITY BITS FOR DATA WRITTEN IN MULTI-LEVEL CELLS 审中-公开
标题翻译：用于在多级电池中写入数据的辅助奇偶校验位
公开(公告)号：WO2011073710A1
公开(公告)日：2011-06-23
申请号：PCT/IB2009/007789
申请日：2009-12-16
申请人： SANDISK IL LTD , SHARON, Eran , ALROD, Idan
发明人： SHARON, Eran , ALROD, Idan
IPC分类号： G06F11/10
CPC分类号： G06F11/1048 , G06F11/1072
摘要： Methods of writing data to and reading data from memory devices and systems for writing and reading data are disclosed. In a particular embodiment, a method includes writing data bits a first time into a memory. Auxiliary parity bits are written in the memory, where the auxiliary parity bits are computed based on the data bits. Subsequent to writing the data bits a first time and writing the auxiliary parity bits, the data bits are written a second time into the memory. Writing the data bits the first time and writing the data bits the second time are directed to one or more storage elements at a common physical address in the memory. Subsequent to writing the data bits the second time, the auxiliary parity bits are discarded while maintaining the data bits in the memory.
摘要翻译：公开了将数据写入和读取数据的方法，用于从存储器件和系统读取和读取数据。在特定实施例中，一种方法包括将数据位第一次写入存储器。辅助奇偶校验位写入存储器中，其中辅助奇偶校验位基于数据位计算。在第一次写入数据位并写入辅助奇偶校验位之后，将数据位第二次写入存储器。第一次写入数据位并且第二次写入数据位将被引导到存储器中公共物理地址的一个或多个存储元件。在第二次写数据位之后，辅助奇偶校验位被丢弃，同时保持存储器中的数据位。

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