专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2011056482A1 NON-VOLATILE MEMORY AND METHOD WITH POST-WRITE READ AND ADAPTIVE RE-WRITE TO MANAGE ERRORS 审中-公开
标题翻译：非易失性存储器和具有后置读取和自适应再写入管理错误的方法
公开(公告)号：WO2011056482A1
公开(公告)日：2011-05-12
申请号：PCT/US2010/053805
申请日：2010-10-22
申请人： SANDISK CORPORATION , DUSIJA, Gautam Ashok , CHEN, Jian , AVILA, Chris , HUANG, Jianmin , GAVENS, Lee M.
发明人： DUSIJA, Gautam Ashok , CHEN, Jian , AVILA, Chris , HUANG, Jianmin , GAVENS, Lee M.
IPC分类号： G11C11/56 , G11C16/10 , G11C16/34
CPC分类号： G11C11/5621 , G11C16/10 , G11C16/349 , G11C16/3495 , G11C29/00 , G11C2211/5641
摘要： Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. Input data is written and staged in the first portion before being copied to the second portion. An error management provides checking the quality of the copied data for excessive error bits. The copying and checking are repeated on a different location in the second portion until either a predetermined quality is satisfied or the number or repeats exceeds a predetermined limit. The error management is not started when a memory is new with little or no errors, but started after the memory has aged to a predetermined amount as determined by the number of erase/program cycling its has experienced.
摘要翻译：非易失性存储器中的数据错误不可避免地随着使用而增加，并且每个单元存储更高密度的位。存储器被配置为具有以较小误差但是较低密度存储器操作的第一部分，以及以较高密度但较不牢固的存储器操作的第二部分。在将第一部分复制到第二部分之前，输入数据被写入并分级。错误管理提供检查复制数据的质量是否存在过多的错误位。在第二部分中的不同位置重复复印和检查，直到满足预定质量或者数量或重复超过预定限度。当存储器是新的，几乎没有或没有错误时，错误管理不开始，但是在内存已经老化到由其经历的擦除/程序循环的数量确定的预定量之后开始。

2. 发明申请

WO2011056483A1 NON-VOLATILE MEMORY AND METHOD WITH ACCELERATED POST-WRITE READ TO MANAGE ERRORS 审中-公开
标题翻译：非易失性存储器和加速后置写入的方法读取管理错误
公开(公告)号：WO2011056483A1
公开(公告)日：2011-05-12
申请号：PCT/US2010/053813
申请日：2010-10-22
申请人： SANDISK CORPORATION , CHEN, Jian , GAVENS, Lee M.
发明人： CHEN, Jian , GAVENS, Lee M.
IPC分类号： G11C11/56 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/3418 , G11C16/3454 , G11C29/00 , G11C2211/5621 , G11C2211/5641
摘要： Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. An error management provides reading and checking the copy after copying to the second portion. If the copy has excessive error bits, it is repeated in a different location either in the second or first portion. The reading and checking of the copy is accelerated by reading only a sample of it. The sample is selected from a subset of the copy having its own ECC and estimated to represent a worst error rate among the copy it is sampling. One embodiment has the sample taken from one bit of each multi-bit memory cell of a group.
摘要翻译：非易失性存储器中的数据错误不可避免地随着使用而增加，并且每个单元存储更高密度的位。存储器被配置为具有以较小误差但是较低密度存储器操作的第一部分，以及以较高密度但较不牢固的存储器操作的第二部分。错误管理在复制到第二部分后提供读取和检查副本。如果副本具有过多的错误位，则在第二或第一部分的不同位置重复该复制。通过只读取样本来读取和检查副本。从具有其自己的ECC的副本的子集中选择该样本，并且估计该样本表示其正在采样的副本中的最差错误率。一个实施例具有取自组中的每个多位存储器单元的一位的样本。

3. 发明申请

WO2008157084A1 PROGRAMMABLE CHIP ENABLE AND CHIP ADDRESS IN SEMICONDUCTOR MEMORY 审中-公开
标题翻译：半导体存储器中的可编程芯片使能和芯片地址
公开(公告)号：WO2008157084A1
公开(公告)日：2008-12-24
申请号：PCT/US2008/066111
申请日：2008-06-06
申请人： SANDISK CORPORATION , TU, Loc , CHEN, Jian , MAK, Alex , KUO, Tien-chien , LONG, Pham
发明人： TU, Loc , CHEN, Jian , MAK, Alex , KUO, Tien-chien , LONG, Pham
IPC分类号： G11C16/34 , G11C16/10 , G11C16/08
CPC分类号： G11C29/88 , G11C5/04 , G11C16/04 , G11C29/76 , G11C29/886
摘要： Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be re-addressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.
摘要翻译：存储器管芯具有可编程芯片使能电路，以允许在封装和/或可编程芯片地址电路之后禁止特定存储器管芯，以允许特定存储器管芯在封装之后被读取。在多芯片存储器封装中，可以通过可覆盖从控制器或主机设备接收的主芯片使能信号的可编程电路来禁止与存储器封装隔离的封装级测试失败的存储器管芯。为了提供连续的地址范围，可以使用替代由焊盘键合提供的唯一芯片地址的另一个可编程电路来重新寻址无缺陷存储器管芯中的一个或多个。封装后的存储器芯片也可以被独立于检测出错的存储器芯片而被读取。

4. 发明申请

WO2007079062A1 CONTINUED VERIFICATION IN NON-VOLATILE MEMORY WRITE OPERATIONS 审中-公开
标题翻译：在非易失性存储器写操作中继续验证
公开(公告)号：WO2007079062A1
公开(公告)日：2007-07-12
申请号：PCT/US2006/049220
申请日：2006-12-27
申请人： SANDISK CORPORATION , CHEN, Jian
发明人： CHEN, Jian
IPC分类号： G11C16/34
CPC分类号： G11C16/3468 , G11C16/3486
摘要： Temporary lock-out is provided while programming a group of non¬ volatile memory cells to more accurately program the memory cells. After successfully verifying that the threshold voltage of a memory cell has reached the level for its intended state, it is possible that the threshold voltage will subsequently decrease to below the verify level during additional iterations of the programming process needed to complete programming of other memory cells of the group. Memory cells are monitored (e.g., after each iteration) to determine if they fall below the verify level after previously verifying that the target threshold voltage has been reached. Cells that pass verification and then subsequently fail verification can be subjected to further programming. For example, the bit line voltage for the memory cell of interest may be set to a moderately high voltage to slow down or reduce the amount of programming accomplished by each subsequent programming pulse. In this manner, a memory cell that falls out of verification can be placed back in the normal programming flow without risking over-programming of the cell.
摘要翻译：在编写一组非易失性存储单元以更准确地对存储单元进行编程时，提供临时锁定。在成功验证存储器单元的阈值电压已经达到其预期状态的电平之后，有可能阈值电压随后在完成编程其它存储器单元所需的编程过程的附加迭代期间降低到低于验证电平的组合。监视存储器单元（例如，在每次迭代之后），以确定在先前验证是否已达到目标阈值电压之后它们是否落在验证电平以下。通过验证然后随后验证失败的单元可以进行进一步的编程。例如，感兴趣的存储单元的位线电压可以被设置为适度的高电压以减慢或减少由每个随后的编程脉冲实现的编程量。以这种方式，退出验证的存储单元可以放回到正常编程流程中，而不会对单元进行过度编程的风险。

5. 发明申请

WO2005119696A1 ERASE VERIFICATION FOR NON-VOLATILE MEMORY BY TESTING THE CONDUCTION OF THE MEMORY ELEMENTS IN A FIRST AND A SECOND DIRECTION 审中-公开
标题翻译：通过测试第一和第二方向的记忆元素的导致来对非易失性存储器进行擦除验证
公开(公告)号：WO2005119696A1
公开(公告)日：2005-12-15
申请号：PCT/US2005/017862
申请日：2005-05-20
申请人： SANDISK CORPORATION , TRAN, Dat , PONNURU, Kiran , CHEN, Jian , LUTZE, Jeffrey, W. , WANG, Jun
发明人： TRAN, Dat , PONNURU, Kiran , CHEN, Jian , LUTZE, Jeffrey, W. , WANG, Jun
IPC分类号： G11C16/34
CPC分类号： G11C16/3468
摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a first (380) and a second (382) direction, defects in any transistors of the Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements in verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.
摘要翻译：根据各种实施例的系统和方法可以提供非易失性半导体存储器中的全面擦除验证和缺陷检测。在一个实施例中，使用多个测试条件来验证擦除一组存储元件的结果，以更好地检测组中的有缺陷和/或不充分擦除的存储元件。例如，擦除NAND串的结果可以通过在多个方向上测试字符串的充电来验证，其中存储元件被偏置为在擦除状态下导通。如果一串存储元件通过第一个测试过程或操作，但是失败了第二个测试过程或操作，则可以确定该字符串已经失效了擦除过程并且可能是有缺陷的。通过测试第一（380）和第二（382）方向的串的充电或导通，根据各种实施例的系统和方法的任何晶体管中的缺陷可以提供非易失性半导体中的全面擦除验证和缺陷检测记忆。在一个实施例中，擦除使用多个测试条件验证的一组存储元件的结果，以更好地检测该组的有缺陷和/或不充分擦除的存储元件。例如，擦除NAND串的结果可以通过在多个方向上测试字符串的充电来验证，其中存储元件被偏置为在擦除状态下导通。如果一串存储元件通过第一个测试过程或操作，但是失败了第二个测试过程或操作，则可以确定该字符串已经失效了擦除过程并且可能是有缺陷的。通过在多个方向上测试串的充电或导通，在一组条件下被屏蔽的串的任何晶体管中的缺陷可能在第二组偏置条件下暴露。例如，字符串可以传递擦除验证操作，然后被读取为包括一个或多个编程的存储元件。这样的字符串可能是有缺陷的，并被映射出存储器件。

6. 发明申请

WO2005101424A1 VARIABLE PROGRAMMING OF NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器的可变编程
公开(公告)号：WO2005101424A1
公开(公告)日：2005-10-27
申请号：PCT/US2005/010006
申请日：2005-03-23
申请人： SANDISK CORPORATION , CHEN, Jian , WANG, Chi-Ming
发明人： CHEN, Jian , WANG, Chi-Ming
IPC分类号： G11C16/34
CPC分类号： G11C16/3459 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C16/3454 , G11C2211/5621
摘要： Systems and methods in accordance with various embodiments can provide for reduced program disturb in non-volatile semiconductor memory. In one embodiment, select memory cells such as those connected to a last word line of a NAND string are programmed using one or more program verify levels or voltages that are different than a corresponding level used to program other cells or word lines. One exemplary embodiment includes using a lower threshold voltage verify level for select physical states when programming the last word line to be programmed for a string during a program operation. Another embodiment includes applying a lower program voltage to program memory cells of the last word line to select physical states. Additional read levels are established for reading the states programmed using lower verify levels in some exemplary implementations. A second program voltage step size that is larger than a nominal step size is used in one embodiment when programming select memory cells or word lines, such as the last word line to be programmed for a NAND string.
摘要翻译：根据各种实施例的系统和方法可以提供非易失性半导体存储器中减少的程序干扰。在一个实施例中，使用与编程其他单元或字线的相应级别不同的一个或多个程序验证电平或电压对连接到NAND串的最后字线的选择存储器单元进行编程。一个示例性实施例包括在编程在程序操作期间编程用于字符串的最后一个字线时，使用较低的阈值电压验证电平进行选择的物理状态。另一个实施例包括将较低编程电压施加到最后字线的编程存储单元以选择物理状态。在一些示例性实施方式中，建立读取使用较低验证电平编程的状态的附加读取电平。在一个实施例中，当编程选择存储器单元或字线（诸如要为NAND串编程的最后字线）时，使用大于标称步长的第二编程电压步长。

7. 发明申请

WO2011087602A1 SYSTEM AND METHOD OF ERROR CORRECTION OF CONTROL DATA AT A MEMORY DEVICE 审中-公开
标题翻译：在存储器件中控制数据的错误校正的系统和方法
公开(公告)号：WO2011087602A1
公开(公告)日：2011-07-21
申请号：PCT/US2010/058591
申请日：2010-12-01
申请人： SANDISK CORPORATION , YURZOLA, Damian Pablo , NAGABHIRAVA, Rajeev , KAPOOR, Arjun , DROR, Itai , CHANG, Annie Chi-San , HWANG, Peter , CHEN, Jian
发明人： YURZOLA, Damian Pablo , NAGABHIRAVA, Rajeev , KAPOOR, Arjun , DROR, Itai , CHANG, Annie Chi-San , HWANG, Peter , CHEN, Jian
IPC分类号： G06F11/10
CPC分类号： H03M7/30 , G06F11/1048 , G06F12/0246 , G06F2212/401 , G06F2212/403 , H03M13/35 , H03M13/6312
摘要： A controller coupled to a memory array includes an error correction coding (ECC) engine and an ECC enhancement compression module coupled to the ECC engine. The ECC enhancement compression module is configured to receive and compress control data to be provided to the ECC engine to be encoded. Compressed encoded control data generated at the ECC engine is stored as a codeword at the memory array.
摘要翻译：耦合到存储器阵列的控制器包括耦合到ECC引擎的纠错编码（ECC）引擎和ECC增强压缩模块。 ECC增强压缩模块被配置为接收和压缩要提供给要编码的ECC引擎的控制数据。在ECC引擎处生成的压缩编码控制数据作为码字存储在存储器阵列中。

8. 发明申请

WO2008083162A1 RETENTION MARGIN PROGRAM VERIFICATION 审中-公开
标题翻译：保留MARGIN程序验证
公开(公告)号：WO2008083162A1
公开(公告)日：2008-07-10
申请号：PCT/US2007/088831
申请日：2007-12-26
申请人： SANDISK CORPORATION , WAN, Jun , LUTZE, Jeffrey, W. , CHEN, Jian , LI, Yan , MAK, Alex
发明人： WAN, Jun , LUTZE, Jeffrey, W. , CHEN, Jian , LI, Yan , MAK, Alex
IPC分类号： G11C11/56 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3436 , G11C2211/5621
摘要： A memory system, comprising an array of storage elements divided into logical blocks and pages within said logical blocks and a managing circuit is provided. The managing circuit is in communication with said array of storage elements and performs programming and reading operations. The programming operations include programming a plurality of multi-state storage data. The reading operations include defining an retention margin between adjacent data thresholds, determining whether bits are present in a portion of the data retention margin, and if the number of bits in the portion of retention margin exceeds a threshold, generating an error.
摘要翻译：一种存储器系统，包括被划分成逻辑块的存储元件阵列和所述逻辑块内的页面，以及管理电路。管理电路与所述存储元件阵列通信并执行编程和读取操作。编程操作包括编程多个多状态存储数据。读取操作包括定义相邻数据阈值之间的保留余量，确定位是否存在于数据保留余量的一部分中，以及如果保留余量部分中的位数超过阈值，则产生错误。

9. 发明申请

WO2007058846A1 REVERSE COUPLING EFFECT WITH TIMING INFORMATION 审中-公开
标题翻译：具有时序信息的反向耦合效应
公开(公告)号：WO2007058846A1
公开(公告)日：2007-05-24
申请号：PCT/US2006/043483
申请日：2006-11-08
申请人： SANDISK CORPORATION , CHEN, Jian
发明人： CHEN, Jian
IPC分类号： G11C16/26
CPC分类号： G11C11/5642 , G11C11/5628 , G11C16/0483 , G11C16/12 , G11C16/26 , G11C16/3418
摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in neighboring floating gates (or other neighboring charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of a neighbor memory cell if the neighbor memory cell was programmed subsequent to the given memory cell. Techniques for determining whether the neighbor memory cell was programmed before or after the given memory cell are disclosed.
摘要翻译：存在于非易失性存储单元的浮动栅极（或其它电荷存储元件）上的表观电荷的变化可能发生，因为基于存储在相邻浮动栅极（或其它相邻电荷存储元件）中的电荷的电场的耦合）。在不同时间编程的相邻存储器单元组之间最明显地出现该问题。为了补偿该耦合，如果相邻存储器单元在给定存储器单元之后被编程，则给定存储器单元的读取过程将考虑相邻存储器单元的编程状态。公开了用于确定相邻存储器单元是否在给定存储器单元之前或之后被编程的技术。

10. 发明申请

WO2006078460A2 DELIVERY OF A MESSAGE TO A USER OF A PORTABLE DATA STORAGE DEVICE AS A CONDITION OF ITS USE 审中-公开
标题翻译：向便携式数据存储设备的用户传递消息作为其使用条件
公开(公告)号：WO2006078460A2
公开(公告)日：2006-07-27
申请号：PCT/US2006/000327
申请日：2006-01-05
申请人： SANDISK CORPORATION , CHEN, Jian , GONZALEZ, Carlos J. , GUTERMAN, Daniel C.
发明人： CHEN, Jian , GONZALEZ, Carlos J. , GUTERMAN, Daniel C.
IPC分类号： G06F21/00
CPC分类号： G06F12/1433 , G06F21/78 , G06F21/79 , G06F2221/2141 , G06Q30/0207 , G06Q30/0277
摘要： A memory card, flash memory drive or other removable re-programmable non-volatile memory device is configured so that at least part of the memory is not available for storage of user data until data of a message stored in the memory is at least read out by the user through a host device to which the memory device is connected. The message may be an advertisement, instructions on using the memory device, or the like, to which the user is at least exposed as a condition of having the full capacity of the memory card available thereafter for use by him or her.
摘要翻译：配置存储卡，闪速存储器驱动器或其他可移动可重新编程的非易失性存储器件，使得至少部分存储器不可用于存储用户数据，直到存储在存储器中的消息的数据至少被读出由用户通过与存储设备连接的主机设备。该消息可以是用户至少暴露于其中的广告，关于使用存储设备的指示等等，作为具有可供其使用的存储卡的全部容量的条件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式