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    • 4. 发明申请
    • IMPROVEMENTS IN A VLSI MEMORY CIRCUIT
    • VLSI存储器电路中的改进
    • WO1996005655A1
    • 1996-02-22
    • PCT/US1995010397
    • 1995-08-14
    • CREATIVE INTEGRATED SYSTEMS, INC.RICOH COMPANY, LTD.
    • CREATIVE INTEGRATED SYSTEMS, INC.RICOH COMPANY, LTD.KOMAREK, James, A.PADGETT, Clarence, W.MINNEY, Jack, L.TANNER, Scott, B.KOJIMA, Shin-ichiOISHI, MotohiroFUKUMURA, KeijiNAKANISHI, Hiroaki
    • H03K17/16
    • G11C7/1057G11C7/1051G11C7/106G11C7/12G11C7/22G11C8/06G11C8/18
    • The rate of increase or decrease of the rising and falling edge respectively of an output driver in a read-only memory circuit is provided by driving a CMOS output amplifier by gate control signals whose rate of increase or decrease in turn is controlled by a control signal, SLOW. The signal SLOW is generated based upon the speed of operation of the ROM and is binary, one state being indicative of normal speed of operation and a second state being indicative of a slow speed of operation of the ROM. When the signal SLOW is high, the rate at which complementary gate drive signals are applied to the CMOS amplifier are generated at a first or normal rate. However, when the signal SLOW is low, the rate of generation of these gate drive signals is also decreased to correspondingly decrease the switching speed of the CMOS amplifier. A voltage precharge signal VPC is also applied to the rate controlling circuit so that variations in the precharge voltage indicative of manufacturing parameters, voltage variations and temperature variations directly effect the rate at which the gate drive signals are generated and hence the switching speeds of the CMOS amplifier.
    • 只读存储器电路中的输出驱动器的上升沿和下降沿的增加或减小的速率通过由控制信号控制的栅极控制信号驱动CMOS输出放大器来提供, , 慢。 基于ROM的操作速度产生信号SLOW,是二进制的,一个状态表示正常的操作速度,第二个状态指示ROM的低速操作。 当信号SLOW为高时,互补栅极驱动信号施加到CMOS放大器的速率以第一或正常速率产生。 然而,当信号SLOW为低电平时,这些栅极驱动信号的产生速率也降低,以相应地降低CMOS放大器的开关速度。 电压预充电信号VPC也被施加到速率控制电路,使得指示制造参数,电压变化和温度变化的预充电电压的变化直接影响产生栅极驱动信号的速率,因此CMOS的开关速度 放大器。