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1. 发明申请

WO2008070138A9 METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN TRANSCEIVER DEVICES 审中-公开
标题翻译：收发器设备之间信道均衡不对称分布的方法和电路
公开(公告)号：WO2008070138A9
公开(公告)日：2009-03-05
申请号：PCT/US2007024948
申请日：2007-12-05
申请人： RAMBUS INC , ZERBE JARED L , ASSADERAGHI FARIBORZ , LEIBOWITZ BRIAN S , LEE HAE-CHANG , REN JIHONG , LIN QI
发明人： ZERBE JARED L , ASSADERAGHI FARIBORZ , LEIBOWITZ BRIAN S , LEE HAE-CHANG , REN JIHONG , LIN QI
IPC分类号： H04L25/03
CPC分类号： H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
摘要： A transceiver architecture supports high-speed communication over a signal lane (120-125) that extends between a high-performance integrated circuit (IC) (105) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers (110). The. architecture compensates for performance asymmetry between ICs communicating over a bidirectional lan by instantiating relatively complex transmit (Tx1) and receive (Rx1) equalization cir.cuitry on the higher-performance, side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated (162) based upon the signal response at the receiver of the higher-performance IC (Rx1N).
摘要翻译：收发机体系结构支持在高性能集成电路（IC）（105）和采用较不复杂的发射机和接收机（110）的一个或多个相对低性能的IC之间延伸的信号通道（120-125）上的高速通信。。的。通过在更高性能的通道侧实例化相对复杂的发送（Tx1）和接收（Rx1）均衡电路，体系结构补偿了通过双向lan进行通信的IC之间的性能不对称。基于在更高性能IC（Rx1N）的接收机处的信号响应，高性能IC中的发射和接收均衡滤波器系数都可以自适应地更新（162）。

2. 发明申请

WO2008070138A3 METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN TRANSCEIVER DEVICES 审中-公开
标题翻译：收发器之间通道均衡化的不对称分配方法与电路
公开(公告)号：WO2008070138A3
公开(公告)日：2009-01-15
申请号：PCT/US2007024948
申请日：2007-12-05
申请人： RAMBUS INC , ZERBE JARED L , ASSADERAGHI FARIBORZ , LEIBOWITZ BRIAN S , LEE HAE-CHANG , REN JIHONG , LIN QI
发明人： ZERBE JARED L , ASSADERAGHI FARIBORZ , LEIBOWITZ BRIAN S , LEE HAE-CHANG , REN JIHONG , LIN QI
IPC分类号： H04L25/03
CPC分类号： H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
摘要： A transceiver architecture supports high-speed communication over a signal lane (120-125) that extends between a high-performance integrated circuit (IC) (105) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers (110). The. architecture compensates for performance asymmetry between ICs communicating over a bidirectional lan by instantiating relatively complex transmit (Tx1) and receive (Rx1) equalization cir.cuitry on the higher-performance, side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated (162) based upon the signal response at the receiver of the higher-performance IC (Rx1N).
摘要翻译：收发器架构支持在高性能集成电路（IC）（105）和使用较不复杂的发送器和接收器（110）的一个或多个相对低性能的IC之间延伸的信号通道（120-125）上的高速通信，。的。架构通过在车道的较高性能侧实例化相对复杂的发送（Tx1）和接收（Rx1）均衡电路来补偿通过双向LAN通信的IC之间的性能不对称性。基于在高性能IC（Rx1N）的接收机处的信号响应，可以自适应地更新（162）高性能IC中的发射和接收均衡滤波器系数。

3. 发明申请

WO2009003129A3 METHODS AND CIRCUITS FOR ADAPTIVE EQUALIZATION AND CHANNEL CHARACTERIZATION USING LIVE DATA 审中-公开
标题翻译：使用实时数据的自适应均衡和通道特征的方法和电路
公开(公告)号：WO2009003129A3
公开(公告)日：2009-04-16
申请号：PCT/US2008068409
申请日：2008-06-26
申请人： RAMBUS INC , LEE HAE-CHANG , REN JIHONG , LEIBOWITZ BRIAN S , MADDEN CHRISTOPHER J , LIN QI , ZERBE JARED L
发明人： LEE HAE-CHANG , REN JIHONG , LEIBOWITZ BRIAN S , MADDEN CHRISTOPHER J , LIN QI , ZERBE JARED L
IPC分类号： H04L25/02 , H04L1/20 , H04L25/03
CPC分类号： H04L25/03878 , H04L1/203 , H04L1/205 , H04L25/0224 , H04L25/0242 , H04L25/0264 , H04L25/0272 , H04L25/03012 , H04L25/03343
摘要： A communication system supports high-speed communication over a signal lane that extends between respective transmitting and receiving integrated circuit (IC) devices. One or both of the IC devices includes an equalizer to offset channel characteristics that otherwise impair speed performance. A margining circuit on the receiving IC measures a timing margin of the received signal and adjusts the equalization settings for one or both transmitters to maximize the timing margin. Another embodiment compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex error analysis and adaptation circuitry on the higher-performance side of the lane. The error analysis and adaptation circuitry reduces the error margin of the transmitted signal to introduce bit errors at the receiver, analyzes the bit errors to measure ISI imposed by the channel, and adjusts voltage offsets of the continuous-time signal to compensate for the ISI. In some embodiments the receiver calculates the system response for diagnostics and for computing equalization settings.
摘要翻译：通信系统支持在相应的发送和接收集成电路（IC）设备之间延伸的信号通道上的高速通信。一个或两个IC器件包括均衡器以抵消否则会影响速度性能的通道特性。接收IC上的边缘电路测量接收信号的定时裕度，并调整一个或两个发射机的均衡设置以使定时裕度最大化。另一实施例通过在车道的较高性能侧实例化相对复杂的误差分析和适配电路来补偿通过双向通道通信的IC之间的性能不对称性。误差分析和自适应电路减少发射信号的误差容限，在接收机引入位错误，分析位误差以测量通道施加的ISI，并调整连续时间信号的电压补偿以补偿ISI。在一些实施例中，接收机计算用于诊断和计算均衡设置的系统响应。

4. 发明申请

WO2011062823A3 RECEIVER WITH TIME-VARYING THRESHOLD VOLTAGE 审中-公开
标题翻译：具有时变门限电压的接收器
公开(公告)号：WO2011062823A3
公开(公告)日：2011-08-18
申请号：PCT/US2010056213
申请日：2010-11-10
申请人： RAMBUS INC , ZERBE JARED L , LEIBOWITZ BRIAN S , LIN QI
发明人： ZERBE JARED L , LEIBOWITZ BRIAN S , LIN QI
IPC分类号： G11C5/14 , G11C7/10 , G11C7/22
CPC分类号： H03K3/013 , G11C7/02 , H03K5/153 , H04L25/03057 , H04L25/066 , H04L25/4902 , H04L25/4917
摘要： A system for communicating information between circuits is described. A transmit circuit provides pulse-amplitude-modulation (PAM) signals via a communication channel to a receiver. A circuit in the receiver determines digital values from the received signals using a time-varying threshold voltage, which varies during the bit-time. This approach may compensate for inter-symbol interference (ISI) to increase the voltage and timing margins of the system.
摘要翻译：描述了用于在电路之间传送信息的系统。发射电路通过通信信道向接收器提供脉冲幅度调制（PAM）信号。接收机中的电路使用时变阈值电压从接收信号中确定数字值，该阈值电压在比特时间内变化。这种方法可以补偿符号间干扰（ISI）以增加系统的电压和时间裕度。

5. 发明申请

WO2012064537A3 USING A STUTTERED CLOCK SIGNAL TO REDUCE SELF-INDUCED VOLTAGE NOISE 审中-公开
标题翻译：使用时钟信号来减少自感电压噪声
公开(公告)号：WO2012064537A3
公开(公告)日：2012-07-12
申请号：PCT/US2011058525
申请日：2011-10-31
申请人： RAMBUS INC , LEIBOWITZ BRIAN S , ZERBE JARED L
发明人： LEIBOWITZ BRIAN S , ZERBE JARED L
IPC分类号： G06F1/04 , G06F1/32 , H03K19/0175
CPC分类号： G06F1/12 , G06F1/08 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： The disclosed embodiments relate to a technique that uses a modified timing signal to reduce self-induced voltage noise in a synchronous system. During a transient period associated with a deterministic event in the synchronous system, the technique uses a modified timing signal generated based on a normal timing signal as a timing signal for the synchronous system. Outside of the transient period, the technique uses the normal timing as the timing signal for the synchronous system. In some embodiments, the modified timing signal is generated by skipping a pattern of clock transitions in the normal timing signal.
摘要翻译：所公开的实施例涉及使用修改的时序信号来减少同步系统中的自感应电压噪声的技术。在与同步系统中的确定性事件相关联的过渡时段期间，该技术使用基于正常定时信号生成的修改定时信号作为同步系统的定时信号。在瞬态时段之外，该技术使用正常时序作为同步系统的时序信号。在一些实施例中，通过跳过正常定时信号中的时钟转变的模式来生成修改的定时信号。

6. 发明申请

WO2013006231A3 LOW-LATENCY, FREQUENCY-AGILE CLOCK MULTIPLIER 审中-公开
标题翻译：低延迟，频率敏捷的时钟倍频器
公开(公告)号：WO2013006231A3
公开(公告)日：2013-04-04
申请号：PCT/US2012039268
申请日：2012-05-24
申请人： RAMBUS INC , ZERBE JARED L , LEIBOWITZ BRIAN S , HOSSAIN MASUM
发明人： ZERBE JARED L , LEIBOWITZ BRIAN S , HOSSAIN MASUM
IPC分类号： H03K5/00 , H03B19/00
CPC分类号： H03L7/16 , H03J2200/10 , H03K3/0315 , H03K5/00006 , H03K5/13 , H03K5/14 , H03L7/06 , H03L7/0995 , H03L7/24
摘要： In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally- staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
摘要翻译：在第一时钟倍频器中，并行操作具有光谱交错锁定范围的多个注入锁定振荡器（ILO），以实现比单独ILO的集中输入频率范围宽得多的集中输入频率范围。在每个输入频率改变之后，可以根据一个或多个合格标准评估ILO输出时钟，以选择ILO中的一个作为最终时钟源。在第二个时钟倍频器中，柔性注入速率注入锁定振荡器锁定超级谐波，次谐波或频率注入脉冲，在不同的注入脉冲速率之间无缝切换，以实现宽泛的输入频率范围。由第一和/或第二时钟倍频器响应于输入时钟而实现的倍频因子被实时确定，然后与编程的（期望的）倍增因子进行比较以在倍频的不同分频实例之间进行选择时钟。

7. 发明申请

WO2012021380A2 FAST-WAKE MEMORY 审中-公开
标题翻译：快速存储器
公开(公告)号：WO2012021380A2
公开(公告)日：2012-02-16
申请号：PCT/US2011046669
申请日：2011-08-04
申请人： RAMBUS INC , WARE FREDERICK A , ZERBE JARED L , LEIBOWITZ BRIAN S
发明人： WARE FREDERICK A , ZERBE JARED L , LEIBOWITZ BRIAN S
IPC分类号： G11C7/22 , G06F12/00 , G06F13/16 , G11C7/10
CPC分类号： G06F1/3275 , G06F1/324 , G06F3/0625 , G06F3/0659 , G06F3/0673 , G06F2213/0038 , G11C5/14 , G11C5/148 , G11C7/04 , G11C7/22 , G11C7/222 , G11C11/4072 , G11C11/4076 , G11C2207/2227 , G11C2207/2254
摘要： One or more timing signals used to time data and command transmission over highspeed data and command signaling links are paused or otherwise disabled when a memory system enters a low-power state, and require substantial time to be re-established at appropriate frequency and/or phase as the system returns to an active operating state. Instead of waiting for the high-speed timing signals to be re-established before beginning memory access operations, an alternative, lower-frequency timing source is used to time transfer of one or more memory-access commands over a combination of data and command signaling links while the high-speed timing signals are being restored, thereby hastening transmission of memory-access commands to memory devices and reducing the incremental latency required to exit the low-power state. A timing signal generators capable of glitchlessly shifting a timing signal between two or more oscillation frequencies may also (or alternatively) be provided, thus enabling different- frequency timing signals to be delivered to system components via the same timing signal paths in either operating state. When the timing signal is used to time data (or command) transfer over information-bearing signaling links, the ability to glitchlessly shift the timing signal frequency enables a corresponding glitchless shift between lower and higher data rates on the information-bearing signaling links.
摘要翻译：当存储器系统进入低功率状态并且需要大量时间以适当的频率重新建立时，用于对高速数据和命令信令链路上的数据和命令传输进行计时的一个或多个定时信号被暂停或以其他方式禁用和/或阶段，因为系统返回到活动的操作状态。代替在开始存储器访问操作之前等待高速定时信号被重新建立，替代的较低频率的定时源被用于通过数据和命令信令的组合来定时传送一个或多个存储器访问命令而高速定时信号正在恢复，从而加快了对存储器设备的存储器访问命令的传输，并减少了退出低功耗状态所需的增量等待时间。也可以（或者替代地）提供能够在两个或更多个振荡频率之间无故障地移位定时信号的定时信号发生器，从而使得不同频率定时信号能够在任一操作状态下经由相同定时信号路径被传送到系统组件。当使用定时信号来对通过信息承载的信令链路进行数据（或命令）传输时，无信号地改变定时信号频率的能力使信息承载信令链路上的较低和较高数据速率之间的相应无毛刺移位成为可能。

8. 发明申请

WO2010078384A3 METHOD AND APPARATUS FOR CORRECTING PHASE ERRORS DURING TRANSIENT EVENTS IN HIGH-SPEED SIGNALING SYSTEMS 审中-公开
标题翻译：用于在高速信号系统中的瞬态事件中校正相位误差的方法和装置
公开(公告)号：WO2010078384A3
公开(公告)日：2010-09-16
申请号：PCT/US2009069760
申请日：2009-12-29
申请人： RAMBUS INC , ZERBE JARED L
发明人： ZERBE JARED L
IPC分类号： H04L7/033 , H04L27/18
CPC分类号： H04L7/0083 , H03L7/07 , H03L7/0807 , H03L7/0814 , H04L7/0008
摘要： A system for dynamically correcting phase errors between data and a timing reference signal caused by a transient event during data communication between a transmitter and a receiver is described. During operation, the system stores one or more phase-offset values for the event in an offset table, wherein the constituent phase-offset values are associated with phase error caused by the event. Upon detecting a subsequent occurrence of the event, the system adjusts a phase relationship between the data and the timing reference signal based on the one or more phase-offset values.
摘要翻译：描述了用于在发射机和接收机之间的数据通信期间动态地校正由数据通信期间的瞬态事件引起的数据与定时参考信号之间的相位误差的系统。在操作期间，系统将一个或多个相位偏移值存储在偏移表中，其中组成相位偏移值与由事件引起的相位误差相关联。在检测到事件的后续发生时，系统基于一个或多个相位偏移值来调整数据和定时参考信号之间的相位关系。

9. 发明申请

WO2007024446A3 LINEAR TRANSFORMATION CIRCUITS 审中-公开
标题翻译：线性变换电路
公开(公告)号：WO2007024446A3
公开(公告)日：2008-09-18
申请号：PCT/US2006030411
申请日：2006-08-02
申请人： RAMBUS INC , AMIRKHANY AMIR , STOJANOVIC VLADIMIR M , ALON ELAD , ZERBE JARED L , HOROWITZ MARK A
发明人： AMIRKHANY AMIR , STOJANOVIC VLADIMIR M , ALON ELAD , ZERBE JARED L , HOROWITZ MARK A
IPC分类号： G06J1/00 , G06F17/14
CPC分类号： G06F17/141 , G06J1/005
摘要： A transform circuit includes a first circuit and a second circuit. The first circuit and the second circuit implement first and second mappings that together generate a pre-defined transform of N digital data symbols. The first circuit maps a set of N digital data symbols from N parallel data streams to N analog data symbols by generating N sets of first weighted sums of the N digital data symbols. Each respective first weighted sum is defined by a respective set of pre-determined first weighting values in a first matrix. The second circuit maps the N analog data symbols to a sequence of N output signals over N time intervals. Each of the N output signals corresponds to a respective second weighted sum of the N analog data symbols. Each respective second weighted sum is defined by a respective set of pre-determined second weighting values in a second matrix.
摘要翻译：变换电路包括第一电路和第二电路。第一电路和第二电路实现一起产生N个数字数据符号的预定义变换的第一和第二映射。第一电路通过产生N个数字数据符号的第一加权和的N组，将来自N个并行数据流的一组N个数字数据符号映射到N个模拟数据符号。每个相应的第一加权和由第一矩阵中的预定的第一加权值的相应集合来定义。第二电路在N个时间间隔内将N个模拟数据符号映射到N个输出信号的序列。 N个输出信号中的每一个对应于N个模拟数据符号的相应的第二加权和。每个相应的第二加权和由第二矩阵中的预定的第二加权值的相应集合来定义。

10. 发明申请

WO2006078845A3 HIGH-SPEED SIGNALING SYSTEMS WITH ADAPTABLE PRE-EMPHASIS AND EQUALIZATION 审中-公开
标题翻译：具有适应性前瞻性和均衡性的高速信号系统
公开(公告)号：WO2006078845A3
公开(公告)日：2007-02-15
申请号：PCT/US2006001944
申请日：2006-01-20
申请人： RAMBUS INC , ZERBE JARED L , CHEN FRED F , HO ANDREW , FARJAD-RAD RAMIN , POULTON JOHN W , DONNELLY KEVIN S , LEBOWITZ BRIAN
发明人： ZERBE JARED L , CHEN FRED F , HO ANDREW , FARJAD-RAD RAMIN , POULTON JOHN W , DONNELLY KEVIN S , LEBOWITZ BRIAN
IPC分类号： H04L25/03
CPC分类号： H04L27/01 , H04L1/0026 , H04L7/0025 , H04L7/0087 , H04L7/0337 , H04L25/0272 , H04L25/028 , H04L25/03057 , H04L25/03343 , H04L25/03885 , H04L25/497 , H04L2025/03503 , H04W52/20 , H04W52/225 , Y02B60/50
摘要： A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.
摘要翻译：一个信令系统包括一个预先强调的发射机和一个通过高速信号路径相互耦合的均衡接收机。接收机测量从发射机传送的数据的质量。控制器使用该信息和其他信息来自适应地建立适当的发送预加重和接收均衡设置，例如，选择信令系统提供一些最小通信带宽而不超过所需误码率的最低功率设置。

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