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1. 发明申请

WO2007024446A3 LINEAR TRANSFORMATION CIRCUITS 审中-公开
标题翻译：线性变换电路
公开(公告)号：WO2007024446A3
公开(公告)日：2008-09-18
申请号：PCT/US2006030411
申请日：2006-08-02
申请人： RAMBUS INC , AMIRKHANY AMIR , STOJANOVIC VLADIMIR M , ALON ELAD , ZERBE JARED L , HOROWITZ MARK A
发明人： AMIRKHANY AMIR , STOJANOVIC VLADIMIR M , ALON ELAD , ZERBE JARED L , HOROWITZ MARK A
IPC分类号： G06J1/00 , G06F17/14
CPC分类号： G06F17/141 , G06J1/005
摘要： A transform circuit includes a first circuit and a second circuit. The first circuit and the second circuit implement first and second mappings that together generate a pre-defined transform of N digital data symbols. The first circuit maps a set of N digital data symbols from N parallel data streams to N analog data symbols by generating N sets of first weighted sums of the N digital data symbols. Each respective first weighted sum is defined by a respective set of pre-determined first weighting values in a first matrix. The second circuit maps the N analog data symbols to a sequence of N output signals over N time intervals. Each of the N output signals corresponds to a respective second weighted sum of the N analog data symbols. Each respective second weighted sum is defined by a respective set of pre-determined second weighting values in a second matrix.
摘要翻译：变换电路包括第一电路和第二电路。第一电路和第二电路实现一起产生N个数字数据符号的预定义变换的第一和第二映射。第一电路通过产生N个数字数据符号的第一加权和的N组，将来自N个并行数据流的一组N个数字数据符号映射到N个模拟数据符号。每个相应的第一加权和由第一矩阵中的预定的第一加权值的相应集合来定义。第二电路在N个时间间隔内将N个模拟数据符号映射到N个输出信号的序列。 N个输出信号中的每一个对应于N个模拟数据符号的相应的第二加权和。每个相应的第二加权和由第二矩阵中的预定的第二加权值的相应集合来定义。

2. 发明申请

WO2009085417A2 MULTI-BAND, MULTI-DROP CHIP TO CHIP SIGNALING 审中-公开
标题翻译：多带，多芯片切片信号
公开(公告)号：WO2009085417A2
公开(公告)日：2009-07-09
申请号：PCT/US2008083231
申请日：2008-11-12
申请人： RAMBUS INC , ZERBE JARED L , STOJANOVIC VLADIMIR M , KOLLIPARA RAVINDRANATH , BEYENE WENDEMAGEGNEHU , AMIRKHANY AMIR , GARLEPP BRUNO
发明人： ZERBE JARED L , STOJANOVIC VLADIMIR M , KOLLIPARA RAVINDRANATH , BEYENE WENDEMAGEGNEHU , AMIRKHANY AMIR , GARLEPP BRUNO
IPC分类号： H04L25/08 , G06F13/40 , H04L5/06
CPC分类号： H04L5/06 , G06F13/4086 , H04L25/085
摘要： A multi-band, multi-drop signaling system. First, second and third integrated circuit devices are coupled to one another via a common signaling link. The first integrated circuit device includes a first transmitter to transmit a baseband signal via the signaling link and a second transmitter to transmit a signal centered around a non-zero frequency via the signaling link.
摘要翻译：一个多频段，多点信号系统。首先，第二和第三集成电路器件通过公共信令链路相互耦合。第一集成电路装置包括经由信令链路发送基带信号的第一发射机和经由信令链路发送以非零频率为中心的信号的第二发射机。

3. 发明申请

WO2006068694A8 ADJUSTABLE DUAL-BAND LINK 审中-公开
标题翻译：可调双链接
公开(公告)号：WO2006068694A8
公开(公告)日：2006-11-02
申请号：PCT/US2005038707
申请日：2005-10-26
申请人： RAMBUS INC , STOJANOVIC VLADIMIR M , AMIRKHANY AMIR , ZERBE JARED L
发明人： STOJANOVIC VLADIMIR M , AMIRKHANY AMIR , ZERBE JARED L
IPC分类号： H04L5/06 , H04L27/26
CPC分类号： H04L27/2637 , H04L5/06 , H04L27/2653
摘要： A communication system utilizing an adjustable link has at least a first data transmission circuit including at least a first communication link circuit. The first communication link circuit has a baseband circuit and at least a passband circuit. The baseband circuit corresponds to a baseband sub-channel and the passband circuit corresponds to a passband sub-channel. The first communication link circuit also includes a circuit that distributes a first subset of a data stream having a first symbol rate to the baseband circuit and a second subset of the data stream having a second symbol rate to the passband circuit. The baseband sub-channel and the passband sub-channel are separated by an adjacent guardband of frequencies. The passband carrier frequency is adjusted to define the guardband and the guardband corresponds to a first notch in a channel response of a first communications
摘要翻译：利用可调节链路的通信系统具有至少包括至少第一通信链路电路的第一数据传输电路。第一通信链路电路具有基带电路和至少一个通带电路。基带电路对应于基带子信道，通带电路对应于通带子信道。第一通信链路电路还包括将具有第一符号率的数据流的第一子集分配给基带电路的电路和具有第二符号速率的数据流的第二子集给通带电路。基带子信道和通带子信道被相邻的频带保护带隔开。调整通带载波频率以定义保护带，并且保护带对应于第一通信的信道响应中的第一个陷波

4. 发明申请

WO2004093144A3 PARTIAL RESPONSE RECEIVER 审中-公开
标题翻译：部分响应接收者
公开(公告)号：WO2004093144A3
公开(公告)日：2006-10-12
申请号：PCT/US2004010980
申请日：2004-04-09
申请人： RAMBUS INC , STOJANOVIC VLADIMIR M , HOROWITZ MARK A , ZERBE JARED L , BESSIOS ANTHONY , HO ANDREW C C , WEI JASON C , TSANG GRACE , GARLEPP BRUNO W
发明人： STOJANOVIC VLADIMIR M , HOROWITZ MARK A , ZERBE JARED L , BESSIOS ANTHONY , HO ANDREW C C , WEI JASON C , TSANG GRACE , GARLEPP BRUNO W
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159 , H04L25/06 , H04L25/497
CPC分类号： H04L25/03057 , H04L7/0276 , H04L25/063 , H04L25/497 , H04L2025/03369 , H04L2025/03503
摘要： A receive circuit for receiving a signal transmitted via an electrical signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample value that indicates whether the signal exceeds a second threshold level. A first select circuit receives the first and second sample values from the first and second sampling circuits and selects, according to a previously generated sample value, either the first sample value or the second sample value to be output as a selected sample value.
摘要翻译：用于接收通过电信号导体发送的信号的接收电路。第一采样电路产生指示信号是否超过第一阈值电平的第一采样值，并且第二采样电路产生指示信号是否超过第二阈值电平的第二采样值。第一选择电路从第一和第二采样电路接收第一和第二采样值，并根据先前产生的采样值选择作为选择的采样值输出的第一采样值或第二采样值。

5. 发明申请

WO2007024815A3 SIGNALING SYSTEM WITH DATA CORRELATION DETECTION 审中-公开
标题翻译：具有数据相关性检测的信号发送系统
公开(公告)号：WO2007024815A3
公开(公告)日：2007-04-19
申请号：PCT/US2006032687
申请日：2006-08-21
申请人： RAMBUS INC , STOJANOVIC VLADIMIR M , HO ANDREW , CHEN FRED F , LI SIMON
发明人： STOJANOVIC VLADIMIR M , HO ANDREW , CHEN FRED F , LI SIMON
IPC分类号： H04L25/03
CPC分类号： H04L25/03006
摘要： Conditionally updating equalization tap weights within an equalized signaling system based on a measure of correlation that indicates a difference between the number of received data values that have matching bits at a first pair of predetermined bit positions, and the number of received data values that have non-matching bits at the first pair of predetermined bit positions.
摘要翻译：基于指示在第一对预定比特位置处具有匹配比特的接收数据值的数量与具有非接收数据值的接收数据值的数量之间的差的相关性度量，在均衡信令系统内有条件地更新均衡抽头权重在第一对预定比特位置上匹配比特。

6. 发明申请

WO2005029743A3 DATA-LEVEL CLOCK RECOVERY 审中-公开
标题翻译：数据级时钟恢复
公开(公告)号：WO2005029743A3
公开(公告)日：2006-07-06
申请号：PCT/US2004029347
申请日：2004-09-08
申请人： RAMBUS INC , STOJANOVIC VLADIMIR M
发明人： STOJANOVIC VLADIMIR M
IPC分类号： H04L7/033 , H04L7/00
CPC分类号： H04L7/0331 , H04L7/0087 , H04L7/0334 , H04L7/0337
摘要： A circuit for adjusting the phase of a clock signal. A first sampling circuit (340) generates a sequence of data samples in response to transitions of the clock signal (176), each of the data samples having either a first state or a second state according to whether an incoming signal exceeds a first threshold. An second sampling circuit (361) generates an error sample in response to one of the transitions of the clock signal, the error sample having either the first state or the second state according to whether the incoming signal exceeds a second threshold. A phase adjust circuit adjusts the phase of the clock signal if the sequence of data samples matches a predetermined pattern and based, at least in part, on whether the error sample has the first state or the second state.
摘要翻译：用于调整时钟信号相位的电路。第一采样电路（340）响应于时钟信号（176）的转变产生数据样本序列，根据输入信号是否超过第一阈值，每个数据样本具有第一状态或第二状态。第二采样电路（361）根据输入信号是否超过第二阈值响应于时钟信号的转换之一产生误差采样，误差采样具有第一状态或第二状态。如果数据样本序列与预定模式匹配并且至少部分地基于该误差样本是否具有第一状态或第二状态，则相位调整电路调整时钟信号的相位。

7. 发明申请

WO2004008490A3 A SELECTABLE-TAP EQUALIZER, AUTO-CONFIGURED EQUALIZER, RECEIVING CIRCUIT HAVING AN EQUALIZER CALIBRATION FUNCTION, AND SYSTEM HAVING GROUPED REFLECTION CHARACTERISTICS 审中-公开
标题翻译：可选择的均衡器，自动配置的均衡器，接收均衡器校准功能的电路以及具有分组反射特性的系统
公开(公告)号：WO2004008490A3
公开(公告)日：2008-11-06
申请号：PCT/US0321566
申请日：2003-07-10
申请人： RAMBUS INC
发明人： ZERBE JARED L , STOJANOVIC VLADIMIR M , CHEN FRED F
IPC分类号： H03H7/30 , H03M13/00 , H04L25/03
CPC分类号： H04L25/03038 , H04L25/03343 , H04L25/03885
摘要： A selectable-tap equalizer, auto-configured equalizer, receiving circuit having an equalizer calibration function, and system having grouped reflection characteristics is provided. The selectable-tap equalizer includes a buffer, a select circuit and an equalizing circuit. The auto-configured equalizer includes a scoping circuit, buffer circuit, select circuit and equalizing circuit. The receiving circuit includes a sampling circuit, output driver and clock signal generator. The system includes a transmit circuit, a receive circuit, and a signal path coupled between the transmit circuit and the receive circuit. The signal path includes a first signal path segment coupled between the transmit circuit and a first interface, and a second signal path segment coupled between the receive circuit and a second interface, the second signal path having an electrical length that is substantially equal to an electrical length of the first signal path segment.
摘要翻译：提供了可选择抽头均衡器，自动配置均衡器，具有均衡器校准功能的接收电路和具有分组反射特性的系统。可选择抽头均衡器包括缓冲器，选择电路和均衡电路。自动配置的均衡器包括一个示波电路，缓冲电路，选择电路和均衡电路。接收电路包括采样电路，输出驱动器和时钟信号发生器。该系统包括发射电路，接收电路和耦合在发射电路和接收电路之间的信号路径。信号路径包括耦合在发射电路和第一接口之间的第一信号路径段和耦合在接收电路和第二接口之间的第二信号路径段，第二信号路径具有基本上等于电第一信号路径段的长度。

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