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1. 发明申请

WO2007024446A3 LINEAR TRANSFORMATION CIRCUITS 审中-公开
标题翻译：线性变换电路
公开(公告)号：WO2007024446A3
公开(公告)日：2008-09-18
申请号：PCT/US2006030411
申请日：2006-08-02
申请人： RAMBUS INC , AMIRKHANY AMIR , STOJANOVIC VLADIMIR M , ALON ELAD , ZERBE JARED L , HOROWITZ MARK A
发明人： AMIRKHANY AMIR , STOJANOVIC VLADIMIR M , ALON ELAD , ZERBE JARED L , HOROWITZ MARK A
IPC分类号： G06J1/00 , G06F17/14
CPC分类号： G06F17/141 , G06J1/005
摘要： A transform circuit includes a first circuit and a second circuit. The first circuit and the second circuit implement first and second mappings that together generate a pre-defined transform of N digital data symbols. The first circuit maps a set of N digital data symbols from N parallel data streams to N analog data symbols by generating N sets of first weighted sums of the N digital data symbols. Each respective first weighted sum is defined by a respective set of pre-determined first weighting values in a first matrix. The second circuit maps the N analog data symbols to a sequence of N output signals over N time intervals. Each of the N output signals corresponds to a respective second weighted sum of the N analog data symbols. Each respective second weighted sum is defined by a respective set of pre-determined second weighting values in a second matrix.
摘要翻译：变换电路包括第一电路和第二电路。第一电路和第二电路实现一起产生N个数字数据符号的预定义变换的第一和第二映射。第一电路通过产生N个数字数据符号的第一加权和的N组，将来自N个并行数据流的一组N个数字数据符号映射到N个模拟数据符号。每个相应的第一加权和由第一矩阵中的预定的第一加权值的相应集合来定义。第二电路在N个时间间隔内将N个模拟数据符号映射到N个输出信号的序列。 N个输出信号中的每一个对应于N个模拟数据符号的相应的第二加权和。每个相应的第二加权和由第二矩阵中的预定的第二加权值的相应集合来定义。

2. 发明申请

WO8900279A3 ANALOG-DIGITAL CORRELATOR 审中-公开
标题翻译：模拟 - 数字相关器
公开(公告)号：WO8900279A3
公开(公告)日：1989-02-09
申请号：PCT/US8802159
申请日：1988-06-22
申请人： HUGHES AIRCRAFT CO
发明人： BURNS RICHARD J , GRIM KENNETH R , LEVY MIGUEL E
IPC分类号： G01J1/44 , G01S7/292 , G01S13/28 , G06J1/00 , G01J1/00
CPC分类号： G01S13/288 , G06J1/005
摘要： An analog-digital correlator (10) utilizes a plurality of sample and hold circuits (16-0 to 16-(M-1)) to directly store samples of a received analog signal. Bits of a correlation pattern are shifted through stages in a correlation pattern shift register (26). The state of the correlation pattern bits causes the value in the associated sample and hold circuit (16) to either be inverted or noninverted when it is summed with other similarly generated signals from the remaining sample and hold circuits to form the correlation output sum by network (30). The output of network (30) will peak when the bits of the digital correlation pattern signal are shifted to stages in register (26) that are aligned with the sample and hold circuits containing the digitally-impressed code of interest. In the preferred embodiment, a mask shift register (28) is used to selectively disable certain of the sample and hold circuits from affecting the correlation output sum. To this end, mask bits corresponding to the length of the digitally-impressed code are shifted through mask register (28) simultaneously with the correlation pattern bits in register (26).
摘要翻译：模拟数字相关器（10）利用多个采样和保持电路（16-0至16-（M-1））来直接存储接收到的模拟信号的采样。相关模式的位在相关模式移位寄存器（26）中通过级进行移位。相关模式位的状态使得相关的采样和保持电路（16）中的值在与来自其余采样和保持电路的其他类似产生的信号相加以通过网络形成相关输出和时被反转或不反转（30）。当数字相关模式信号的位移位到寄存器（26）中与包含数字印记代码的采样和保持电路对齐的级中时，网络（30）的输出将达到峰值。在优选实施例中，使用掩模移位寄存器（28）来选择性地禁止某些采样和保持电路影响相关输出和。为此，与数字加压代码的长度相对应的掩码位通过掩码寄存器（28）与寄存器（26）中的相关模式位同时移位。

3. 发明申请

WO2017131711A1 MEMRISTOR CROSSBAR ARRAY FOR PERFORMING A FOURIER TRANSFORMATION 审中-公开
标题翻译： MEMRISTOR CROSSBAR阵列用于执行傅立叶变换
公开(公告)号：WO2017131711A1
公开(公告)日：2017-08-03
申请号：PCT/US2016/015429
申请日：2016-01-28
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： STRACHAN, John Paul , HU, Miao , WILLIAMS, R. Stanley , LI, Zhiyong
IPC分类号： G06F17/14 , B81B7/04
CPC分类号： G06J1/005
摘要： A technique includes providing a first set of values to a memristor crossbar array and using the memristor crossbar array to perform a Fourier transformation. Using the memristor crossbar array to perform the Fourier transform includes using the array to apply a Discrete Fourier Transform (DFT) to the first set of values to provide a second set of values.
摘要翻译：一种技术包括向忆阻器交叉开关阵列提供第一组值并使用忆阻器交叉开关阵列执行傅立叶变换。使用忆阻器交叉开关阵列执行傅里叶变换包括使用该阵列对第一组值施加离散傅里叶变换（DFT）以提供第二组值。

4. 发明申请

WO2012091582A1 SYSTEM FOR DIRECT DISCRETE HILBERT TRANSFORM 审中-公开
标题翻译：直接离散HILBERT变换系统
公开(公告)号：WO2012091582A1
公开(公告)日：2012-07-05
申请号：PCT/PL2011/000144
申请日：2011-12-28
申请人： UNIWERSYTET TECHNICZNO-PRZYRODNICZY IM. JANA I JĘDRZEJA ŚNIADECKICH W BYDGOSZCZY , POGRIBNY Włodzimierz , SULIMA Mariusz
发明人： POGRIBNY Włodzimierz , SULIMA Mariusz
IPC分类号： G06J1/00 , G06F17/14
CPC分类号： G06J1/005 , G06F17/14
摘要： The subject of the invention is a multi-channel system for direct Discrete Hilbert Transform (DHT) in PCM format (pulse-code modulation) based on a parallel structure. The system enables determination of all 2 N + 1 output samples of DHT within time that does not exceed one sampling period T s of analogue/digital converter /4/ immediately after the last sample of input signal is received. It also enables the application of weighted impulse response (formule I) to ensure higher resolution of DHT. The system according to the invention wherein at input side, it has one analogue/digital converter /4/, with output parallelly connected to inputs of 2 N +1 multiplication units /3 -N /-/3 N / The second input of each multiplication unit is connected to specific output of the cyclic register /2/. The cyclic register has 2 N + 1 outputs from which weight factors are collected. In each (formule II) channel, output of the multiplication unit /3 j / is connected with an individual input of each accumulator channel /5 j /, where products of input signal samples and relevant weight factors are added. Finally, after processing 2 N + 1 samples of input signal (formule III), complete DHT result (formule IV) appears at outputs of channel accumulators /5 j /. A common element for all channels is controller ( clock ) /1/, whose signals come at Τ s -1 frequency.
摘要翻译：本发明的主题是基于并行结构的用于以PCM格式（脉冲编码调制）的直接离散希尔伯特变换（DHT）的多通道系统。该系统能够在接收到最后一个输入信号采样之后，立即在不超过模拟/数字转换器/ 4的一个采样周期T s的时间内确定DHT的所有2N + 1个输出采样。它还能够应用加权脉冲响应（Formule I）来确保DHT的更高分辨率。根据本发明的系统，其中在输入侧具有一个模拟/数字转换器/ 4 /，其输出并联连接到2N + 1个乘法单元的输入/ 3-N / - / 3N /每个乘法单元的第二输入连接到循环寄存器/ 2 /的特定输出。循环寄存器具有2N + 1个输出，从中收集权重因子。在每个（组合II）通道中，乘法单元/ 3j /的输出与每个累加器通道/ 5j /的单独输入连接，其中输入信号样本和相关权重因子的乘积被相加。最后，在处理2N + 1个输入信号采样（表III）之后，在信道累加器/ 5j /的输出端出现完整的DHT结果（第四组）。所有通道的常用元件是控制器（时钟）/ 1 /，其信号进入？ s -1频率。

5. 发明申请

WO2007024446A2 LINEAR TRANSFORMATION CIRCUITS 审中-公开
标题翻译：线性变换电路
公开(公告)号：WO2007024446A2
公开(公告)日：2007-03-01
申请号：PCT/US2006/030411
申请日：2006-08-02
申请人： RAMBUS INC. , AMIRKHANY, Amir , STOJANOVIC, Vladimir, M. , ALON, Elad , ZERBE, Jared, L. , HOROWITZ, Mark, A.
发明人： AMIRKHANY, Amir , STOJANOVIC, Vladimir, M. , ALON, Elad , ZERBE, Jared, L. , HOROWITZ, Mark, A.
IPC分类号： G06F17/14
CPC分类号： G06F17/141 , G06J1/005
摘要： A transform circuit includes a first circuit and a second circuit. The first circuit and the second circuit implement first and second mappings that together generate a pre-defined transform of N digital data symbols. The first circuit maps a set of N digital data symbols from N parallel data streams to N analog data symbols by generating N sets of first weighted sums of the N digital data symbols. Each respective first weighted sum is defined by a respective set of pre-determined first weighting values in a first matrix. The second circuit maps the N analog data symbols to a sequence of N output signals over N time intervals. Each of the N output signals corresponds to a respective second weighted sum of the N analog data symbols. Each respective second weighted sum is defined by a respective set of pre-determined second weighting values in a second matrix.
摘要翻译：变换电路包括第一电路和第二电路。第一电路和第二电路实现一起产生N个数字数据符号的预定义变换的第一和第二映射。第一电路通过产生N个数字数据符号的第一加权和的N组，将来自N个并行数据流的一组N个数字数据符号映射到N个模拟数据符号。每个相应的第一加权和由第一矩阵中的预定的第一加权值的相应集合来定义。第二电路在N个时间间隔内将N个模拟数据符号映射到N个输出信号的序列。 N个输出信号中的每一个对应于N个模拟数据符号的相应的第二加权和。每个相应的第二加权和由第二矩阵中的预定的第二加权值的相应集合来定义。

6. 发明申请

WO1989000279A2 ANALOG-DIGITAL CORRELATOR 审中-公开
标题翻译：模拟数字相关器
公开(公告)号：WO1989000279A2
公开(公告)日：1989-01-12
申请号：PCT/US1988002159
申请日：1988-06-22
申请人： HUGHES AIRCRAFT COMPANY
发明人： HUGHES AIRCRAFT COMPANY , BURNS, Richard, J. , GRIM, Kenneth, R. , LEVY, Miguel, E.
IPC分类号： G01J01/00
CPC分类号： G01S13/288 , G06J1/005
摘要： An analog-digital correlator (10) utilizes a plurality of sample and hold circuits (16-0 to 16-(M-1)) to directly store samples of a received analog signal. Bits of a correlation pattern are shifted through stages in a correlation pattern shift register (26). The state of the correlation pattern bits causes the value in the associated sample and hold circuit (16) to either be inverted or noninverted when it is summed with other similarly generated signals from the remaining sample and hold circuits to form the correlation output sum by network (30). The output of network (30) will peak when the bits of the digital correlation pattern signal are shifted to stages in register (26) that are aligned with the sample and hold circuits containing the digitally-impressed code of interest. In the preferred embodiment, a mask shift register (28) is used to selectively disable certain of the sample and hold circuits from affecting the correlation output sum. To this end, mask bits corresponding to the length of the digitally-impressed code are shifted through mask register (28) simultaneously with the correlation pattern bits in register (26).

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