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1. 发明申请

WO2007134135A2 SYSTEM AND METHOD OF SILICON SWITCHED POWER DELIVERY USING A PACKAGE 审中-公开
标题翻译：使用包装的硅切换电源的系统和方法
公开(公告)号：WO2007134135A2
公开(公告)日：2007-11-22
申请号：PCT/US2007/068608
申请日：2007-05-09
申请人： QUALCOMM Incorporated , CHUA-EOAN, Lew G. , TOMS, Thomas R. , ANDREEV, Boris Dimitrov , GAGNE, Justin Joseph Rosen , SHI, Chunlei
发明人： CHUA-EOAN, Lew G. , TOMS, Thomas R. , ANDREEV, Boris Dimitrov , GAGNE, Justin Joseph Rosen , SHI, Chunlei
IPC分类号： H03K19/00
CPC分类号： H03K17/223 , H01L2924/0002 , H01L2924/00
摘要： In one particular embodiment, an integrated circuit includes a package and a substrate electrically and physically coupled to the package. The package includes a first pin, a second pin, and metallization coupling the first pin to the second pin. The substrate is coupled to the package via the first pin and the second pin. The substrate includes a plurality of power domains and a power control unit. The second pin of the package is coupled to a particular power domain of the plurality of power domains. The power control unit includes logic and a switch, where the switch includes a first terminal coupled to a voltage supply terminal, a control terminal coupled to the logic, and a second terminal coupled to the first pin of the package. The logic selectively activates the switch to distribute power to the particular power domain via the metallization of the package.
摘要翻译：在一个具体实施例中，集成电路包括电气和物理耦合到封装的封装和衬底。封装包括第一引脚，第二引脚和将第一引脚耦合到第二引脚的金属化。衬底经由第一引脚和第二引脚耦合到封装。基板包括多个电力域和功率控制单元。封装的第二引脚耦合到多个电源域的特定电源域。功率控制单元包括逻辑和开关，其中开关包括耦合到电压源端子的第一端子，耦合到逻辑电路的控制端子和耦合到封装的第一引脚的第二端子。逻辑选择性地激活开关以通过封装的金属化分配功率到特定的功率域。

2. 发明申请

WO2007133899A1 SYSTEM AND METHOD OF POWER DISTRIBUTION CONTROL OF AN INTEGRATED CIRCUIT 审中-公开
标题翻译：集成电路功率分配控制系统与方法
公开(公告)号：WO2007133899A1
公开(公告)日：2007-11-22
申请号：PCT/US2007/067227
申请日：2007-04-23
申请人： QUALCOMM Incorporated , CHUA-EOAN, Lew G. , ANDREEV, Boris , RIDDLE, Christopher C. , SHI, Chunlei , JUNG, Seong-ook , TOMS, Thomas R. , GAGNE, Justin Joseph Rosen
发明人： CHUA-EOAN, Lew G. , ANDREEV, Boris , RIDDLE, Christopher C. , SHI, Chunlei , JUNG, Seong-ook , TOMS, Thomas R. , GAGNE, Justin Joseph Rosen
IPC分类号： H03K19/00
CPC分类号： H03K19/0016 , H02M3/158 , H02M2001/009
摘要： A device is disclosed that includes a first pin to supply power to a first power domain of an integrated circuit, a second pin to supply power to a second power domain of the integrated circuit, a switching regulator and a controller. The switching regulator is coupled to the first pin to provide a first regulated power supply to the first power domain and is coupled to the second pin to provide a second regulated power supply to the second power domain. The controller is coupled to the first pin and to the second pin to selectively reduce current flow to at least the second pin during a low power event.
摘要翻译：公开了一种器件，其包括用于向集成电路的第一电源域供电的第一引脚，向集成电路的第二电源域供电的第二引脚，开关稳压器和控制器。开关调节器耦合到第一引脚，以向第一功率域提供第一稳压电源，并且耦合到第二引脚以向第二功率域提供第二稳压电源。控制器耦合到第一引脚和第二引脚，以在低功率事件期间选择性地减少至少第二引脚的电流。

3. 发明申请

WO2011044392A1 THREE DIMENSIONAL INDUCTOR AND TRANSFORMER 审中-公开
标题翻译：三维电感和变压器
公开(公告)号：WO2011044392A1
公开(公告)日：2011-04-14
申请号：PCT/US2010/051868
申请日：2010-10-07
申请人： QUALCOMM Incorporated , KIM, Jonghae , GU, Shiqun , HENDERSON, Brian Matthew , TOMS, Thomas R. , CHUA-EOAN, Lew G. , BAZARJANI, Seyfollah S. , NOWAK, Matthew
发明人： KIM, Jonghae , GU, Shiqun , HENDERSON, Brian Matthew , TOMS, Thomas R. , CHUA-EOAN, Lew G. , BAZARJANI, Seyfollah S. , NOWAK, Matthew
IPC分类号： H01L21/02 , H01L23/522 , H01F17/00 , H01L27/06 , H01L23/48
CPC分类号： H01L28/10 , H01F17/0013 , H01F19/04 , H01F2017/002 , H01L23/481 , H01L23/5227 , H01L27/0207 , H01L2224/16145 , H01L2924/3011
摘要： A three dimensional on-chip inductor, transformer and radio frequency amplifier are disclosed. The radio frequency amplifier includes a pair of transformers and a transistor. The transformers include at least two inductively coupled inductors. The inductors include a plurality of segments (704) of a first metal layer, a plurality of segments (706) of a second metal layer, a first inductor input (708) a second inductor input (710) and a plurality of through silicon vias (702) coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input. The inductors can have a symmetric or asymmetric geometry. The first metal layer can be a metal layer in the back-end-of-line section of the chip. The second metal layer can be located in the redistributed design layer of the chip
摘要翻译：公开了三维片上电感器，变压器和射频放大器。射频放大器包括一对变压器和晶体管。变压器包括至少两个电感耦合电感器。电感器包括第一金属层的多个段（704），第二金属层的多个段（706），第一电感器输入端（708），第二电感器输入端（710）和多个通孔硅通孔（702），耦合所述第一金属层的所述多个段和所述第二金属层的所述多个段，以在所述第一电感器输入和所述第二电感器输入之间形成连续的，不相交的路径。电感器可以具有对称或不对称的几何形状。第一金属层可以是芯片的后端部分中的金属层。第二金属层可以位于芯片的再分布设计层中

4. 发明申请

WO2010075331A1 EMBEDDED THROUGH SILICON STACK 3-D DIE IN A PACKAGE SUBSTRATE 审中-公开
标题翻译：通过硅包堆叠在包装基板中的三维模具
公开(公告)号：WO2010075331A1
公开(公告)日：2010-07-01
申请号：PCT/US2009/069102
申请日：2009-12-22
申请人： QUALCOMM INCORPORATED , RAY, Urmi , SWEENEY, Fifin , KASKOUN, Kenneth , GU, Shiqun , TOMS, Thomas R.
发明人： RAY, Urmi , SWEENEY, Fifin , KASKOUN, Kenneth , GU, Shiqun , TOMS, Thomas R.
IPC分类号： H01L23/538 , H01L25/065
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/5383 , H01L23/5385 , H01L23/5389 , H01L25/03 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06541 , H01L2225/06568 , H01L2924/00014 , H01L2924/15311 , H01L2224/0401
摘要： An integrated circuit package has a die or die stack with through silicon vias embedded in a package substrate. A method of producing an integrated circuit package embeds at least one die with a through silicon via in a package substrate. The package substrate provides a protective cover for the die or die stack.
摘要翻译：集成电路封装具有通过硅通孔嵌入封装衬底中的管芯或管芯堆叠。一种制造集成电路封装件的方法在封装衬底中嵌入具有穿硅通孔的至少一个管芯。封装衬底提供用于管芯或管芯堆叠的保护盖。

5. 发明申请

WO2012021775A2 SYSTEM AND METHOD TO INITIATE A HOUSEKEEPING OPERATION AT A MOBILE DEVICE 审中-公开
标题翻译：在移动设备上启动家庭操作的系统和方法
公开(公告)号：WO2012021775A2
公开(公告)日：2012-02-16
申请号：PCT/US2011/047535
申请日：2011-08-12
申请人： QUALCOMM INCORPORATED , TOMS, Thomas R. , RAO, Hari M. , KANG, Seung H. , KIM, Jung Pill , SUH, Jungwon
发明人： TOMS, Thomas R. , RAO, Hari M. , KANG, Seung H. , KIM, Jung Pill , SUH, Jungwon
IPC分类号： G11C16/30 , G11C5/14 , H04W52/00
CPC分类号： G11C16/3418 , G06F1/263 , G06F11/1048
摘要： A system and method to initiate a housekeeping operation at a mobile device is disclosed. In a particular embodiment, a method at a mobile device includes modifying a scheduled housekeeping operation in response to determining that the mobile device is in a charging mode.
摘要翻译：公开了一种在移动设备处启动内务操作的系统和方法。在特定实施例中，移动设备处的方法包括响应于确定移动设备处于充电模式而修改预定的内务操作。

6. 发明申请

WO2010068785A1 PARALLEL PLANE MEMORY AND PROCESSOR COUPLING IN A 3-D MICRO-ARCHITECTURAL SYSTEM 审中-公开
标题翻译：三维微结构系统中的并行平面存储器和处理器耦合
公开(公告)号：WO2010068785A1
公开(公告)日：2010-06-17
申请号：PCT/US2009/067544
申请日：2009-12-10
申请人： QUALCOMM Incorporated , TOMS, Thomas R.
发明人： TOMS, Thomas R.
IPC分类号： H01L25/18 , H01L25/065
CPC分类号： G06F13/42 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： An IC device (10) is constructed in a manner that allows for the memory (12), (13) and processor elements (11), (14) to be positioned one above the other on parallel planes of a 3-D structure. Interconnections (31), (32), (33) between the memory (s) and the processor (s) are accomplished by using through substrate stacking (TSS) techniques. This arrangement provides the processor with direct access to the memory by reducing the distance between the memory and the processor.
摘要翻译： IC器件（10）以允许存储器（12），（13）和处理器元件（11），（14）在3-D结构的平行平面上一个位于另一个之上的方式构造。存储器和处理器之间的互连（31），（32），（33）通过使用通过衬底堆叠（TSS）技术来实现。这种布置使处理器能够通过减少存储器和处理器之间的距离来直接访问存储器。

7. 发明申请

WO2011097630A2 SYSTEMS AND METHODS PROVIDING ARRANGEMENTS OF VIAS 审中-公开
标题翻译：提供VIAS安排的系统和方法
公开(公告)号：WO2011097630A2
公开(公告)日：2011-08-11
申请号：PCT/US2011/024058
申请日：2011-02-08
申请人： QUALCOMM Incorporated , GU, Shiqun , NOWAK, Matthew Michael , LISK, Durodami J. , TOMS, Thomas R. , RAY, Urmi , SUH, Jungwon , CHANDRASEKARAN, Arvind
发明人： GU, Shiqun , NOWAK, Matthew Michael , LISK, Durodami J. , TOMS, Thomas R. , RAY, Urmi , SUH, Jungwon , CHANDRASEKARAN, Arvind
IPC分类号： H01L25/065
CPC分类号： H01L23/5286 , H01L23/3677 , H01L23/481 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/48 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05093 , H01L2224/13009 , H01L2224/13025 , H01L2224/13028 , H01L2224/131 , H01L2224/14505 , H01L2224/16145 , H01L2224/16146 , H01L2224/17517 , H01L2224/48091 , H01L2224/48227 , H01L2224/81136 , H01L2224/81193 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2225/06562 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor chip includes an array of electrical contacts and multiple vias coupling at least one circuit in the semiconductor chip to the array of electrical contacts. A first one of the electrical contacts of the array of electrical contacts is coupled to N vias, and a second one of the electrical contacts of the array of electrical contacts is coupled to M vias. M and N are positive integers of different values.
摘要翻译：半导体芯片包括电连接阵列和将半导体芯片中的至少一个电路耦合到电接触阵列的多个通孔。电触点阵列的电触点中的第一个耦合到N个通孔，并且电触点阵列的电触点中的第二个耦合到M个通孔。 M和N是不同值的正整数。

8. 发明申请

WO2010045413A1 ELECTROSTATIC DISCHARGE (ESD) SHIELDING FOR STACKED ICS 审中-公开
标题翻译：用于堆叠ICS的静电放电（ESD）屏蔽
公开(公告)号：WO2010045413A1
公开(公告)日：2010-04-22
申请号：PCT/US2009/060764
申请日：2009-10-15
申请人： QUALCOMM INCORPORATED , TOMS, Thomas R. , JALILIZEINALI, Reza , GU, Shiqun
发明人： TOMS, Thomas R. , JALILIZEINALI, Reza , GU, Shiqun
IPC分类号： H01L25/065 , H01L23/60
CPC分类号： H01L23/60 , H01L25/0657 , H01L2224/274 , H01L2924/01055 , H01L2924/12044
摘要： An unassembled stacked IC device (60) includes an unassembled tier. (41) The unassembled stacked IC device also includes a first unpatterned layer (610) on the unassembled tier. The first unpatterned layer protects the unassembled tier from ESD events.
摘要翻译：未组装的堆叠式IC器件（60）包括未组装的层。（41）未组装的堆叠IC器件还包括在未组装层上的第一未图案化层（610）。第一个无图案层保护未组装的层免受ESD事件的影响。

9. 发明申请

WO2009158287A1 ACTIVE THERMAL CONTROL FOR STACKED IC DEVICES 审中-公开
标题翻译：堆叠IC器件的主动热控制
公开(公告)号：WO2009158287A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/048031
申请日：2009-06-19
申请人： QUALCOMM INCORPORATED , GU, Shiqun , NOWAK, Matthew , TOMS, Thomas R.
发明人： GU, Shiqun , NOWAK, Matthew , TOMS, Thomas R.
IPC分类号： H01L25/065 , H01L23/38
CPC分类号： H05K7/20 , H01L23/38 , H01L25/0657 , H01L2224/05571 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06589 , H01L2924/00014 , H01L2224/05599
摘要： Thermal conductivity in a stacked IC device (30) can be improved by constructing one or more active temperature control devices within the stacked IC device. In one embodiment, the control devices are thermal electric (TE) devices, such as Peltier devices. The TE devices (300) can then be selectively controlled to remove or add heat, as necessary, to maintain the stacked IC device within a defined temperature range. The active temperature control elements can be P-N junctions (301, 302) created in the stacked IC device and can serve to move the heat laterally and/or vertically, as desired.
摘要翻译：通过在堆叠的IC器件内构造一个或多个有源温度控制器件，可以提高层叠IC器件（30）中的导热性。在一个实施例中，控制装置是诸如珀耳帖装置之类的热电（TE）装置。然后可根据需要选择性地控制TE器件（300）以去除或加热，以将堆叠的IC器件保持在规定的温度范围内。有源温度控制元件可以是在堆叠的IC器件中产生的P-N结（301,302），并且可以根据需要用于横向和/或垂直地移动热量。

10. 发明申请

WO2006063248A1 SYSTEM AND METHOD TO DETERMINE PEAK POWER DEMAND IN AN INTEGRATED CIRCUIT 审中-公开
标题翻译：确定集成电路中峰值功率需求的系统和方法
公开(公告)号：WO2006063248A1
公开(公告)日：2006-06-15
申请号：PCT/US2005/044655
申请日：2005-12-08
申请人： QUALCOMM INCORPORATED , TOMS, Thomas R.
发明人： TOMS, Thomas R.
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method comprises receiving a description of a power distribution network of a circuit, defining at least one DC supernode in the power distribution network, receiving a logical description of the circuit, and determining at least one logic path in the circuit. The method further comprises traversing the at least one logic path in reverse and determining at least one input vector of the at least one logic path. The input vector describes a plurality of nodes in the logic path and a logic transition at an output node occurring in response to a combination of logic transitions at at least one input node in the at least one logic path. The method further comprises assigning a weighting value to each logic transition of each node in the at least one input vector, identifying at least one input vector with maximum contribution to drawing power from the power distribution network as indicated by the assigned weighting, and simulating an AC response of the identified at least one input vector with maximum contribution and identifying at least one logic path generating a peak load to the power distribution network.
摘要翻译：一种方法包括接收电路的配电网络的描述，在配电网络中定义至少一个DC超级节点，接收电路的逻辑描述，以及确定电路中的至少一个逻辑路径。该方法还包括相反地遍历至少一个逻辑路径并确定至少一个逻辑路径的至少一个输入向量。输入向量描述了逻辑路径中的多个节点和响应于至少一个逻辑路径中的至少一个输入节点处的逻辑转换的组合而发生的输出节点处的逻辑转换。所述方法还包括为所述至少一个输入向量中的每个节点的每个逻辑转换分配加权值，识别至少一个输入向量，所述至少一个输入向量对所分配的权重所指示的来自所述配电网络的绘图功率具有最大贡献，并且模拟所识别的至少一个输入向量的AC响应具有最大贡献，并且识别生成到配电网络的峰值负载的至少一个逻辑路径。

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