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1. 发明申请

WO2010085671A1 BUTTON SENSOR 审中-公开
标题翻译：按钮传感器
公开(公告)号：WO2010085671A1
公开(公告)日：2010-07-29
申请号：PCT/US2010/021841
申请日：2010-01-22
申请人： QUALCOMM INCORPORATED , MATSUMORI, Barry, Alan , KASKOUN, Kenneth , NOWAK, Matthew , YU, Nicholas
发明人： MATSUMORI, Barry, Alan , KASKOUN, Kenneth , NOWAK, Matthew , YU, Nicholas
IPC分类号： A61B5/00
CPC分类号： A61B5/6804 , A41D2300/32 , A61B5/0006 , A61B5/0008 , A61B5/002 , A61B5/0024 , A61B5/02 , A61B5/6802 , G06F1/163 , G06F19/00 , G06F19/3418 , G08B21/0438 , Y10T29/49002
摘要： A hermetically sealed electronic closure device, or button, includes a self-renewing power source, a sensor for measuring a metric, a memory storing information, a data processing circuit for controlling operations of the device, and a transceiver for sending and receiving information. The device is a standard part of a clothing item that is inconspicuous to a wearer of the clothing item.
摘要翻译：密封电子封闭装置或按钮包括自更新电源，用于测量度量的传感器，存储信息的存储器，用于控制设备的操作的数据处理电路以及用于发送和接收信息的收发器。该装置是与服装项目的佩戴者不显眼的服装物品的标准部分。

2. 发明申请

WO2010065667A2 WIRELESS BRANDING 审中-公开
标题翻译：无线品牌
公开(公告)号：WO2010065667A2
公开(公告)日：2010-06-10
申请号：PCT/US2009/066450
申请日：2009-12-02
申请人： QUALCOMM Incorporated , KASKOUN, Kenneth , MATSUMORI, Barry , YU, Nicholas , NOWAK, Matthew
发明人： KASKOUN, Kenneth , MATSUMORI, Barry , YU, Nicholas , NOWAK, Matthew
IPC分类号： H04B7/00 , G06Q99/00
CPC分类号： G06Q30/02 , G06Q30/0185
摘要： A device wirelessly broadcasts branding information associated with a consumer product attached to the device. The branding information is sent to a receiver located remotely from the product.
摘要翻译：设备无线地广播与附接到设备的消费者产品相关联的品牌信息。品牌信息被发送到远离产品的接收器。

3. 发明申请

WO2010030532A1 SYSTEMS AND METHODS FOR ENABLING ESD PROTECTION ON 3-D STACKED DEVICES 审中-公开
标题翻译：用于在三维堆叠设备上实现ESD保护的系统和方法
公开(公告)号：WO2010030532A1
公开(公告)日：2010-03-18
申请号：PCT/US2009/055620
申请日：2009-09-01
申请人： QUALCOMM INCORPORATED , KASKOUN, Kenneth , GU, Shiqun , NOWAK, Matthew
发明人： KASKOUN, Kenneth , GU, Shiqun , NOWAK, Matthew
IPC分类号： H01L25/065 , H01L23/60 , H01L23/48
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/60 , H01L24/06 , H01L24/16 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/13099 , H01L2224/14181 , H01L2224/16145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01027 , H01L2924/01033 , H01L2924/01093 , H01L2924/10253 , H01L2924/14 , H01L2924/00 , H01L2224/05552
摘要： An electrostatic discharge (ESD) protection device is fabricated in a vertical space between active layers of stacked semiconductor dies thereby utilizing space that would otherwise be used only for communication purposes. The vertical surface area of the through silicon vias (TSVs) is used for absorbing large voltages resulting from ESD events. In one embodiment, an ESD diode is created in a vertical TSV between active layers of the semiconductor dies of a stacked device. This ESD diode can be shared by circuitry on both semiconductor dies of the stack thereby saving space and reducing die area required by ESD protection circuitry.
摘要翻译：在堆叠的半导体管芯的有源层之间的垂直空间中制造静电放电（ESD）保护装置，从而利用否则将仅用于通信目的的空间。通过硅通孔（TSV）的垂直表面积用于吸收由ESD事件引起的大电压。在一个实施例中，在层叠器件的半导体管芯的有源层之间的垂直TSV中产生ESD二极管。该ESD二极管可以由堆叠的两个半导体管芯上的电路共享，从而节省了ESD保护电路所需的空间和减小管芯面积。

4. 发明申请

WO2010048259A1 MAGNETIC TUNNEL JUNCTION AND METHOD OF FABRICATION 审中-公开
标题翻译：磁性隧道结和制造方法
公开(公告)号：WO2010048259A1
公开(公告)日：2010-04-29
申请号：PCT/US2009/061438
申请日：2009-10-21
申请人： QUALCOMM INCORPORATED , LI, Xia , KANG, Seung H. , ZHU, Xiaochun , LEE, Kangho , NOWAK, Matthew
发明人： LI, Xia , KANG, Seung H. , ZHU, Xiaochun , LEE, Kangho , NOWAK, Matthew
IPC分类号： H01L43/08 , H01L43/12
CPC分类号： H01L43/12 , H01L43/08
摘要： In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device (200) includes applying a dielectric layer (240) to a surface, applying a metal layer (230) to the dielectric layer, and adding a cap layer (202) on the dielectric layer. The method also includes forming a magnetic tunnel junction (MTJ) stack (206) such that an electrode (210) of the MTJ stack is disposed on the metal layer and the cap layer contacts a side portion (232) of the metal layer. An adjustable depth to via may connect a top electrode of the MTJ stack to a top metal.
摘要翻译：在特定实施例中，形成磁性隧道结（MTJ）器件（200）的方法包括将电介质层（240）施加到表面，将金属层（230）施加到电介质层上，并且添加覆盖层 202）。该方法还包括形成磁隧道结（MTJ）堆叠（206），使得MTJ堆叠的电极（210）设置在金属层上，盖层接触金属层的侧部（232）。通孔的可调节深度可将MTJ叠层的顶部电极连接到顶部金属。

5. 发明申请

WO2010021981A1 CAPACITIVE MEMS-BASED DISPLAY WITH TOUCH POSITION SENSING 审中-公开
标题翻译：具有触摸位置感测功能的基于MEMS的电容显示器
公开(公告)号：WO2010021981A1
公开(公告)日：2010-02-25
申请号：PCT/US2009/054031
申请日：2009-08-17
申请人： QUALCOMM INCORPORATED , GU, Shiqun , NOWAK, Matthew
发明人： GU, Shiqun , NOWAK, Matthew
IPC分类号： G06F3/041
CPC分类号： G06F3/0412 , G06F3/044
摘要： A micro-electro-mechanical systems (MEMS) pixel for display and touch position sensing includes a substrate and a capacitive element. The capacitive element includes one or more pixels having a first conductive platelet above the substrate, and a second conductive platelet above and spaced apart from the first conductive platelet, the two platelets forming the capacitive element. A connection to each platelet provides for applying a voltage, wherein the platelet separation changes according to the applied voltage. A transparent dielectric plate, spaced apart from and positioned opposite the substrate, covers the at least one pixel. A capacitance sensing circuit attached to the connection to each platelet of the pixel senses changes in capacitance not resulting from the applied voltage.
摘要翻译：用于显示和触摸位置感测的微电子机械系统（MEMS）像素包括基板和电容元件。电容元件包括一个或多个像素，其具有在衬底上方的第一导电片，以及在第一导电片上方并与第一导电片形成间隔开的第二导电片，所述两片片形成电容元件。与每个血小板的连接提供施加电压，其中血小板分离根据所施加的电压而改变。与衬底间隔开并与衬底相对设置的透明电介质板覆盖至少一个像素。连接到与像素的每个血小板的连接的电容感测电路感测不是由施加电压引起的电容变化。

6. 发明申请

WO2010019889A1 CORROSION CONTROL OF STACKED INTEGRATED CIRCUITS 审中-公开
标题翻译：堆叠集成电路的腐蚀控制
公开(公告)号：WO2010019889A1
公开(公告)日：2010-02-18
申请号：PCT/US2009/053895
申请日：2009-08-14
申请人： QUALCOMM INCORPORATED , GU, Shiqun , NOWAK, Matthew
发明人： GU, Shiqun , NOWAK, Matthew
IPC分类号： H01L23/10 , H01L25/065 , H01L23/20
CPC分类号： H01L25/0657 , H01L25/50 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/056 , H01L2224/13025 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A system and method prevent corrosive elements (or at- least the oxidizing agent) from making contact with metal connections at the interface between two layers of a stacked IC device (10). When layers are positioned in proximity to each other, a cavity is formed at the boundary of the planar surfaces of the layers. This cavity is bounded by a peripheral seal (110/113) between the layers. In one embodiment, a vacuum is created within the cavity thereby reducing the corrosive atmosphere within the cavity. In another embodiment, the cavity is filled with an inert gas, such as argon. Once the cavity has oxidizing elements reduced, the peripheral seal (110/113) can be encapsulated to prevent seepage of contaminants into the cavity.
摘要翻译：一种系统和方法可以防止腐蚀性元素（或至少是氧化剂）在层叠的IC器件（10）的两层之间的界面处与金属连接接触。当层彼此靠近地定位时，在层的平面表面的边界处形成空腔。该空腔由层之间的周边密封（110/113）限定。在一个实施例中，在空腔内产生真空，从而减小空腔内的腐蚀性气氛。在另一个实施例中，空腔填充惰性气体，例如氩气。一旦空腔的氧化元素减少，外围密封件（110/113）就可以被包封，以防止污染物渗入空腔。

7. 发明申请

WO2010011448A2 PREDICTIVE MODELING OF INTERCONNECT MODULES FOR ADVANCED ON-CHIP INTERCONNECT TECHNOLOGY 审中-公开
标题翻译：用于高级片上互连技术的互连模块的预测建模
公开(公告)号：WO2010011448A2
公开(公告)日：2010-01-28
申请号：PCT/US2009/047668
申请日：2009-06-17
申请人： QUALCOMM INCORPORATED , LI, Xia , ZHAO, Wei , CAO, Yu , GU, Shiqun , KANG, Seung, H. , NOWAK, Matthew
发明人： LI, Xia , ZHAO, Wei , CAO, Yu , GU, Shiqun , KANG, Seung, H. , NOWAK, Matthew
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A computer program product estimates performance of an interconnect structure of a semiconductor integrated circuit (IC). The program product includes code executing on a computer to calculate at least one electrical characteristic of the interconnect structure based on input data accounting for multiple layers of the interconnect structure. The electrical characteristics can be capacitance, resistance, and/or inductance. The capacitance may be based upon multiple components, including a fringe capacitance component, a terminal capacitance component, and a coupling capacitance component.
摘要翻译：计算机程序产品估计半导体集成电路（IC）的互连结构的性能。程序产品包括在计算机上执行的代码，用于基于考虑到互连结构的多层的输入数据来计算互连结构的至少一个电特性。电气特性可以是电容，电阻和/或电感。电容可以基于多个分量，包括边缘电容分量，端子电容分量和耦合电容分量。

8. 发明申请

WO2009158287A1 ACTIVE THERMAL CONTROL FOR STACKED IC DEVICES 审中-公开
标题翻译：堆叠IC器件的主动热控制
公开(公告)号：WO2009158287A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/048031
申请日：2009-06-19
申请人： QUALCOMM INCORPORATED , GU, Shiqun , NOWAK, Matthew , TOMS, Thomas R.
发明人： GU, Shiqun , NOWAK, Matthew , TOMS, Thomas R.
IPC分类号： H01L25/065 , H01L23/38
CPC分类号： H05K7/20 , H01L23/38 , H01L25/0657 , H01L2224/05571 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06589 , H01L2924/00014 , H01L2224/05599
摘要： Thermal conductivity in a stacked IC device (30) can be improved by constructing one or more active temperature control devices within the stacked IC device. In one embodiment, the control devices are thermal electric (TE) devices, such as Peltier devices. The TE devices (300) can then be selectively controlled to remove or add heat, as necessary, to maintain the stacked IC device within a defined temperature range. The active temperature control elements can be P-N junctions (301, 302) created in the stacked IC device and can serve to move the heat laterally and/or vertically, as desired.
摘要翻译：通过在堆叠的IC器件内构造一个或多个有源温度控制器件，可以提高层叠IC器件（30）中的导热性。在一个实施例中，控制装置是诸如珀耳帖装置之类的热电（TE）装置。然后可根据需要选择性地控制TE器件（300）以去除或加热，以将堆叠的IC器件保持在规定的温度范围内。有源温度控制元件可以是在堆叠的IC器件中产生的P-N结（301,302），并且可以根据需要用于横向和/或垂直地移动热量。

9. 发明申请

WO2011044392A1 THREE DIMENSIONAL INDUCTOR AND TRANSFORMER 审中-公开
标题翻译：三维电感和变压器
公开(公告)号：WO2011044392A1
公开(公告)日：2011-04-14
申请号：PCT/US2010/051868
申请日：2010-10-07
申请人： QUALCOMM Incorporated , KIM, Jonghae , GU, Shiqun , HENDERSON, Brian Matthew , TOMS, Thomas R. , CHUA-EOAN, Lew G. , BAZARJANI, Seyfollah S. , NOWAK, Matthew
发明人： KIM, Jonghae , GU, Shiqun , HENDERSON, Brian Matthew , TOMS, Thomas R. , CHUA-EOAN, Lew G. , BAZARJANI, Seyfollah S. , NOWAK, Matthew
IPC分类号： H01L21/02 , H01L23/522 , H01F17/00 , H01L27/06 , H01L23/48
CPC分类号： H01L28/10 , H01F17/0013 , H01F19/04 , H01F2017/002 , H01L23/481 , H01L23/5227 , H01L27/0207 , H01L2224/16145 , H01L2924/3011
摘要： A three dimensional on-chip inductor, transformer and radio frequency amplifier are disclosed. The radio frequency amplifier includes a pair of transformers and a transistor. The transformers include at least two inductively coupled inductors. The inductors include a plurality of segments (704) of a first metal layer, a plurality of segments (706) of a second metal layer, a first inductor input (708) a second inductor input (710) and a plurality of through silicon vias (702) coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input. The inductors can have a symmetric or asymmetric geometry. The first metal layer can be a metal layer in the back-end-of-line section of the chip. The second metal layer can be located in the redistributed design layer of the chip
摘要翻译：公开了三维片上电感器，变压器和射频放大器。射频放大器包括一对变压器和晶体管。变压器包括至少两个电感耦合电感器。电感器包括第一金属层的多个段（704），第二金属层的多个段（706），第一电感器输入端（708），第二电感器输入端（710）和多个通孔硅通孔（702），耦合所述第一金属层的所述多个段和所述第二金属层的所述多个段，以在所述第一电感器输入和所述第二电感器输入之间形成连续的，不相交的路径。电感器可以具有对称或不对称的几何形状。第一金属层可以是芯片的后端部分中的金属层。第二金属层可以位于芯片的再分布设计层中

10. 发明申请

WO2010135572A3 METHOD AND APPARATUS FOR PROVIDING THROUGH SILICON VIA (TSV) REDUNDANCY 审中-公开
公开(公告)号：WO2010135572A3
公开(公告)日：2010-11-25
申请号：PCT/US2010/035646
申请日：2010-05-20
申请人： QUALCOMM INCORPORATED , KIM, Jonghae , WANG, Feng , NOWAK, Matthew
发明人： KIM, Jonghae , WANG, Feng , NOWAK, Matthew
IPC分类号： H01L21/768 , H01L21/3205
摘要： An apparatus includes a first die having a first bus, a second die having a second bus stacked on the first die, a plurality of through silicon vias connecting the first bus to the second bus, and first control logic for sending data to indentified ones of the plurality of through silicon vias. Also, optionally, second control logic for determining a first set of the plurality of through silicon vias that are nonfunctional, wherein the second control logic is configured to send information to the first control logic identifying the first set of the plurality of through silicon vias or identifying a second set of through silicon vias that are functional. Also a method of sending signals through a plurality of through silicon vias.

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