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1. 发明申请

WO2010151894A1 FEEDBACK SYSTEM WITH IMPROVED STABILITY 审中-公开
标题翻译：反馈系统具有改进的稳定性
公开(公告)号：WO2010151894A1
公开(公告)日：2010-12-29
申请号：PCT/US2010/040252
申请日：2010-06-28
申请人： QUALCOMM Incorporated , APARIN, Vladimir , BALLANTYNE, Gary, John
发明人： APARIN, Vladimir , BALLANTYNE, Gary, John
IPC分类号： H04B1/04
CPC分类号： H04B1/0475
摘要： Techniques for improving stability of a feedback system are described. In an exemplary design, the feedback system includes a forward path and a feedback path. The forward path receives an input signal and a rotated feedback signal and provides an output signal having a phase shift. The feedback path receives the output signal, generates a feedback signal, and rotates the feedback signal to obtain the rotated feedback signal having at least part of the phase shift removed. In another exemplary design, the feedback system includes a forward path and a feedback loop. The forward path receives a combined signal and provides an output signal having a phase shift. The feedback loop generates an error signal based on an input signal and the output signal, generates the combined signal based on the error signal and the input signal, and performs phase rotation to remove at least part of the phase shift.
摘要翻译：描述了提高反馈系统稳定性的技术。在示例性设计中，反馈系统包括前向路径和反馈路径。正向路径接收输入信号和旋转的反馈信号，并提供具有相移的输出信号。反馈路径接收输出信号，产生反馈信号，并且使反馈信号旋转以获得具有至少部分移相消除的旋转的反馈信号。在另一示例性设计中，反馈系统包括前向路径和反馈回路。前向路径接收组合信号并提供具有相移的输出信号。反馈回路基于输入信号和输出信号产生误差信号，基于误差信号和输入信号产生组合信号，并执行相位旋转以去除至少部分相移。

2. 发明申请

WO2006068635A1 ADAPTIVE FILTER FOR TRANSMIT LEAKAGE SIGNAL REJECTION 审中-公开
标题翻译：用于传输泄漏信号的自适应滤波器
公开(公告)号：WO2006068635A1
公开(公告)日：2006-06-29
申请号：PCT/US2004/038343
申请日：2004-11-15
申请人： QUALCOMM INCORPORATED , APARIN, Vladimir , BALLANTYNE, Gary, John , PERSICO, Charles, J.
发明人： APARIN, Vladimir , BALLANTYNE, Gary, John , PERSICO, Charles, J.
IPC分类号： H04B1/52
CPC分类号： H04B1/525
摘要： An adaptive filter suitable for fabrication on an RF integrated circuit and used for transmit (TX) leakage rejection in a wireless full-duplex communication system is described. The adaptive filter includes a summer and an adaptive estimator. The summer receives an input signal having a TX leakage signal and an estimator signal having an estimate of the TX leakage signal, subtracts the estimator signal from the input signal, and provides an output signal having the TX leakage signal attenuated. The adaptive estimator receives the output signal and a reference signal having a version of the transmit signal, estimates the TX leakage signal in the input signal based on the output signal and the reference signal, and provides the estimator signal. The adaptive estimator may utilize an LMS algorithm to minimize a mean square error between the TX leakage signal in the input signal and the TX leakage signal estimate in the estimator signal.
摘要翻译：描述了适用于在RF集成电路上制造并用于无线全双工通信系统中的发射（TX）泄漏抑制的自适应滤波器。自适应滤波器包括一个加法器和一个自适应估计器。夏天接收具有TX泄漏信号的输入信号和具有TX泄漏信号的估计的估计信号，从输入信号中减去估计器信号，并且提供具有衰减的TX泄漏信号的输出信号。自适应估计器接收输出信号和具有发射信号版本的参考信号，基于输出信号和参考信号估计输入信号中的TX泄漏信号，并提供估计器信号。自适应估计器可以利用LMS算法来最小化输入信号中的TX泄漏信号与估计器信号中的TX泄漏信号估计之间的均方误差。

3. 发明申请

WO2010151557A1 METHOD AND APPARATUS FOR USING PRE-DISTORTION AND FEEDBACK TO MITIGATE NONLINEARITY OF CIRCUITS 审中-公开
标题翻译：使用预失真和反馈来减轻电路非线性的方法和装置
公开(公告)号：WO2010151557A1
公开(公告)日：2010-12-29
申请号：PCT/US2010/039553
申请日：2010-06-22
申请人： QUALCOMM Incorporated , APARIN, Vladimir , BALLANTYNE, Gary, John
发明人： APARIN, Vladimir , BALLANTYNE, Gary, John
IPC分类号： H03F1/32 , H03F1/34
CPC分类号： H03F1/34 , H03F1/3258
摘要： Techniques for mitigating nonlinearity of circuits with both pre-distortion and feedback are described. An apparatus may include at least one circuit (e.g., an upconverter, a power amplifier, etc.), a pre-distortion circuit, and a feedback circuit. The circuit(s) may generate an output signal having distortion components due to their nonlinearity. The pre-distortion circuit may receive an input signal and generate a pre-distorted signal based on at least one coefficient determined by the nonlinearity of the circuit(s). The pre-distortion circuit may adaptively determine the coefficient(s) based on the input signal and an error signal. The feedback circuit may generate the error signal based on the input signal and the output signal and may filter the error signal to obtain a filtered error signal. The circuit(s) may process the pre-distorted signal and the filtered error signal to generate the output signal, which may have attenuated distortion components due to pre-distortion and feedback.
摘要翻译：描述了减轻预失真和反馈的电路非线性的技术。装置可以包括至少一个电路（例如，上变频器，功率放大器等），预失真电路和反馈电路。电路可以由于它们的非线性而产生具有失真分量的输出信号。预失真电路可以接收输入信号，并且基于由电路的非线性确定的至少一个系数产生预失真信号。预失真电路可以基于输入信号和误差信号自适应地确定系数。反馈电路可以基于输入信号和输出信号产生误差信号，并且可以对误差信号进行滤波以获得滤波后的误差信号。电路可以处理预失真信号和滤波后的误差信号以产生输出信号，其可能由于预失真和反馈而具有衰减的失真分量。

4. 发明申请

WO2009094398A1 THRESHOLD DITHERING FOR TIME-TO-DIGITAL CONVERTERS 审中-公开
标题翻译：用于数字时间转换器的阈值
公开(公告)号：WO2009094398A1
公开(公告)日：2009-07-30
申请号：PCT/US2009/031595
申请日：2009-01-21
申请人： QUALCOMM INCORPORATED , BALLANTYNE, Gary, John
发明人： BALLANTYNE, Gary, John
IPC分类号： H03L7/091
CPC分类号： H03L7/091 , G04F10/005 , H03L2207/50
摘要： Techniques for dithering quantization thresholds of time-to-digital converters (TDC's) in all-digital phase-locked loops (ADPLL's) are disclosed. In an embodiment, the delay introduced by an individual buffer in a TDC delay line may be dithered. In another embodiment, the delay associated with the TDC delay line may be extended by a fixed amount to accommodate dithering of the zero-delay threshold.
摘要翻译：公开了用于在全数字锁相环（ADPLL）中抖动时 - 数转换器（TDC）的量化阈值的技术。在一个实施例中，由TDC延迟线中的单个缓冲器引入的延迟可以是抖动的。在另一个实施例中，与TDC延迟线相关联的延迟可以扩展固定的量以适应零延迟阈值的抖动。

5. 发明申请

WO2010068679A2 DIGITAL PHASE-LOCKED LOOP WITH TWO-POINT MODULATION AND ADAPTIVE DELAY MATCHING 审中-公开
标题翻译：具有两点调制和自适应延迟匹配的数字相位锁定环
公开(公告)号：WO2010068679A2
公开(公告)日：2010-06-17
申请号：PCT/US2009/067354
申请日：2009-12-09
申请人： QUALCOMM Incorporated , GENG, Jifeng , BALLANTYNE, Gary, John , FILIPOVIC, Daniel, F.
发明人： GENG, Jifeng , BALLANTYNE, Gary, John , FILIPOVIC, Daniel, F.
IPC分类号： H03L7/06
CPC分类号： H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0966
摘要： A digital phase-locked loop (DPLL) supporting two-point modulation with adaptive delay matching is described. The DPLL includes highpass and lowpass modulation paths that support wideband and narrowband modulation, respectively, of the frequency and/or phase of an oscillator. The DPLL can adaptively adjust the delay of one modulation path to match the delay of the other modulation path. In one design, the DPLL includes an adaptive delay unit that provides a variable delay for one of the two modulation paths. Within the adaptive delay unit, a delay computation unit determines the variable delay based on a modulating signal applied to the two modulation paths and a phase error signal in the DPLL. An interpolator provides a fractional portion of the variable delay, and a programmable delay unit provides an integer portion of the variable delay.
摘要翻译：描述了支持具有自适应延迟匹配的两点调制的数字锁相环（DPLL）。 DPLL包括分别支持振荡器的频率和/或相位的宽带和窄带调制的高通和低通调制路径。 DPLL可以自适应地调整一个调制路径的延迟以匹配另一个调制路径的延迟。在一种设计中，DPLL包括为两个调制路径中的一个提供可变延迟的自适应延迟单元。在自适应延迟单元内，延迟计算单元基于施加到两个调制路径的调制信号和DPLL中的相位误差信号来确定可变延迟。内插器提供可变延迟的小数部分，并且可编程延迟单元提供可变延迟的整数部分。

6. 发明申请

WO2007092921A1 ADAPTIVE RECEIVER FOR WIRELESS COMMUNICATION DEVICE 审中-公开
标题翻译：无线通信设备的自适应接收机
公开(公告)号：WO2007092921A1
公开(公告)日：2007-08-16
申请号：PCT/US2007/061838
申请日：2007-02-08
申请人： QUALCOMM Incorporated , BALLANTYNE, Gary, John
发明人： BALLANTYNE, Gary, John
IPC分类号： H04B1/16
CPC分类号： H04B1/109 , H04W52/0245 , Y02D70/1222 , Y02D70/1242 , Y02D70/144 , Y02D70/164 , Y02D70/40
摘要： In general, the disclosure is directed to techniques for combining a high performance receiver and a low power receiver within a wireless communication device (WCD) to reduce power consumption. Upon receiving a signal from a base station, a controller within the WCD detects one or more channel conditions of a radio frequency (RF) environment between the base station and the WCD. The controller selects a high performance receiver to process the received signal when the RF environment is unfavorable and selects a low power receiver to process the received signal when the RF environment is favorable. In this manner, the WCD implements an adaptive receiver that adapts its receiver structure according to RF channel conditions.
摘要翻译：通常，本公开涉及用于组合无线通信设备（WCD）内的高性能接收机和低功率接收机以降低功耗的技术。在接收到来自基站的信号之后，WCD内的控制器检测基站和WCD之间的射频（RF）环境的一个或多个信道条件。当RF环境不利时，控制器选择高性能接收机来处理接收信号，并且当RF环境有利时选择低功率接收机来处理接收信号。以这种方式，WCD实现了根据RF信道条件来适应其接收机结构的自适应接收机。

7. 发明申请

WO2007025030A1 A PHASE LOCKED LOOP SYSTEM HAVING LOCKING AND TRACKING MODES OF OPERATION 审中-公开
标题翻译：具有锁定和跟踪操作模式的相位锁定环路系统
公开(公告)号：WO2007025030A1
公开(公告)日：2007-03-01
申请号：PCT/US2006/033055
申请日：2006-08-23
申请人： QUALCOMM Incorporated , BALLANTYNE, Gary, John , SAHOTA, Gurkanwal, Singh
发明人： BALLANTYNE, Gary, John , SAHOTA, Gurkanwal, Singh
IPC分类号： H03L7/107 , H03L7/093
CPC分类号： H03L7/107 , H03L7/093
摘要： An embodiment pertains to a phase locked loop (PLL) circuit. The PLL includes a voltage controlled oscillator which outputs a signal at a desired frequency. A phase detector is coupled to an output from the voltage controlled oscillator. The phase detector compares the phase of a signal output from the voltage controlled oscillator (VCO) with the phase of a reference signal. A loop filter is coupled to the VCO and the phase detector. The loop filter has a locking mode of operation for locking the phase of the VCO signal to the phase of the reference signal. The loop filter can subsequently be placed in a tracking mode of operation which adjusts the phase of the VCO signal to track the phase of the reference signal.
摘要翻译：实施例涉及锁相环（PLL）电路。 PLL包括以期望频率输出信号的压控振荡器。相位检测器耦合到压控振荡器的输出。相位检测器将从压控振荡器（VCO）输出的信号的相位与参考信号的相位进行比较。环路滤波器耦合到VCO和相位检测器。环路滤波器具有用于将VCO信号的相位锁定到参考信号的相位的锁定操作模式。随后可以将环路滤波器置于跟踪操作模式中，该操作模式调整VCO信号的相位以跟踪参考信号的相位。

8. 发明申请

WO2009152106A2 DITHERING A DIGITALLY-CONTROLLED OSCILLATOR OUTPUT IN A PHASE-LOCKED LOOP 审中-公开
标题翻译：在锁相环中摆动数字控制振荡器输出
公开(公告)号：WO2009152106A2
公开(公告)日：2009-12-17
申请号：PCT/US2009/046643
申请日：2009-06-08
申请人： QUALCOMM INCORPORATED , BALLANTYNE, Gary, John
发明人： BALLANTYNE, Gary, John
IPC分类号： H03L7/099
CPC分类号： H03L7/099 , H03L2207/50 , H04B1/69
摘要： A digitally-controlled oscillator (DCO) of a PLL is dithered such that a DCO_OUT signal has a frequency that changes at dithered intervals. In one example, the DCO receives an undithered stream of incoming digital tuning words, and receives a dithered reference clock signal REFD, and outputs the DCO_OUT signal such that its frequency changes occur at dithered intervals. Where the PLL is employed in the local oscillator of a cellular telephone transmitter, the novel dithering of the DCO spreads digital image noise out in frequency such that less digital image noise is present at a particular frequency offset from the main local oscillator frequency. Spreading digital image noise out in frequency allows a noise specification to be met without having to increase the frequency of the PLL reference clock. By avoiding increasing the frequency of the reference clock to meet the noise specification, increases in power consumption are avoided.
摘要翻译： PLL的数字控制振荡器（DCO）抖动，使得DCO_OUT信号具有在抖动间隔处变化的频率。在一个示例中，DCO接收输入的数字调谐字的未传输流，并接收抖动参考时钟信号REFD，并输出DCO_OUT信号，使得其频率变化以抖动间隔发生。在蜂窝电话发射机的本地振荡器中使用PLL的情况下，DCO的新颖抖动以频率扩展数字图像噪声，使得在与主本地振荡器频率偏移的特定频率处存在较少的数字图像噪声。以频率扩展数字图像噪声允许满足噪声规范，而不必增加PLL参考时钟的频率。通过避免增加参考时钟的频率以满足噪声规范，避免了功耗的增加。

9. 发明申请

WO2009039444A1 MULTI-MODE AND MULTI-BAND TRANSMITTERS FOR WIRELESS COMMUNICATION 审中-公开
标题翻译：用于无线通信的多模和多带发射机
公开(公告)号：WO2009039444A1
公开(公告)日：2009-03-26
申请号：PCT/US2008/077121
申请日：2008-09-19
申请人： QUALCOMM INCORPORATED , SEE, Puay Hoe Andrew , SAHOTA, Gurkanwal Singh , SUN, Bo , BALLANTYNE, Gary, John , PANTON, William, Ronald , CHOI, Zae Yong
发明人： SEE, Puay Hoe Andrew , SAHOTA, Gurkanwal Singh , SUN, Bo , BALLANTYNE, Gary, John , PANTON, William, Ronald , CHOI, Zae Yong
IPC分类号： H04L27/00 , H04L27/36 , H04B1/00
CPC分类号： H04L27/0008 , H03C3/0916 , H03C3/0975 , H03C5/00 , H03F1/3241 , H03F1/3252 , H04B1/0483 , H04B2001/0425 , H04L27/361 , H04L27/362
摘要： Transmitters supporting multiple modulation modes and/or multiple frequency bands are described. A transmitter may perform large signal polar modulation, small signal polar modulation, and/or quadrature modulation, which may support different modulation schemes and systems. Circuit blocks may be shared by the different modulation modes to reduce cost and power. For example, a single modulator (160) and a single power amplifier (170) may be used for small signal polar modulation and quadrature modulation. The transmitter may apply pre-distortion (124,142) to improve performance, to allow a power amplifier to support multiple frequency bands, to allow the power amplifier to operate at higher output power levels, etc. Envelope and phase distortions due to non-linearity of the power amplifier may be characterized for different input levels and different bands and stored at the transmitter. Thereafter, envelope and phase signals may be pre-distorted based on the stored characterizations to compensate for non-linearity of the power amplifier.
摘要翻译：描述了支持多个调制模式和/或多个频带的发射机。发射机可以执行大信号极性调制，小信号极化调制和/或正交调制，其可以支持不同的调制方案和系统。电路块可以由不同的调制模式共享以降低成本和功率。例如，单个调制器（160）和单个功率放大器（170）可用于小信号极性调制和正交调制。发射机可以应用预失真（124,142）来提高性能，以允许功率放大器支持多个频带，以允许功率放大器在较高的输出功率电平下工作等。由于非线性的包络和相位失真功率放大器可以被表征为不同的输入电平和不同的频带并存储在发射机。此后，包络和相位信号可以基于存储的特征来预失真，以补偿功率放大器的非线性。

10. 发明申请

WO2010141909A1 DIGITAL PHASE LOCKED LOOP WITH PARTS OPERATING AT DIFFERENT SAMPLE RATES 审中-公开
标题翻译：数字相位锁定环与不同采样率的零件操作
公开(公告)号：WO2010141909A1
公开(公告)日：2010-12-09
申请号：PCT/US2010/037530
申请日：2010-06-04
申请人： QUALCOMM Incorporated , BALLANTYNE, Gary, John , GENG, Jifeng , FILIPOVIC, Daniel, F.
发明人： BALLANTYNE, Gary, John , GENG, Jifeng , FILIPOVIC, Daniel, F.
IPC分类号： H03L7/08 , H03C3/09
CPC分类号： H03L7/08 , H03C3/0941 , H03C3/095 , H03C3/0966 , H03L2207/50
摘要： A Digital Phase-Locked Loop (DPLL) involves a Time-to-Digital Converter (TDC) that receives a DCO output signal and a reference clock and outputs a first stream of digital values. Quantization noise is reduced by clocking the TDC at a high rate. Downsampling circuitry converts the first stream into a second stream. The second stream is supplied to a phase detecting summer of the DPLL such that a control portion of the DPLL can switch at a lower rate to reduce power consumption. The DPLL is therefore referred to as a multi-rate DPLL. A third stream of digital tuning words output by the control portion is upsampled before being supplied to the DCO so that the DCO can be clocked at the higher rate, thereby reducing digital images. In a receiver application, no upsampling is performed and the DCO is clocked at the lower rate, thereby further reducing power consumption.
摘要翻译：数字锁相环（DPLL）涉及一个时间数字转换器（TDC），它接收DCO输出信号和参考时钟并输出第一个数字值。通过以较高的速率计时TDC来减少量化噪声。下采样电路将第一流转换为第二流。第二流被提供给DPLL的相位检测加法器，使得DPLL的控制部分可以以较低的速率切换以降低功耗。因此，DPLL被称为多速率DPLL。由控制部分输出的第三个数字调谐字流在被提供给DCO之前被上采样，从而可以以更高的速率计时DCO，从而减少数字图像。在接收机应用中，不执行上采样，并且以较低的速率对DCO进行计时，从而进一步降低功耗。

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