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1. 发明申请

WO2016164270A1 SYSTEM, APPARATUS, AND METHOD FOR SENSE AMPLIFIERS 审中-公开
标题翻译：用于感应放大器的系统，装置和方法
公开(公告)号：WO2016164270A1
公开(公告)日：2016-10-13
申请号：PCT/US2016/025594
申请日：2016-04-01
申请人： QUALCOMM INCORPORATED , INDUSTRY-ACADEMIC COOPERATION FOUNDATION; YONSEI UNIVERSITY
发明人： JUNG, Seong-Ook , NA, Taehui , KIM, Jisu , KIM, Jung Pill , KANG, Seung Hyuk
IPC分类号： G11C7/06 , G11C11/16 , G11C13/00
CPC分类号： G11C7/08 , G11C5/10 , G11C7/062 , G11C7/12 , G11C7/14 , G11C11/1673 , G11C13/004 , G11C16/28 , G11C2013/0042 , G11C2013/0054 , H03F3/45179 , H03F3/45775 , H03F2203/45212
摘要： An offset cancelling sense amplifier according to some examples of the disclosure may use a double sensing margin structure and positive feedback to achieve better performance characteristics and read stability without a multistage operation. For example, a sense amplifier may include a second pair of sensing switches cross coupled in parallel with a first pair of sensing switches and a pair of degeneration transistors coupled in line before a pair of load transistors.
摘要翻译：根据本公开的一些示例的偏移消除读出放大器可以使用双重感测余量结构和正反馈来实现更好的性能特征和读取稳定性而不需要多级操作。例如，读出放大器可以包括与第一对感测开关并联耦合的第二对感测开关和一对在一对负载晶体管之前串联耦合的退化晶体管。

2. 发明申请

WO2016149140A1 SYSTEMS AND METHODS TO REFRESH STORAGE ELEMENTS 审中-公开
标题翻译：系统和方法来刷新储存元素
公开(公告)号：WO2016149140A1
公开(公告)日：2016-09-22
申请号：PCT/US2016/022192
申请日：2016-03-11
申请人： QUALCOMM INCORPORATED
发明人： SAIFUDDIN, Mosaddiq , KIM, Jung Pill
IPC分类号： G11C11/406 , G11C11/408
CPC分类号： G11C11/406 , G11C11/40611 , G11C11/40618 , G11C11/40622 , G11C11/408 , G11C11/4087 , G11C11/4096 , G11C2211/4061
摘要： A method of performing refresh operations on a storage device includes identifying word lines coupled to weak storage elements. The method also includes grouping a plurality of word lines having distinct bank offsets onto a single refresh address. Each of the plurality of word lines is coupled to a corresponding weak storage element. The method further includes performing a refresh of the single refresh address.
摘要翻译：在存储设备上执行刷新操作的方法包括识别耦合到弱存储元件的字线。该方法还包括将具有不同的组偏移的多个字线分组到单个刷新地址上。多个字线中的每一个耦合到相应的弱存储元件。该方法还包括执行单个刷新地址的刷新。

3. 发明申请

WO2016048662A1 READ OPERATION OF CACHE MRAM USING A REFERENCE WORD LINE 审中-公开
标题翻译：使用参考线读取高速缓存MRAM的操作
公开(公告)号：WO2016048662A1
公开(公告)日：2016-03-31
申请号：PCT/US2015/049229
申请日：2015-09-09
申请人： QUALCOMM INCORPORATED
发明人： KIM, Taehyun , KIM, Sungryul , KIM, Jung Pill , DONG, Xiangyu
IPC分类号： G11C11/16 , G06F12/08
CPC分类号： G11C11/1673 , G11C11/161 , G11C11/1693
摘要： Systems and methods relate to a read operation on a magnetoresistive random access memory (MRAM) coupled with a tag array, the method comprising: receiving an index and a tag; based on the index, accessing n memory locations in the tag array and for each of the accessed n memory locations comparing data stored therein with the received tag; based on the index, activating a dummy word line in the MRAM; after the activation of the dummy word line, generating a hit signal associated with one of the n memory locations if the comparing indicates a match for said one of the n memory locations; in response to the activation of the dummy word line obtaining a settled reference voltage for reading MRAM bit cells of the MRAM designated by the index; among the MRAM cells designated by the index, reading the MRAM cells having a memory location corresponding to the one of the n-memory location in the tag array providing said hit signal, the reading using the settled reference voltage.
摘要翻译：系统和方法涉及与标签阵列耦合的磁阻随机存取存储器（MRAM）上的读取操作，该方法包括：接收索引和标签; 基于所述索引，访问所述标签阵列中的n个存储器位置以及对于存储在其中的数据与所接收的标签的所访问的n个存储器单元中的每一个; 基于索引，激活MRAM中的虚拟字线; 在所述虚拟字线的激活之后，如果所述比较指示所述n个存储器位置中的所述一个存储器位置的匹配，则产生与所述n个存储器位置之一相关联的命中信号; 响应于所述伪字线的激活获得用于读取由所述索引指定的MRAM的MRAM位单元的稳定参考电压; 在由索引指定的MRAM单元中，读取具有对应于提供所述命中信号的标签阵列中的n个存储器位置之一的存储器位置的MRAM单元，该读取使用稳定的参考电压。

4. 发明申请

WO2015163979A1 METHOD AND APPARATUS FOR GENERATING A REFERENCE FOR USE WITH A MAGNETIC TUNNEL JUNCTION 审中-公开
标题翻译：用于产生用于具有磁性隧道结的参考的方法和装置
公开(公告)号：WO2015163979A1
公开(公告)日：2015-10-29
申请号：PCT/US2015/018288
申请日：2015-03-02
申请人： QUALCOMM INCORPORATED
发明人： KIM, Sungryul , KIM, Taehyun , KIM, Jung Pill
IPC分类号： G11C7/14 , G11C11/16
CPC分类号： G11C11/1673 , G11C7/14 , G11C11/1659
摘要： Methods and apparatus for generating a reference for use with a magnetic tunnel junction are provided. In an example, provided is a magnetoresistive read only memory including a magnetic tunnel junction (MTJ) storage element, a sense amplifier having a first input coupled to the MTJ storage element, and a reference resistance device coupled to a second input of the sense amplifier. The reference resistance device includes a plurality of groups of at least two reference MTJ devices. Each reference MTJ device in a respective group is coupled in parallel with each other reference MTJ device in the respective group. Each group is coupled in series with the other groups. This arrangement advantageously mitigates read disturbances and reference level variations, while saving power, reducing reference resistance device area, and increasing read speed.
摘要翻译：提供了用于产生用于磁性隧道结的参考的方法和装置。在一个例子中，提供了一种包括磁性隧道结（MTJ）存储元件的磁阻只读存储器，具有耦合到MTJ存储元件的第一输入的读出放大器和耦合到读出放大器的第二输入的参考电阻器件。参考电阻装置包括多组至少两个参考MTJ装置。相应组中的每个参考MTJ设备与相应组中的每个其他参考MTJ设备并联耦合。每个组与其他组串联。这种布置有利于减轻读取干扰和参考电平变化，同时节省功率，减少参考电阻器件面积并增加读取速度。

5. 发明申请

WO2015077055A1 BIT RECOVERY SYSTEM 审中-公开
标题翻译：位恢复系统
公开(公告)号：WO2015077055A1
公开(公告)日：2015-05-28
申请号：PCT/US2014/064574
申请日：2014-11-07
申请人： QUALCOMM INCORPORATED
发明人： KIM, Taehyun , KIM, Jung Pill , KIM, Sungryul
IPC分类号： G06F11/10 , G06F12/00
CPC分类号： G06F11/102 , G06F11/1064 , G06F12/00
摘要： A particular device includes a resistance-based memory device, a tag random-access memory (RAM), and a bit recovery (BR) memory. The resistance-based memory device is configured to store a data value and error-correcting code (ECC) data associated with the data value. The tag RAM is configured to store information that maps memory addresses of a main memory to wordlines of a cache memory, where the cache memory includes the resistance-based memory device. The BR memory is configured to store additional error correction data associated with the data value, where the BR memory corresponds to a volatile memory device.
摘要翻译：特定设备包括基于电阻的存储器件，标签随机存取存储器（RAM）和位恢复（BR）存储器。基于电阻的存储器件被配置为存储与数据值相关联的数据值和纠错码（ECC）数据。标签RAM被配置为存储将主存储器的存储器地址映射到高速缓冲存储器的字线的信息，其中高速缓冲存储器包括基于电阻的存储器件。 BR存储器被配置为存储与数据值相关联的附加纠错数据，其中BR存储器对应于易失性存储器设备。

6. 发明申请

WO2015047809A3 METHOD AND APPARATUS FOR REFRESHING A MEMORY CELL 审中-公开
公开(公告)号：WO2015047809A3
公开(公告)日：2015-04-02
申请号：PCT/US2014/056001
申请日：2014-09-17
申请人： QUALCOMM INCORPORATED
发明人： DONG, Xiangyu , KIM, Jung Pill , SRIRAMAGIRI, Deepti Vijayalakshmi , SUH, Jungwon
IPC分类号： G06F13/16 , G11C7/04 , G11C11/406
摘要： Memory devices may send information related to refresh rates to a memory controller. The memory controller may instruct the memory devices to refresh based on the received information.

7. 发明申请

WO2015013023A2 SENSE AMPLIFIER OFFSET VOLTAGE REDUCTION 审中-公开
标题翻译：感应放大器偏置电压降低
公开(公告)号：WO2015013023A2
公开(公告)日：2015-01-29
申请号：PCT/US2014/045689
申请日：2014-07-08
申请人： QUALCOMM INCORPORATED
发明人： KIM, Jung Pill , KIM, Taehyun , KIM, Sungryul , KIM, Daeik D.
IPC分类号： G11C19/02
CPC分类号： G01R31/2851 , G11C16/28 , G11C29/02 , G11C29/026 , G11C29/028 , G11C29/14 , G11C29/44 , G11C29/46
摘要： A circuit includes a plurality of transistors responsive to a plurality of latches that store a test code. The circuit further includes a first bit line coupled to a data cell and coupled to a sense amplifier. The circuit also includes a second bit line coupled to a reference cell and coupled to the sense amplifier. A current from a set of the plurality of transistors is applied to the data cell via the first bit line. The set of the plurality of transistors is determined based on the test code. The circuit also includes a test mode reference circuit coupled to the first bit line and to the second bit line.
摘要翻译：电路包括响应于存储测试码的多个锁存器的多个晶体管。电路还包括耦合到数据单元并耦合到读出放大器的第一位线。电路还包括耦合到参考单元并耦合到读出放大器的第二位线。来自一组多个晶体管的电流经由第一位线被施加到数据单元。基于测试代码来确定多个晶体管的集合。电路还包括耦合到第一位线和第二位线的测试模式参考电路。

8. 发明申请

WO2014123824A1 METHOD AND APPARATUS FOR GENERATING RANDOM NUMBERS USING A PHYSICAL ENTROPY SOURCE 审中-公开
标题翻译：使用物理熵源产生随机数的方法和装置
公开(公告)号：WO2014123824A1
公开(公告)日：2014-08-14
申请号：PCT/US2014/014507
申请日：2014-02-03
申请人： QUALCOMM INCORPORATED
发明人： WU, Wenqing , WANG, Peiyuan , MADALA, Raghu Sagar , GOVINDASWAMY, Senthil Kumar , YUEN, Kendrick H. , GILMORE, Robert P. , KIM, Jung Pill , KANG, Seung H.
IPC分类号： G06F7/58
CPC分类号： G06F7/58 , G06F7/588
摘要： A method and apparatus for generating random binary sequences from a physical entropy source having a state A and a state B by detecting whether the physical entropy source is in the state A or in the state B, attempting to shift the state of the physical entropy source to the opposite state in a probabilistic manner with less than 100% certainty, and producing one of four outputs based on the detected state and the state of the physical entropy source before the attempted shift. The outputs are placed in first and second queues and extracted in pairs from each queue. Random binary bits are output based on the sequences extracted from each queue.
摘要翻译：一种用于通过检测物理熵源是处于状态A还是状态B从具有状态A和状态B的物理熵源生成随机二进制序列的方法和装置，试图将物理熵源的状态以小于100％确定性的概率方式向相反状态，并且在尝试移位之前基于检测到的状态和物理熵源的状态产生四个输出中的一个。将输出放置在第一和第二队列中，并从每个队列中成对提取。基于从每个队列提取的序列输出随机二进制位。

9. 发明申请

WO2014120529A1 ERROR DETECTION AND CORRECTION OF ONE-TIME PROGRAMMABLE ELEMENTS 审中-公开
标题翻译：一次性可编程元件的错误检测和校正
公开(公告)号：WO2014120529A1
公开(公告)日：2014-08-07
申请号：PCT/US2014/012539
申请日：2014-01-22
申请人： QUALCOMM INCORPORATED
发明人： KIM, Jung Pill , KIM, Taehyun , KIM, Sungryul
IPC分类号： G11C17/02 , G06F11/10 , G11C17/14 , G11C29/02 , G11C17/18
CPC分类号： G06F11/1048 , G11C11/16 , G11C17/02 , G11C17/146 , G11C17/18 , G11C29/027 , G11C2029/4402
摘要： A circuit includes a first one-time programmable (OTP) element and a second OTP element. The circuit also includes error detection circuitry coupled to receive a first representation of data from the first OTP element. The circuit further includes output circuitry responsive to an output of the error detection circuitry to output an OTP read result based on the first representation of the data or based on a second representation of the data from the second OTP element.
摘要翻译：电路包括第一个一次性可编程（OTP）元件和第二个OTP元件。电路还包括耦合以从第一OTP元件接收数据的第一表示的错误检测电路。电路还包括响应于错误检测电路的输出的输出电路，以基于数据的第一表示或基于来自第二OTP元件的数据的第二表示来输出OTP读取结果。

10. 发明申请

WO2014043575A1 OTP SCHEME WITH MULTIPLE MAGNETIC TUNNEL JUNCTION DEVICES IN A CELL 审中-公开
标题翻译： OTP方案与细胞中的多个磁性隧道连接装置
公开(公告)号：WO2014043575A1
公开(公告)日：2014-03-20
申请号：PCT/US2013/059809
申请日：2013-09-13
申请人： QUALCOMM INCORPORATED
发明人： KIM, Jung Pill , KIM, Taehyun , KIM, Sungryul , LEE, Kangho
IPC分类号： G11C11/16 , G11C17/02 , G11C17/16
CPC分类号： G11C11/1675 , G11C11/161 , G11C11/1673 , G11C17/02 , G11C17/146 , G11C17/165 , G11C2213/78
摘要： A one time programming (OTP) apparatus unit cell includes multiple magnetic tunnel junctions (MTJs) and a shared access transistor coupled between the multiple MTJs and a fixed potential. Each of the multiple MTJs in a unit cell can be coupled to separate programming circuitry and/or separate sense amplifier circuitry so that they can be individually programmed and/or individually sensed. A logical combination from the separate sense amplifiers can be generated as an output of the unit cell.
摘要翻译：一次编程（OTP）装置单元包括多个磁隧道结（MTJ）和耦合在多个MTJ之间的共享存取晶体管和固定电位。单位单元中的多个MTJ中的每一个可以耦合到单独的编程电路和/或单独的读出放大器电路，使得它们可以被单独编程和/或单独感测。可以产生来自单独读出放大器的逻辑组合作为单位单元的输出。

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