专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2010088042A2 MEMORY HAVING NEGATIVE VOLTAGE WRITE ASSIST CIRCUIT AND METHOD THEREFOR 审中-公开
标题翻译：具有负电压写入辅助电路的存储器及其方法
公开(公告)号：WO2010088042A2
公开(公告)日：2010-08-05
申请号：PCT/US2010020852
申请日：2010-01-13
申请人： FREESCALE SEMICONDUCTOR INC , KENKARE PRASHANT U , COOPER TROY L
发明人： KENKARE PRASHANT U , COOPER TROY L
IPC分类号： G11C11/416 , G11C5/14 , G11C7/00 , G11C11/413
CPC分类号： G11C11/419
摘要： A method of writing data to a selected column of a memory (10) includes selecting a first column. The data writing is initiated by applying a logic high to a first bit line (BL0) of the first column and a first potential to a second bit line (BLB0) of the first column that is lower than the logic high. The first potential is removed and a second potential is applied to the second bit line. The second potential is less than the first potential. The first potential may be ground (VSS), and the second potential may be a negative voltage (VNEG). Reducing the write voltage for the bit line that is receiving a logic low improves its ability to be written. By first bringing the logic low to the first potential, which may be ground, and then further reducing the applied voltage, the requirements on the source of the second potential are reduced.
摘要翻译：将数据写入存储器（10）的选定列的方法包括选择第一列。通过对第一列的第一位线（BL0）施加逻辑高电平并将第一电位施加到低于逻辑高电平的第一列的第二位线（BLB0）来启动数据写入。第一电位被去除并且第二电位被施加到第二位线。第二个潜力小于第一个潜力。第一电位可以接地（VSS），第二电位可以是负电压（VNEG）。降低接收逻辑低电平的位线的写入电压提高了写入能力。首先将逻辑低电位置于可能被理解的第一电位，然后进一步降低施加电压，降低对第二电位源的要求。

2. 发明申请

WO2010027550A1 CIRCUIT AND METHOD FOR OPTIMIZING MEMORY SENSE AMPLIFIER TIMING 审中-公开
标题翻译：用于优化存储器感测放大器时序的电路和方法
公开(公告)号：WO2010027550A1
公开(公告)日：2010-03-11
申请号：PCT/US2009/048774
申请日：2009-06-26
申请人： FREESCALE SEMICONDUCTOR INC. , BURNETT, James, D. , HOEFLER, Alexander, B.
发明人： BURNETT, James, D. , HOEFLER, Alexander, B.
IPC分类号： G11C7/06 , G11C7/08 , G11C11/413 , G11C11/416
CPC分类号： G11C29/02 , G11C7/04 , G11C7/08 , G11C7/14 , G11C7/22 , G11C11/41 , G11C29/023 , G11C29/026 , G11C29/028
摘要： A memory (10) has an array of memory cells (12, 16, 18), a word line driver (36), a sense amplifier (46), and a sense enable circuit (50). Each memory cell has a coupling transistor (20, 22) for coupling a storage portion (26, 28, 30, 32) to a bit line (BL). The coupling transistors have an average threshold voltage and a maximum threshold voltage. The word line driver (36) is coupled to the array and is for enabling a selected row of memory cells in the array. The sense amplifier (46) detects a state of a memory cell (12) in the selected row (WLB) in response to a sense enable signal. The sense enable circuit provides the sense enable signal at a time based on the maximum threshold voltage. This timing enables the sense amplifier (46) sufficiently late for low temperature operation while providing for faster operation at high temperature than would normally be achieved using just the average threshold voltage in providing timing of the sense enable signal.
摘要翻译：存储器（10）具有存储器单元阵列（12,16,18），字线驱动器（36），读出放大器（46）和感测使能电路（50）。每个存储单元具有用于将存储部分（26,28,30,32）耦合到位线（BL）的耦合晶体管（20,22）。耦合晶体管具有平均阈值电压和最大阈值电压。字线驱动器（36）耦合到阵列，并且用于使能阵列中的选定行的存储器单元。感测放大器（46）响应于感测使能信号来检测所选行（WLB）中的存储器单元（12）的状态。感测使能电路基于最大阈值电压一次提供感测使能信号。该定时使得读出放大器（46）能够在低温操作期间足够晚，同时在提供在提供感测使能信号的定时时通常仅通过平均阈值电压实现的在高温下的操作更快。

3. 发明申请

WO2016126478A1 APPARATUSES AND METHODS FOR MEMORY DEVICE AS A STORE FOR PROGRAM INSTRUCTIONS 审中-公开
标题翻译：作为程序指令存储的存储器件的装置和方法
公开(公告)号：WO2016126478A1
公开(公告)日：2016-08-11
申请号：PCT/US2016/015059
申请日：2016-01-27
申请人： MICRON TECHNOLOGY, INC.
发明人： ZAWODNY, Jason T. , WHEELER, Kyle B. , MURPHY, Richard C.
IPC分类号： G11C7/06 , G11C11/413 , G11C11/416
CPC分类号： G06F12/0238 , G06F12/0888 , G06F15/7821 , G06F2212/202 , G06F2212/603 , G11C7/06 , G11C7/065 , G11C7/1006 , G11C7/1036 , G11C8/12 , G11C11/4087 , G11C11/4096
摘要： The present disclosure includes apparatuses and methods related to a memory device as the store to program instructions. An example apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller, coupled to the array and the sensing circuitry is configured to receive a block of instructions including a plurality of program instructions. The memory controller is configured to store the block of instructions in the array and retrieve program instructions to perform logical operations on the compute component.
摘要翻译：本公开包括与作为用于编程指令的存储器的存储器件相关的装置和方法。示例性装置包括具有存储器单元阵列和耦合到阵列的感测电路的存储器件。感测电路包括读出放大器和被配置为实现逻辑运算的计算组件。耦合到阵列和感测电路的存储器控制器被配置为接收包括多个程序指令的指令块。存储器控制器被配置为将指令块存储在阵列中并检索程序指令以对计算组件执行逻辑运算。

4. 发明申请

WO2011087597A3 REDUCED AREA MEMORY ARRAY BY USING SENSE AMPLIFIER AS WRITE DRIVER 审中-公开
标题翻译：通过使用SENSE AMPLIFIER作为驱动器来减少区域存储阵列
公开(公告)号：WO2011087597A3
公开(公告)日：2011-11-03
申请号：PCT/US2010058339
申请日：2010-11-30
申请人： INTEL CORP , HAMZAOGLU FATIH , ZHANG KEVIN
发明人： HAMZAOGLU FATIH , ZHANG KEVIN
IPC分类号： G11C11/413 , G11C11/416
CPC分类号： G11C11/412 , G11C11/413
摘要： Techniques are disclosed for reducing area needed for implementing a memory array, such as SRAM arrays. The techniques may be embodied, for example, in a memory array design that includes a sense amplifier configured to operate in a reading mode for readout of memory cells and a writing mode for writing to memory cells. In addition, a common column multiplexer can be used for both read and write functions (as opposed to having separate multiplexers for reading and writing).
摘要翻译：公开了用于减小实现存储器阵列（例如SRAM阵列）所需的面积的技术。这些技术可以例如在存储器阵列设计中体现，该存储器阵列设计包括被配置为以用于读出存储器单元的读取模式和用于写入存储器单元的写入模式来操作的读出放大器。此外，共同的列多路复用器可用于读取和写入功能（与具有用于读取和写入的单独多路复用器相反）。

5. 发明申请

WO2010088042A3 MEMORY HAVING NEGATIVE VOLTAGE WRITE ASSIST CIRCUIT AND METHOD THEREFOR 审中-公开
公开(公告)号：WO2010088042A3
公开(公告)日：2010-08-05
申请号：PCT/US2010/020852
申请日：2010-01-13
申请人： FREESCALE SEMICONDUCTOR INC. , KENKARE, Prashant U. , COOPER, Troy L.
发明人： KENKARE, Prashant U. , COOPER, Troy L.
IPC分类号： G11C11/416 , G11C11/413 , G11C5/14 , G11C7/00
摘要： A method of writing data to a selected column of a memory (10) includes selecting a first column. The data writing is initiated by applying a logic high to a first bit line (BL0) of the first column and a first potential to a second bit line (BLB0) of the first column that is lower than the logic high. The first potential is removed and a second potential is applied to the second bit line. The second potential is less than the first potential. The first potential may be ground (VSS), and the second potential may be a negative voltage (VNEG). Reducing the write voltage for the bit line that is receiving a logic low improves its ability to be written. By first bringing the logic low to the first potential, which may be ground, and then further reducing the applied voltage, the requirements on the source of the second potential are reduced.

6. 发明申请

WO2017176217A1 CIRCUIT ARRANGEMENT, MEMORY COLUMN, MEMORY ARRAY, AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：电路布置，存储器列，存储器阵列以及形成它们的方法
公开(公告)号：WO2017176217A1
公开(公告)日：2017-10-12
申请号：PCT/SG2017/050199
申请日：2017-04-07
申请人： AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
发明人： DO, Anh Tuan , FONG, Xuanyao , ZHOU, Jun , LIU, Xin , HAN, Michael Kim Kwong
IPC分类号： G11C11/15 , G11C11/416 , G11C11/16 , H01L27/105 , H01L43/08
摘要： Various embodiments may provide a circuit arrangement. The circuit arrangement may include a first and a second memory element each having a first electrode and a second electrode, a first access transistor having a first controlled electrode connected to the second electrode of the first memory element, a second access transistor having a first controlled electrode connected to the first electrode of the second memory element, a first bit line connected to the first electrode of the first memory element, and a second bit line connected to the second electrode of the second memory element, wherein current flows of same direction in the first and second memory elements would provide complementary logic states in the first and second memory elements, respectively.
摘要翻译：各种实施例可以提供电路布置。该电路装置可以包括第一和第二存储元件，每个存储元件具有第一电极和第二电极，第一存取晶体管具有连接到第一存储元件的第二电极的第一受控电极，第二存取晶体管具有第一受控连接到第二存储器元件的第一电极的第一位线，连接到第一存储器元件的第一电极的第一位线以及连接到第二存储器元件的第二电极的第二位线，其中电流在第一和第二存储器元件将分别在第一和第二存储器元件中提供互补的逻辑状态。

7. 发明申请

WO2013147848A1 MEMORY CELL WITH IMPROVED WRITE MARGIN 审中-公开
标题翻译：具有改进的写字符的存储单元
公开(公告)号：WO2013147848A1
公开(公告)日：2013-10-03
申请号：PCT/US2012/031455
申请日：2012-03-30
申请人： WANG, Yih , KHELLAH, Muhammad M. , HAMZAOGLU, Fatih , INTEL CORPORATION
发明人： WANG, Yih , KHELLAH, Muhammad M. , HAMZAOGLU, Fatih
IPC分类号： G11C7/10 , G11C7/22 , G11C5/14 , G11C11/416
CPC分类号： G11C11/419 , G11C5/14 , G11C5/147 , G11C5/148 , G11C11/4074 , G11C11/412 , G11C11/413 , G11C11/417
摘要： Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption..
摘要翻译：描述了一种用于改善存储器单元中的写入裕度的装置和系统。在一个实施例中，该装置包括：提供具有宽度的脉冲信号的第一电路; 以及第二电路，用于接收所述脉冲信号并产生用于所述存储器单元的电源，其中所述第二电路将所述电源的电平降低到所述存储单元的数据保持电压电平以下一段对应于所述宽度的时间段的脉冲信号。在一个实施例中，该装置包括具有高供应节点和低供应节点的一列存储器单元; 以及位于存储单元列中的电荷共享电路，电荷共享电路耦合到高电源节点和低电源节点，电荷共享电路可操作以减少直流（DC）功率消耗。

8. 发明申请

WO1991007757A1 SENSE AMPLIFIER CONTROL CIRCUIT 审中-公开
标题翻译：感应放大器控制电路
公开(公告)号：WO1991007757A1
公开(公告)日：1991-05-30
申请号：PCT/JP1990001524
申请日：1990-11-21
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED , SEKI, Teruo
发明人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
IPC分类号： G11C11/416
CPC分类号： H03K19/0016 , G05F3/20 , G11C7/062 , H03K5/2436
摘要： A circuit for controlling operation/non-operation of a sense amplifier, which does not cause the operation speed of the sense amplifier to decrease yet maintaining correct and error-free operation, and which has a structure suited to higher integration. Sense amplifiers controlled by the control circuits are of a type comprising a pair of differential transistors and a transistor serving as a constant current source and connected to a common connection point of the differential transistors. A control means of the control circuit generates a constant current source control signal in response to a control signal representing instruction of operation/non-operation of the differential amplification of the paired transistors.

9. 发明申请

WO2022232055A1 EMBEDDED MATRIX-VECTOR MULTIPLICATION EXPLOITING PASSIVE GAIN VIA MOSFET CAPACITOR FOR MACHINE LEARNING APPLICATION 审中-公开
公开(公告)号：WO2022232055A1
公开(公告)日：2022-11-03
申请号：PCT/US2022/026190
申请日：2022-04-25
申请人： UNIVERSITY OF SOUTHERN CALIFORNIA
发明人： CHEN, Shuo-Wei , RASUL, Rezwan
IPC分类号： G06N3/06 , G06N3/063 , G06N3/08 , G06N5/02 , G06N7/08 , G11C11/416
摘要： A compute in-memory architecture comprising multiple neurons is provided. Each neuron includes one or more storage compute cells, each of which includes a logic circuit configured to receive a multi-bit input and a weight. The weight is defined by one or more weight bits. The logic circuit is further configured to output a control voltage corresponding to logic 'HIGH' when XNOR operation between an input sign bit and a corresponding weight bit is 1 and a corresponding input magnitude bit is also 1. A first digital-to-analog converter is formed from a first MOSCAP group in electrical communication with the logic circuit. The first MOSCAP group includes a total number of MOSCAPs equal to input magnitude bit resolution times weight bit resolution. Characteristically, each MOSCAP in the first MOSCAP group has a first end that receives the control voltage, and a second end in electrical communication with a first summation line.

10. 发明申请

WO2022164659A1 QUASI-VOLATILE MEMORY WITH REFERENCE BIT LINE STRUCTURE 审中-公开
公开(公告)号：WO2022164659A1
公开(公告)日：2022-08-04
申请号：PCT/US2022/012521
申请日：2022-01-14
申请人： SUNRISE MEMORY CORPORATION
发明人： PETTI, Christopher J.
IPC分类号： G11C11/40 , G11C11/409 , G11C11/4097 , G11C11/416 , G11C11/419 , G11C7/12 , G11C7/22
摘要： A semiconductor memory device is implemented as strings of storage transistors, where the storage transistors in each string have drain terminals connected to a bit line and gate terminals connected to respective word lines. In some embodiments, the semiconductor memory device includes a reference bit line structure to provide a reference bit line signal for read operation. The reference bit line structure configures word line connections to provide a reference bit line to be used with a storage transistor being selected for read access. The reference bit line structure provides a reference bit line having the same electrical characteristics as an active bit line and is configured so that no storage transistors are selected when a word line is activated to access a selected storage transistor associated with the active bit line.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式