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1. 发明申请

WO2012054032A8 EMBEDDED WELLS MERGED PN/SCHOTTKY DIODE 审中-公开
公开(公告)号：WO2012054032A8
公开(公告)日：2012-04-26
申请号：PCT/US2010/053423
申请日：2010-10-20
申请人： MICROSEMI CORPORATION , ZHAO, Feng , ODEKIRK, Bruce , SDRULLA, Dumitru
发明人： ZHAO, Feng , ODEKIRK, Bruce , SDRULLA, Dumitru
IPC分类号： H01L21/329 , H01L29/872
摘要： A merged PN/Schottky diode is provided having a substrate of a first conductivity type and a grid of doped wells of the second conductivity type embedded in the substrate. A Schottky barrier metal layer makes a Schottky barrier contact with the surface of the substrate above the grid. Selected embedded wells in the grid may contact the Schottky barrier metal layer, while most embedded wells do not. The diode forward voltage drop is reduced for the same diode area with reverse blocking benefits similar to a conventional JBS structure.

2. 发明申请

WO2009039014A1 EDGE TERMINATION HIGH VOLTAGE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：边缘终端高压半导体器件
公开(公告)号：WO2009039014A1
公开(公告)日：2009-03-26
申请号：PCT/US2008/075891
申请日：2008-09-10
申请人： MICROSEMI CORPORATION , TSANG, Dah, Wen , SDRULLA, Dumitru , ZHANG, Jinshu
发明人： TSANG, Dah, Wen , SDRULLA, Dumitru , ZHANG, Jinshu
IPC分类号： H01L29/00
CPC分类号： H01L29/66712 , H01L21/761 , H01L29/0619 , H01L29/0638 , H01L29/0878 , H01L29/404 , H01L29/7811
摘要： High voltage semiconductor devices with high-voltage termination structures (100, 200, 300) are constructed on lightly doped substrates (12). Lightly doped p-type substrates (12) are particularly prone to depletion and inversion from positive charges, degrading the ability of associated termination structures to block high voltages. To improve the efficiency and stability of termination structures, second termination regions (23, 223, 323) of the same dopant type as the substrate (12), more heavily doped than the substrate (12) but more lightly doped than first termination regions (22), are positioned adjoining the first termination regions (22). The second termination regions raise the field threshold voltage where the surface is vulnerable and render the termination structure (110) substantially insensitive to positive charges at the surface. The use of higher dopant concentration in the gap region without causing premature avalanche is facilitated by only creating second termination regions (323) for regions lacking field plate (10) protection.
摘要翻译：具有高电压端接结构（100,200,300）的高电压半导体器件构造在轻掺杂衬底（12）上。轻掺杂的p型衬底（12）特别容易从正电荷中消耗和反转，降低了相关终端结构阻挡高电压的能力。为了提高端接结构的效率和稳定性，与衬底（12）相同的掺杂剂类型的第二端接区域（23,223,323）比衬底（12）掺杂更多，但比第一端接区域更轻掺杂 22）定位成邻接第一端接区域（22）。第二终端区域提高场表面易受伤害的场阈值电压，并使端接结构（110）对表面的正电荷基本不敏感。通过仅为缺少场板（10）保护的区域创建第二终止区域（323），便于在间隙区域中使用更高的掺杂剂浓度而不引起过早的雪崩。

3. 发明申请

WO2014204491A1 LOW LOSS SIC MOSFET 审中-公开
标题翻译：低损耗SIC MOSFET
公开(公告)号：WO2014204491A1
公开(公告)日：2014-12-24
申请号：PCT/US2013/047145
申请日：2013-06-21
申请人： MICROSEMI CORPORATION
发明人： SDRULLA, Dumitru , ODEKIRK, Bruce , VANDENBERG, Marc
IPC分类号： H01L29/78 , H01L29/16 , H01L29/423 , H01L29/10
CPC分类号： H01L29/7802 , H01L29/1095 , H01L29/1608 , H01L29/42368 , H01L29/66068 , H01L29/7395 , H01L29/7816
摘要： A Vertical Multiple Implanted Silicon Carbide Power MOSFET (VMIMOSFET) includes a first conductivity semiconductor substrate, a first conductivity semiconductor drift layer on the top of the substrate, a multitude of second conductivity layers implanted in the drift layer. The body layer is where the channel is formed. A first conductivity source layer is interspaced appropriately inside of the second conductivity layers. A gate oxide of a certain thickness and another oxide of a different thickness, a greater thickness than the gate oxide, placed in between the body layers but in such way that its shape does not distort the gate oxide in the channel. A charge compensated body layer of the second conductivity formed outside of the channel region and only at specific high electric field locations in the structure. The device and the manufacturing method deliver a power SiC MOSFET with increased frequency of operation and reduced switching losses.
摘要翻译：垂直多重注入碳化硅功率MOSFET（VMIMOSFET）包括第一导电半导体衬底，衬底顶部上的第一导电半导体漂移层，注入漂移层中的多个第二导电层。身体层是通道形成的地方。第一导电源层在第二导电层内适当地间隔开。具有一定厚度的栅极氧化物和不同厚度的另一种氧化物，比栅极氧化物更大的厚度，放置在主体层之间，但是使得其形状不使通道中的栅极氧化物变形。第二导电体的电荷补偿体层形成在沟道区域外部，并且仅在该结构中的特定高电场位置。该器件和制造方法提供功率SiC MOSFET，具有更高的工作频率和更低的开关损耗。

4. 发明申请

WO2014149047A1 SIC POWER VERTICAL DMOS WITH INCREASED SAFE OPERATING AREA 审中-公开
标题翻译： SIC功率垂直DMOS具有增加的安全操作区域
公开(公告)号：WO2014149047A1
公开(公告)日：2014-09-25
申请号：PCT/US2013/033330
申请日：2013-03-21
申请人： MICROSEMI CORPORATION
发明人： SDRULLA, Dumitru , ODEKIRK, Bruce , VANDERBERG, Marc
IPC分类号： H01L29/78 , H01L29/06 , H01L29/16
CPC分类号： H01L29/7802 , H01L29/0696 , H01L29/0878 , H01L29/1033 , H01L29/1095 , H01L29/1608 , H01L29/42368 , H01L29/66068 , H01L29/7803
摘要： A SiC Power Semiconductor device of the Field Effect Type (MOSFET, IGBT or the like) with "muted" channel conduction in some cells and with negative temperature coefficient of channel mobility, allowing an optimized thermal management of the cells for increased Safe Operating Area is described. Controlling the location of the Zero Temperature Crossover Point (ZTCP) in relationship to the drain current is achieved by the partition between the "active" and "inactive" ("muted") channels and by adjusting the mobility of the carriers in the channel for the temperature range of interest. The "Thermal management" is realized by surrounding the "active" cells/fingers with "inactive" ones and the "negative" feedback of the drain/collector current due to local increase of the gate bias is achieved by implementing in-situ "ballast" resistors inside of each source contact, among other possibilities.
摘要翻译：在一些电池中具有“静音”通道导通和沟道迁移率的负温度系数的场效应型（MOSFET，IGBT等）的SiC功率半导体器件，允许用于增加安全工作面积的电池的优化热管理是描述。通过“有源”和“无效”（“静音”）通道之间的分区，并通过调整通道中的载波的移动性来实现与漏极电流相关的零温度交叉点（ZTCP）的位置控制感兴趣的温度范围。 “热管理”是通过围绕“活动”电池/手指“无效”来实现的，并且由于栅极偏置的局部增加引起的漏极/集电极电流的“负”反馈是通过实施原位“镇流器 “每个源接触器内部的电阻，以及其他可能性。

5. 发明申请

WO2017135940A1 SIC TRANSIENT VOLTAGE SUPPRESSOR 审中-公开
标题翻译： SIC瞬态电压抑制器
公开(公告)号：WO2017135940A1
公开(公告)日：2017-08-10
申请号：PCT/US2016/016302
申请日：2016-02-03
申请人： MICROSEMI CORPORATION
发明人： SDRULLA, Dumitru , ODEKIRK, Bruce , WALTERS, Cecil, Kent
IPC分类号： H01L29/872 , H01L29/861 , H01L21/329 , H01L29/06 , H01L29/16 , H01L29/40
CPC分类号： H01L29/872 , H01L29/0615 , H01L29/0619 , H01L29/1608 , H01L29/402 , H01L29/6606 , H01L29/861
摘要： A high power, high current Unidirectional Transient Voltage Suppressor, formed on SiC starting material is disclosed. The device is structured to avalanche uniformly across the entire central part (active area) such that very high currents can flow while the device is reversely biased. Forcing the device to avalanche uniformly across designated areas is achieved in different ways but consistently in concept, by creating high electric fields where the device is supposed to avalanche (namely the active area) and by relaxing the electric field across the edge of the structure (namely in the termination), which in all embodiments meets the conditions for an increased reliability under harsh environments.
摘要翻译：公开了在SiC起始材料上形成的高功率，高电流单向瞬态电压抑制器。该器件的结构在整个中央部分（有源区域）均匀地雪崩，从而在器件反向偏置时流过非常高的电流。强制设备在指定区域均匀雪崩的方式不同，但在概念上始终如一，通过在设备应该雪崩的地方产生高电场（即活动区域），并通过在结构边缘放宽电场（即在终止中），在所有实施例中，它们满足在恶劣环境下提高可靠性的条件。

6. 发明申请

WO2013177552A1 MONOLITHICALLY INTEGRATED SIC MOSFET AND SCHOTTKY BARRIER DIODE 审中-公开
标题翻译：单片集成SIC MOSFET和肖特基二极管二极管
公开(公告)号：WO2013177552A1
公开(公告)日：2013-11-28
申请号：PCT/US2013/042723
申请日：2013-05-24
申请人： MICROSEMI CORPORATION
发明人： SDRULLA, Dumitru , VANDENBERG, Marc, H. , ODEKIRK, Bruce
IPC分类号： H01L29/78 , H01L29/12 , H01L21/336
CPC分类号： H01L29/7806 , H01L21/8213 , H01L27/0629 , H01L29/1608 , H01L29/66212 , H01L29/66727 , H01L29/872
摘要： A SIC VDMOS transistor is integrated with a SiC SBD, in a seamless way, without any increase of the device area. The SiC SBD is integrated in the active area of the VDMOS by splitting the P- Wells, such that the lightly doped drift region extents all the way to the surface of semiconductor, and by trenching through the source of the VDMOS and partially through the P- Wells to reach the peak of the P-type doping in the P-Well regions. The source of the VDMOS is contacted from the top surface and from the vertical sidewalls of the trenched source and the forward voltage of the Schottky Barrier diode is tailored by using two different metals for the ohmic contact on the source and for the SBD.
摘要翻译： SIC VDMOS晶体管与SiC SBD以无缝的方式集成在一起，而不会增加器件面积。 SiC SBD通过分裂P阱而集成在VDMOS的有源区域中，使得轻掺杂漂移区域一直延伸到半导体的表面，并且通过挖沟通过VDMOS的源并部分地通过P - 在P阱区域达到P型掺杂的峰值。 VDMOS的源极从沟槽源的顶表面和垂直侧壁接触，肖特基势垒二极管的正向电压通过使用两种不同的金属来调节源极和SBD上的欧姆接触。

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